Electrostatic discharge (ESD) protection circuit and method of operating the same

Abstract

This application relates to electrostatic discharge (ESD) protection circuits and their operation methods. The integrated circuit includes a buffer circuit coupled between a first node and a second node, input / output (I / O) pads coupled to the buffer circuit, a first clamping circuit coupled between the I / O pads and the second node, and a second clamping circuit coupled between the I / O pads and the first node. The buffer circuit is configured to output a first signal to the I / O pads. The first clamping circuit is configured to clamp a first ESD event at either the I / O pads or the second node. The second clamping circuit is configured to clamp a second ESD event at either the I / O pads or the first node.

Description

Technical Field

[0001] none Prior Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has enabled smaller devices that consume less power but provide more functionality at higher speeds. Due to various factors, such as thinner dielectric thickness and the associated lower dielectric breakdown voltage, miniaturization processes also make devices more susceptible to electrostatic discharge (ESD) events. ESD is one of the causes of damage to electronic circuits and is a consideration in advanced semiconductor technologies. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to explain the technical solutions of the embodiments disclosed herein. Figure 1A is a schematic block diagram of an integrated circuit according to some embodiments. Figure 1B is a schematic block diagram of an integrated circuit according to some embodiments. Figure 2A is a circuit diagram of an integrated circuit according to some embodiments. Figure 2B is a circuit diagram of an integrated circuit according to some embodiments. Figure 3A is a circuit diagram of an integrated circuit according to some embodiments. Figure 3B is a circuit diagram of an integrated circuit according to some embodiments. Figure 4A is a circuit diagram of an integrated circuit according to some embodiments. Figure 4B is a circuit diagram of an integrated circuit according to some embodiments. Figure 5A is a circuit diagram of an integrated circuit according to some embodiments. Figure 5B is a circuit diagram of an integrated circuit according to some embodiments. Figure 6 is a diagram of a circuit according to some embodiments. Figures 7A to 7G are corresponding block diagrams of corresponding resistor networks according to some embodiments. Figure 8A is a diagram of an integrated circuit according to some embodiments. Figure 8B is a diagram of an integrated circuit according to some embodiments. Figures 8C to 8D are corresponding cross-sectional views of integrated circuits according to some embodiments. Figure 9 is a circuit diagram according to some embodiments. Figure 10 is a flowchart of a method for operating an ESD circuit according to some embodiments. Figure 11 is a functional flowchart of a method for manufacturing an IC device according to some embodiments. Figure 12 is a flowchart of a method for forming or manufacturing an integrated circuit according to some embodiments. Figure 13 is a flowchart of a method for generating layout design of integrated circuits according to some embodiments. Figure 14 is a schematic diagram of a system for designing IC layout and manufacturing IC circuits according to some embodiments. Figure 15 is a block diagram of an integrated circuit (IC) manufacturing system and an associated IC manufacturing process according to at least one embodiment of the present disclosure. Implementation

[0005] The following disclosure provides various embodiments or examples for implementing the features of the provided subject matter. Specific examples of elements, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. These are, of course, examples and not limitations. Other elements, materials, values, steps, arrangements, etc., are to be considered. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially related terms (e.g., “below,” “under,” “lower,” “above,” “higher,” etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0007] In some embodiments, the integrated circuit includes a buffer circuit. In some embodiments, the buffer circuit is coupled between a first node and a second node.

[0008] In some embodiments, the integrated circuitry further includes input / output (I / O) pads. In some embodiments, the I / O pads are coupled to a buffer circuit. In some embodiments, the buffer circuitry is configured to output a first signal to the I / O pads.

[0009] In some embodiments, the integrated circuit further includes a first clamping circuit. In some embodiments, the first clamping circuit is coupled between an I / O pad and a second node. In some embodiments, the first clamping circuit is configured to clamp a first electrostatic discharge (ESD) event at the I / O pad or the second node.

[0010] In some embodiments, the integrated circuit further includes a second clamping circuit. In some embodiments, the second clamping circuit is coupled between the I / O pad and the first node. In some embodiments, the second clamping circuit is configured to clamp a second ESD event at the I / O pad or the first node.

[0011] In some embodiments, the first clamping circuit includes a first ESD detection circuit. In some embodiments, the first ESD detection circuit is coupled between the IO pad and the second node.

[0012] In some embodiments, the second clamping circuit includes a second ESD detection circuit. In some embodiments, the second ESD detection circuit is coupled between the IO pad and the first node.

[0013] Compared with other methods, the integrated circuit of this disclosure has better ESD discharge capability and performance, while occupying a smaller area.

[0014] Figure 1A is a schematic block diagram of an integrated circuit 100A according to some embodiments.

[0015] The integrated circuit 100A includes internal circuitry 102, voltage source node 104, reference voltage source node 106, input / output (IO) pads 108, voltage source rails 109, head circuitry 110, power clamps 112 and 114, capacitor C1, buffer circuitry 116, ESD clamps 120 and 130.

[0016] In some embodiments, at least one or more of the integrated circuits 100A, 100B (FIG. 1B), 200A to 200B (FIG. 2A to 2B), 300A to 300B (FIG. 3A to 3B), 400A to 400B (FIG. 4A to 4B), 500A to 500B (FIG. 5A to 5B), 600 (FIG. 6), 700A to 700G (FIG. 7A to 7G), 800 (FIG. 8A to 8D), or 900 (FIG. 9) are incorporated on a single integrated circuit (IC) or a single semiconductor substrate. In some embodiments, the integrated circuits 100A, 100B (FIG. 1B), 200A to 200B (FIG. 2A to 2B), 300A to 300B (FIG. 3A to 3B), 400A to 400B (FIG. 4A to 4B), 500A to 500B (FIG. 5A to 5B), 600 (FIG. 6), 700A to 700G (FIG. 7A to 7G), 800 (FIG. 8A to 8D), or 900 (FIG. 9) include at least one or more ICs integrated on one or more single semiconductor substrates.

[0017] Internal circuitry 102 is coupled to I / O pad 108 via buffer circuitry 116. Internal circuitry 102 is configured to output signal VB to buffer circuitry 116. Buffer circuitry 116 is configured to output signal Vout to I / O pad 108. In some embodiments, signal Vout is inverted compared to signal VB. In some embodiments, at least one of signal VB or signal Vout is an I / O signal. In some embodiments, the positions of internal circuitry 102 and I / O pad 108 are interchanged. In some embodiments, internal circuitry 102 is configured to receive an I / O signal (e.g., Vout) from I / O pad 108.

[0018] In some embodiments, internal circuitry 102 is coupled to voltage source node 104 (e.g., TVDD) and reference voltage source node 106 (e.g., VSS). In some embodiments, internal circuitry 102 is configured to receive a supply voltage TVDD from voltage source node 104 (e.g., TVDD) and a reference voltage VSS from reference voltage source node 106 (e.g., VSS).

[0019] In some embodiments, internal circuitry 102 is coupled to voltage source rail 109 (e.g., VDD) and reference voltage source node 106 (e.g., VSS). In some embodiments, internal circuitry 102 is configured to receive a virtual supply voltage VDD from voltage source rail 109 (e.g., VDD) and a reference voltage VSS from reference voltage source node 106 (e.g., VSS).

[0020] Internal circuitry 102 includes circuitry configured to generate a signal VB that is output to buffer circuitry 116. In some embodiments, internal circuitry 102 includes circuitry configured to process one or more IO signals (e.g., Vout) received from IO pads 108.

[0021] In some embodiments, the internal circuitry 102 includes core circuitry configured to operate at the power supply voltage TVDD of the voltage source node 104 or the power supply voltage VDD of the voltage source rail 109. In some embodiments, the internal circuitry 102 includes core circuitry configured to operate at a voltage lower than the power supply voltage TVDD of the voltage source node 104 or the power supply voltage VDD of the voltage source rail 109. In some embodiments, the internal circuitry 102 includes at least one n-type or p-type transistor device. In some embodiments, the internal circuitry 102 includes at least logic gate units. In some embodiments, logic gate units include AND, OR, NAND, NOR, XOR, INV, AND-OR-NOT (AOI), OR-AND-NOT (OAI), MUX, flip-flops, BUFFs, latches, delay, or clock units. In some embodiments, the internal circuitry 102 includes at least memory units. In some embodiments, memory units include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), or read-only memory (ROM). In some embodiments, the internal circuitry 102 includes one or more active or passive components. Examples of active components include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, MOSFETs, CMOS transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, and planar MOS transistors with convex source / drain electrodes. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0022] Other configurations, number of devices, or types of devices in the internal circuitry 102 are within the scope of this disclosure.

[0023] Voltage source node 104 is coupled to power clamp 112 and header circuit 110. Reference voltage source node 106 is coupled to power clamp 112, power clamp 114, capacitor C1 and ESD clamp 120.

[0024] Voltage source node 104 is configured to receive a power supply voltage TVDD for normal operation of internal circuitry 102. Similarly, reference voltage source node 106 is configured to receive a reference power supply voltage VSS for normal operation of internal circuitry 102. Voltage source rail 109 is configured to receive a dummy power supply voltage (e.g., power supply voltage VDD) for normal operation of internal circuitry 102. In some embodiments, at least voltage source node 104 is a voltage source pad. In some embodiments, at least voltage source rail 109 is a voltage source pad. In some embodiments, at least reference voltage source node 106 is a reference voltage source pad. In some embodiments, the pad is at least a conductive surface, pin, node, or bus. Voltage source node 104 or reference voltage source node 106 is also referred to as a power supply voltage bus or rail. In some embodiments, voltage source rail 109 is also referred to as a dummy voltage source pad. In the example configurations shown in Figures 1A-1B, 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6, 7A-7G, 8A-8D, or 9, the power supply voltage TVDD is a positive power supply voltage, voltage source node 104 is a positive power supply voltage, the power supply voltage VDD is a positive power supply voltage, voltage source rail 109 is a positive power supply voltage, the reference power supply voltage VSS is a ground power supply voltage, and the reference voltage source node 106 is a ground voltage terminal. Other power supply configurations are within the scope of this disclosure.

[0025] The buffer circuit 116 is coupled to the internal circuit 102, voltage source rail 109, reference voltage source node 106, IO pad 108, ESD clamp 120 and ESD clamp 130.

[0026] Buffer circuit 116 is configured to receive signal VB from internal circuit 102. Buffer circuit 116 is configured to output signal Vout to IO pad 108. In some embodiments, buffer circuit 108 is an IO buffer circuit. In some embodiments, buffer circuit 108 is an inverter.

[0027] The buffer circuit 116 includes an N-type metal-oxide-semiconductor (NMOS) transistor MN1 and a P-type metal-oxide-semiconductor (PMOS) transistor MP1.

[0028] Each of the first terminal of the power clamp 114, the first terminal of the capacitor C1, the voltage source rail 109, the source of the PMOS transistor MP1, the body of the PMOS transistor MP1, and the first terminal of the ESD clamp 130 is coupled together.

[0029] Each of the output terminal of internal circuit 102, the gate of PMOS transistor MP1, and the gate of NMOS transistor MN1 is coupled together.

[0030] Each of the following is coupled together: the second terminal of the power clamp 114, the second terminal of the capacitor C1, the reference voltage source node 106, the source of the NMOS transistor MN1, and the first terminal of the ESD clamp 120.

[0031] The drain of NMOS transistor MN1, the drain of PMOS transistor MP1, the second terminal of ESD clamp 130, the second terminal of ESD clamp 120, and IO pad 108 are each coupled together.

[0032] Other configurations, number of devices, or types of devices in the buffer circuit 116 are within the scope of this disclosure.

[0033] Capacitor C1 is coupled between voltage source rail 109 and reference voltage source node 106. In some embodiments, capacitor C1 is a transistor-coupled capacitor. For example, in some embodiments, capacitor C1 is a transistor having a drain and a source coupled together to form a transistor-coupled capacitor.

[0034] Other configurations, number of components, or types of components in capacitor C1 are within the scope of this disclosure.

[0035] IO pad 108 is coupled to buffer circuit 102, ESD clamp 120, and ESD clamp 130. IO pad 108 is configured to receive a signal Vout from buffer circuit 116. IO pad 108 is at least a pin coupled to internal circuitry 102. In some embodiments, IO pad 108 is a node, bus, or conductive surface coupled to internal circuitry 102.

[0036] Other configurations, device quantities, or device types in the IO pad 108 are within the scope of this disclosure.

[0037] The header circuit 110 is coupled between voltage source node 104 and voltage source rail 109.

[0038] The header circuit 110 is coupled to the voltage source node 104 and voltage source rail 109 of the voltage source TVDD. The header circuit 110 is configured to receive a first voltage from the first voltage source TVDD. In some embodiments, the first voltage source TVDD is referred to as true VDD (TVDD). In some embodiments, the first voltage source TVDD is a voltage source located outside of integrated circuit 100A or 100B. In some embodiments, the first voltage source TVDD is a voltage source located inside integrated circuit 100A or 100B.

[0039] The header circuit 110 is configured to receive a control signal GC (shown in FIG. 9). In some embodiments, the header circuit 110 is configured to be turned on or off based on the control signal GC. In some embodiments, the header circuit 110 is configured to be turned on and configured to supply voltage to the voltage source rail 109 (referred to as the virtual voltage source (VDD) or the second voltage source VDD). The first voltage of the first power supply voltage TVDD is the same as the second voltage of the second power supply voltage VDD. In some embodiments, the first voltage of the first power supply voltage TVDD is different from the second voltage of the second power supply voltage VDD.

[0040] The header circuit 110 is configured to provide a second voltage to the voltage source rail 109 in response to the control signal GC. The header circuit 110 is configured to gate the power supplied to the integrated circuit 100A or 100B.

[0041] In some embodiments, based on different power states of integrated circuits 100A or 100B, the header circuit 110 is configured to turn on in response to a control signal GC, thereby supplying power to the voltage source rail 109 of integrated circuits 100A or 100B; or the header circuit 110 is configured to turn off in response to a control signal GC, thereby cutting off the power supplied to the voltage source rail 109. For example, when integrated circuits 100A or 100B are in a sleep mode or standby mode, the header circuit 110 is configured to be turned off, thereby cutting off the power supplied to integrated circuits 100A or 100B. For example, when integrated circuits 100A or 100B are in an active mode, the header circuit 110 is configured to be turned on, thereby supplying power to integrated circuits 100A or 100B. In some embodiments, the control signal GC is received from a power management controller circuit (not shown). The header circuit 110 is configured to reduce leakage current in the integrated circuit 100A or 100B, and thus reduce the power consumed by the integrated circuit 100A or 100B.

[0042] In some embodiments, the second voltage of the second voltage source VDD is referred to as the gated power (e.g., VDD) from the header circuit 110. In some embodiments, the first voltage of the first voltage source TVDD is referred to as the anti-gated power (e.g., TVDD).

[0043] In some embodiments, the header circuit 110 is not included in the integrated circuit 100A or 100B. In these embodiments, the voltage source node 104 is directly coupled to the voltage source rail 109. In these embodiments, the voltage source node 104 and the voltage source rail 109 are part of the same structure. In these embodiments, at least one of the power clamp 112 or the power clamp 114 is not included.

[0044] Other configurations, number of devices, or types of devices in the header circuit 110 are within the scope of this disclosure.

[0045] A power clamp 112 is coupled between voltage source node 104 and reference voltage source node 106. In some embodiments, the power clamp 112 is configured to absorb direct ESD stress between voltage source node 104 and reference voltage source node 106, thereby protecting integrated circuit 100A or 100B from one or more ESD events. In some embodiments, the power clamp 112 is configured to provide a current path between a power pad (e.g., voltage source node 104) and a ground pad (e.g., reference voltage source node 106) during one or more ESD events.

[0046] In some embodiments, the power clamp 112 includes one or more NMOS or PMOS transistors configured as clamping circuits. In some embodiments, the power clamp 112 includes one or more diodes configured as clamping circuits. In some embodiments, the power clamp 112 includes one or more of NMOS transistors, PMOS transistors, diodes, resistors, or capacitors. In some embodiments, the power clamp 112 further includes one or more trigger circuits. In some embodiments, the power clamp 112 includes a controlled silicon rectifier (SCR) device.

[0047] Other configurations, number of devices, or types of devices in the power clamp 112 are within the scope of this disclosure.

[0048] A power clamp 114 is coupled between a voltage source rail 109 and a reference voltage source node 106. In some embodiments, the power clamp 114 is configured to absorb direct ESD stress between the voltage source rail 109 and the reference voltage source node 106, thereby protecting the integrated circuit 100A from one or more ESD events. In some embodiments, the power clamp 114 is configured to provide a current path between the voltage source rail 109 and a ground pad (e.g., the reference voltage source node 106) during one or more ESD events.

[0049] In some embodiments, the power clamp 114 includes one or more NMOS or PMOS transistors configured as clamping circuits. In some embodiments, the power clamp 114 includes one or more diodes configured as clamping circuits. In some embodiments, the power clamp 114 includes one or more of NMOS transistors, PMOS transistors, diodes, resistors, or capacitors. In some embodiments, the power clamp 114 further includes one or more trigger circuits. In some embodiments, the power clamp 114 includes a controlled silicon rectifier (SCR) device.

[0050] Other configurations, number of devices, or types of devices in the power clamp 114 are within the scope of this disclosure.

[0051] The header circuit 110 is coupled between the voltage source node 104 and the IO pad 108. The anode of the header circuit 110 is coupled to the cathode of the internal circuit 102, the IO pad 108, and the power clamp 112. The cathode of the header circuit 110 is coupled to the voltage source node 104 and the ESD clamp 120. In some embodiments, the header circuit 110 is a pull-up diode, also referred to as a p+ diode. For example, in these embodiments, the p+ diode is formed between a p-well region (not shown) and an n-well region (not shown), and the n-well region is connected to VDD.

[0052] A power clamp 112 is coupled between a reference voltage source node 106 and an IO pad 108. The anode of the power clamp 112 is coupled to the reference voltage source node 106 and the ESD clamp 120. The cathode of the power clamp 112 is coupled to the anode of the internal circuitry 102, the IO pad 108, and the header circuitry 110. In some embodiments, the power clamp 112 is a pull-down diode, also referred to as an n+ diode. For example, in these embodiments, the n+ diode is formed between an n+ junction (not shown) and a p-substrate (not shown), and the p-substrate is connected to ground or VSS.

[0053] The header circuit 110 and the power clamp 112 are configured to have minimal impact on the normal behavior of the internal circuit 102 or the integrated circuit 100A (e.g., in the absence of ESD conditions or events). In some embodiments, an ESD event occurs when an ESD voltage or current higher than the level expected during normal operation of the internal circuit 102 is applied to at least voltage source node 104, reference voltage source node 106, or IO pad 108.

[0054] ESD clamp 120 is coupled between IO pad 108 and reference voltage source node 106 (e.g., VSS). When no ESD event occurs, ESD clamp 120 is turned off. For example, when no ESD event occurs, ESD clamp 120 is turned off and therefore a non-conductive device or circuit during normal operation of internal circuitry 102. In other words, ESD clamp 120 is turned off or non-conductive when no ESD event occurs.

[0055] If an ESD event occurs, the ESD clamp 120 is configured to sense the ESD event and is configured to be turned on and provide a current shunt path between the IO pad 108 and the reference voltage source node 106 (e.g., VSS), thereby discharging the ESD current. For example, when an ESD event occurs, the voltage difference across the ESD clamp 120 is equal to or greater than the threshold voltage of the ESD clamp 120, and the ESD clamp 120 is turned on, thereby conducting current between the IO pad 108 and the reference voltage source node 106 (e.g., VSS).

[0056] During an ESD event, the ESD clamp 120 is configured to turn on and discharge the ESD current (I1 or I2) in either the forward ESD direction (e.g., current I1) or the reverse ESD direction (e.g., current I2). The forward ESD direction (e.g., current I1) is from the reference voltage source node 106 (e.g., VSS) to the IO pad 108. The reverse ESD direction (e.g., current I2) is from the IO pad 108 to the reference voltage source node 106 (e.g., VSS).

[0057] During a negative-to-VSS ESD surge, ESD clamp 120 is configured to turn on and discharge ESD current I1 in the positive ESD direction from reference voltage source node 106 (e.g., VSS) to IO pad 108, and this is referred to as the negative-to-VSS (NS) mode. In some embodiments, ESD clamp 120 is configured to turn on after the NS mode of the ESD and discharge ESD current I1 in the positive ESD direction from reference voltage source node 106 (e.g., VSS) to IO pad 108.

[0058] During a positive-to-VSS ESD surge on the IO pad 108, the ESD clamp 120 is configured to turn on and discharge the ESD current I2 in the reverse ESD direction from the IO pad 108 to the reference voltage source node 106 (e.g., VSS), and this is referred to as the positive-to-VSS (PS) mode. In some embodiments, the ESD clamp 120 is configured to turn on after the ESD PS mode, and the ESD clamp 120 is configured to discharge the ESD current I2 in the reverse ESD direction from the IO pad 108 to the reference voltage source node 106 (e.g., VSS).

[0059] In some embodiments, ESD clamp 120 is a transient clamp. For example, in some embodiments, ESD clamp 120 is configured to handle transient or fast ESD events, such as rapid changes in voltage and / or current caused by an ESD event. During a transient or fast ESD event, ESD clamp 120 is configured to turn on very quickly to provide a shunt path between IO pad 108 and reference voltage source node 106 (e.g., VSS) before the ESD event could damage one or more components within integrated circuit 100A or 100B. In some embodiments, ESD clamp 120 is configured to turn off more slowly than it turns on.

[0060] In some embodiments, the ESD clamp 120 is a static clamp. In some embodiments, the static clamp is configured to provide a static or steady-state voltage and current response. For example, the static clamp is turned on at a fixed voltage level.

[0061] Other types of clamping circuitry, configurations, and arrangements of the ESD clamper 120 are within the scope of this disclosure.

[0062] ESD clamp 130 is coupled between IO pad 108 and voltage source rail 109 (e.g., VDD). When no ESD event occurs, ESD clamp 130 is turned off. For example, when no ESD event occurs, ESD clamp 130 is turned off and therefore a non-conductive device or circuit during normal operation of internal circuitry 102. In other words, ESD clamp 130 is turned off or non-conductive when no ESD event occurs.

[0063] If an ESD event occurs, the ESD clamp 130 is configured to sense the ESD event and is configured to turn on and provide a current shunt path between the IO pad 108 and the voltage source rail 109 (e.g., VDD), thereby discharging the ESD current. For example, when an ESD event occurs, the voltage difference across the ESD clamp 130 is equal to or greater than the threshold voltage of the ESD clamp 130, and the ESD clamp 130 is turned on, thereby conducting current between the IO pad 108 and the voltage source rail 109 (e.g., VDD).

[0064] During an ESD event, the ESD clamp 130 is configured to be turned on and discharge the ESD current (I3 or I4) in either the forward ESD direction (e.g., current I3) or the reverse ESD direction (e.g., current I4). The forward ESD direction (e.g., current I3) is from the IO pad 108 to the voltage source rail 109 (e.g., VDD). The reverse ESD direction (e.g., current I4) is from the voltage source rail 109 (e.g., VDD) to the IO pad 108.

[0065] During a positive-to-VDD (PD) ESD surge on the IO pad 108, the ESD clamp 130 is configured to turn on and discharge the ESD current I3 in the positive ESD direction from the IO pad 108 to the voltage source rail 109 (e.g., VDD), and this is referred to as the positive-to-VDD (PD) mode. In some embodiments, the ESD clamp 130 is configured to turn on after the PD mode of the ESD and discharge the ESD current I3 in the positive ESD direction from the IO pad 108 to the voltage source rail 109 (e.g., VDD).

[0066] During a negative-to-VDD (ND) ESD surge, ESD clamp 130 is configured to turn on and discharge ESD current I4 in the reverse ESD direction from voltage source rail 109 (e.g., VDD) to IO pad 108, and this is referred to as the negative-to-VDD (ND) mode. In some embodiments, ESD clamp 130 is configured to turn on after the ND mode of the ESD surge and discharge ESD current I4 in the reverse ESD direction from voltage source rail 109 (e.g., VDD) to IO pad 108.

[0067] In some embodiments, ESD clamp 130 is a transient clamp. For example, in some embodiments, ESD clamp 130 is configured to handle transient or fast ESD events, such as rapid changes in voltage and / or current caused by an ESD event. During a transient or fast ESD event, ESD clamp 130 is configured to turn on very quickly to provide a shunt path between IO pad 108 and voltage source rail 109 (e.g., VDD) before the ESD event could damage one or more components within integrated circuit 100A or 100B. In some embodiments, ESD clamp 130 is configured to turn off more slowly than it turns on.

[0068] In some embodiments, ESD clamp 130 is a static clamp. In some embodiments, a static clamp is configured to provide a static or steady-state voltage and current response. For example, a static clamp is turned on at a fixed voltage level.

[0069] Other types of clamping circuitry, configurations, and arrangements of the ESD clamper 130 are within the scope of this disclosure.

[0070] In some embodiments, ESD clamps 120 and 130 are referred to as local voltage clamping (LVC) circuits because the NS ESD mode, PS ESD mode, PD ESD mode, and ND ESD mode are considered locally, rather than being handled by other circuitry that generates long discharge paths. For example, a long discharge path in PS / ND mode includes header circuit 110, power clamp 114, and reference voltage source VSS.

[0071] Other configurations or quantities of circuits in integrated circuit 100A are within the scope of this disclosure.

[0072] In some embodiments, at least one of the integrated circuits 100A or 100B has better ESD discharge capability and performance than other methods, while occupying a smaller area and using fewer wiring resources.

[0073] Figure 1B is a schematic block diagram of an integrated circuit 100B according to some embodiments.

[0074] Integrated circuit 100B is a variant of integrated circuit 100A, therefore a similar detailed description is omitted. Compared to integrated circuit 100A, integrated circuit 100B does not include the power clamp 114, therefore a similar detailed description is omitted.

[0075] Elements that are the same as or similar to those in one or more of Figures 1A to 1B, 2A to 2B, 3A to 3B, 4A to 4B, 5A to 5B, 6, 7A to 7G, 8A to 8D or 9 (as shown below) are given the same reference numerals, and therefore their detailed descriptions are omitted.

[0076] The integrated circuit 100B includes internal circuitry 102, voltage source node 104, reference voltage source node 106, IO pads 108, voltage source rails 109, header circuitry 110, power clamp 112, capacitor C1, buffer circuitry 116, ESD clamp 120, and ESD clamp 130.

[0077] In some embodiments, by omitting the power clamp 114, the integrated circuit 100B occupies less area and uses fewer wiring resources than other methods.

[0078] In some embodiments, the integrated circuit 100B is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0079] Other configurations or quantities of circuits in integrated circuit 100B are within the scope of this disclosure.

[0080] Figure 2A is a circuit diagram of an integrated circuit 200A according to some embodiments.

[0081] The integrated circuit 200A is an embodiment of the ESD clamp 120, therefore a similar detailed description is omitted.

[0082] Node Nd2 in Figures 2A, 3A, 4A and 5A corresponds to node 106 of the reference voltage source in Figures 1A to 1B.

[0083] The integrated circuit 200A includes a set of diodes 202, resistors R1 and NMOS transistors N1.

[0084] A set of diodes 202 are located between the IO pad 108 and the node Nd3.

[0085] A set of diodes 202 includes at least diodes D1a, D2a, or D3a coupled together in series. In some embodiments, each diode in the set of diodes 202 has the same threshold voltage. In some embodiments, at least one diode in the set of diodes 202 has a different threshold voltage than another diode in the set of diodes 202.

[0086] Each of the anode of diode D1a, IO pad 108, and drain of NMOS transistor N1 is coupled together. In some embodiments, each of the anode of diode D1a, IO pad 108, drain of NMOS transistor N1, and output of buffer circuit 116 is coupled together.

[0087] The cathode of diode D1a is coupled to the anode of diode D2a. The cathode of diode D2a is coupled to the anode of diode D3a.

[0088] Each of the cathode of diode D3a, node Nd3, the first terminal of resistor R1, and the gate of NMOS transistor N1 is coupled together.

[0089] In some embodiments, current I5 flows through a set of diodes 202.

[0090] In some embodiments, one or more of the diodes in a group of diodes 202 are the corresponding diode-coupled transistors as shown in FIG6.

[0091] Other numbers of diodes or threshold voltages in a set of diodes 202 are within the scope of this disclosure.

[0092] Resistor R1 is located between node Nd3 and reference voltage source node 106 (VSS). Resistor R1 has a first terminal and a second terminal.

[0093] Each of node Nd3, the second terminal of resistor R1, the source of NMOS transistor N1, and the reference voltage source node 106 (e.g., VSS) is coupled together. In some embodiments, each of the second terminal of resistor R1 and the source of NMOS transistor N1 is coupled to ground.

[0094] The other number of resistors R1 are within the scope of this disclosure.

[0095] In some embodiments, a set of diodes 202 and resistors R1 are referred to as "ESD detection circuit 201".

[0096] ESD detection circuit 201 is coupled between IO pad 108 and reference voltage source node 106 (or node Nd2).

[0097] ESD detection circuit 201 is configured to detect an ESD event at IO pad 108 (e.g., ESD current I2 or ESD current I1 in the reverse ESD direction) and, in response to the ESD event, charge node Nd3, thereby turning on NMOS transistor N1 (e.g., a discharge circuit). In some embodiments, in response to being turned on, NMOS transistor N1 (e.g., a discharge circuit) couples IO pad 108 and reference voltage source node 106 (or node Nd2), thereby providing an ESD discharge path between IO pad 108 and reference voltage source node 106 (or node Nd2).

[0098] The NMOS transistor N1 is located between the IO pad 108 and the reference voltage source node 106.

[0099] NMOS transistor N1 is a ground-gate NMOS (ggNMOS) transistor. NMOS transistor N1 includes a gate, drain, and source (not labeled).

[0100] In some embodiments, NMOS transistor N1 is referred to as a discharge circuit. In some embodiments, NMOS transistor N1 is configured to couple IO pad 108 and node Nd2 during an ESD event at IO pad 108 or node Nd2, thereby providing an ESD discharge path between IO pad 108 and node Nd2. In some embodiments, current IDS1 flows through NMOS transistor N1. In some embodiments, current IDS1 is at least one of currents I1 or I2 in integrated circuits 100A to 100B, therefore similar detailed descriptions are omitted.

[0101] In some embodiments, NMOS transistor N1 is replaced by more than one NMOS transistor. In some embodiments, NMOS transistor N1 is replaced by one or more PMOS transistors.

[0102] Other numbers of transistors or transistor types of NMOS transistor N1 are within the scope of this disclosure.

[0103] In some embodiments, a set of diodes 202 have a trigger voltage Vtrigger1.

[0104] In some embodiments, diode D1a has a threshold voltage Vth_d1a, diode D2a has a threshold voltage Vth_d2a, and diode D3a has a threshold voltage Vth_d3a. In some embodiments, the trigger voltage Vtrigger1 is equal to the sum of the threshold voltages of each of the diodes in the set 202 (e.g., Vth_d1a + Vth_d2a + Vth_d3a).

[0105] In some embodiments, where each diode in a set of diodes 202 has a substantially equal threshold voltage (e.g., Vth_d1a), the trigger voltage Vtrigger1 is equal to the product of the number of diodes in the set of diodes 202 (e.g., 3) and the threshold voltage of each diode in the set of diodes 202 (e.g., 3*Vth_d1a).

[0106] In some embodiments, when the voltage VESD of an ESD event is greater than the trigger voltage Vtrigger1, a set of diodes 202 is turned on, thus the integrated circuit 200A is configured to operate in ESD mode where the ESD event is discharged by the NMOS transistor N1. For example, when an ESD event occurs at the IO pad 108 (e.g., PS mode) (e.g., ESD current I2 or ESD current I1 in the reverse ESD direction), the ESD current or voltage at node Nd1 rises rapidly. In some embodiments, if the ESD voltage is greater than the trigger voltage of the set of diodes 202, the set of diodes 202 is turned on or becomes forward biased. In response to the turn-on or forward bias of the set of diodes 202, the voltage at node Nd3 (e.g., across resistor R1) rises rapidly. In response to the rapidly rising voltage at node Nd3, the gate of the NMOS transistor N1 is charged by the ESD detection circuit 201. In response to the charging by the ESD detection circuit 201, the NMOS transistor N1 of the discharge circuit is turned on and couples the IO pad 108 to node Nd2. By being turned on and coupled to node Nd2, the channel of the NMOS transistor N1 discharges the ESD current I2 in the reverse ESD direction from the IO pad 108 to node Nd2.

[0107] In some embodiments, when the voltage VESD of an ESD event is less than or equal to the trigger voltage Vtrigger1, a set of diodes 202 is turned off, and the integrated circuit 200A is configured to operate in a normal mode where no ESD event has occurred, thus turning off the NMOS transistor N1. For example, when no ESD event occurs at IO pad 108 (e.g., in normal mode), the voltage at IO pad 108 is less than the trigger voltage of the set of diodes 202, causing the set of diodes 202 to turn off. In response to the turn-off of the set of diodes 202, the voltage at node Nd3 is insufficient to turn on the NMOS transistor N1. In some embodiments, in response to the turn-off of the NMOS transistor N1, IO pad 108 and node Nd2 are electrically decoupled from each other. In some embodiments, when the voltage at node Nd3 is substantially equal to 0 V, the NMOS transistor N1 is turned off.

[0108] In some embodiments, the resistance of resistor R1 varies with process, voltage, and / or temperature (PVT). In some embodiments, because integrated circuit 200A is a self-biased adjustment circuit, it is able to overcome the resistance variation of R1, thereby enabling a more flexible design with better performance than other methods.

[0109] For example, in some embodiments, any fluctuations in the gate-to-source voltage VGS of the NMOS transistor N1 caused by changes in the resistance of resistor R1 are self-compensating. In some embodiments, as the resistance of resistor R1 increases, the gate-to-source voltage VGS of the NMOS transistor N1 begins to increase, which reduces the voltage Vout of the IO pad 108. In some embodiments, reducing the voltage Vout of the IO pad 108 reduces the current I5, which in turn reduces the gate-to-source voltage VGS of the NMOS transistor N1. Therefore, using integrated circuit 200A increases the resistance of resistor R1, resulting in a reduction in the self-compensating gate-to-source voltage VGS of the NMOS transistor N1.

[0110] In some embodiments, as the resistance of resistor R1 decreases, the gate-to-source voltage VGS of NMOS transistor N1 begins to decrease, which increases the voltage Vout of IO pad 108. In some embodiments, increasing the voltage Vout of IO pad 108 increases the current I5, which in turn increases the gate-to-source voltage VGS of NMOS transistor N1. Therefore, using integrated circuit 200A reduces the resistance of resistor R1, resulting in a self-compensating increase in the gate-to-source voltage VGS of NMOS transistor N1.

[0111] Other types of circuits, configurations, and arrangements of a set of diodes 202, resistors R1, or NMOS transistors N1 are within the scope of this disclosure.

[0112] In some embodiments, the integrated circuit 200A is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0113] Other configurations or quantities of circuits in the integrated circuit 200A are within the scope of this disclosure.

[0114] Figure 2B is a circuit diagram of an integrated circuit 200B according to some embodiments.

[0115] The integrated circuit 200B is an embodiment of the ESD clamp 130, therefore a similar detailed description is omitted.

[0116] In some embodiments, node Nd1 of Figures 2B, 3B, 4B and 5B corresponds to voltage source rail 109 (e.g., VDD) or voltage source node 104 of Figures 1A to 1B.

[0117] The integrated circuit 200B includes a set of diodes 212, resistors R2 and PMOS transistors P1.

[0118] A set of diodes 212 are located between the IO pad 108 and the node Nd4.

[0119] A set of diodes 212 includes at least diodes D1b, D2b, or D3b coupled together in series. In some embodiments, each diode in the set of diodes 212 has the same threshold voltage. In some embodiments, at least one diode in the set of diodes 212 has a different threshold voltage than another diode in the set of diodes 212.

[0120] Each of the anode of diode D1b, node Nd4, the first terminal of resistor R2, and the gate of PMOS transistor P1 is coupled together.

[0121] The cathode of diode D1b is coupled to the anode of diode D2b. The cathode of diode D2b is coupled to the anode of diode D3b.

[0122] Each of the anode of diode D3b, IO pad 108, and drain of PMOS transistor P1 is coupled together. In some embodiments, each of the anode of diode D3b, IO pad 108, drain of PMOS transistor P1, and output of buffer circuit 116 is coupled together. In some embodiments, each of the anode of diode D3b, IO pad 108, drain of PMOS transistor P1, anode of diode D1a, drain of NMOS transistor N1, and output of buffer circuit 116 is coupled together.

[0123] In some embodiments, current I6 flows through a set of diodes 212.

[0124] In some embodiments, one or more of the diodes in a group of diodes 212 are the corresponding diode-coupled transistors as shown in FIG6.

[0125] Other numbers of diodes or threshold voltages in a set of diodes 212 are within the scope of this disclosure.

[0126] Resistor R2 is located between node Nd4 and voltage source rail 109 (e.g., VDD). Resistor R2 has a first terminal and a second terminal.

[0127] Each of node Nd4, the second terminal of resistor R2, the source of PMOS transistor P1, and voltage source rail 109 (e.g., VDD) is coupled together. In some embodiments, each of the second terminal of resistor R2 and the source of PMOS transistor P1 is coupled to voltage source VDD.

[0128] The other number of resistors R2 are within the scope of this disclosure.

[0129] In some embodiments, a set of diodes 212 and resistors R2 are referred to as “ESD detection circuit 211”.

[0130] ESD detection circuit 211 is coupled between IO pad 108 and voltage source rail 109 (or node Nd1).

[0131] ESD detection circuit 211 is configured to detect an ESD event at IO pad 108 (e.g., ESD current I4 or ESD current I3 in the reverse ESD direction) and, in response to the ESD event, charge node Nd4, thereby turning on PMOS transistor P1 (e.g., a discharge circuit). In some embodiments, in response to being turned on, PMOS transistor P1 (e.g., a discharge circuit) couples IO pad 108 and voltage source rail 109 (or node Nd1), thereby providing an ESD discharge path between IO pad 108 and voltage source rail 109 (or node Nd1).

[0132] The PMOS transistor P1 is located between the IO pad 108 and the voltage source rail 109.

[0133] PMOS transistor P1 is a ground-gate PMOS (ggPMOS) transistor. PMOS transistor P1 includes a gate, drain, and source (not labeled).

[0134] In some embodiments, the PMOS transistor P1 is referred to as a discharge circuit. In some embodiments, the PMOS transistor P1 is configured to couple the IO pad 108 and node Nd1 during an ESD event at the IO pad 108 or node Nd1, thereby providing an ESD discharge path between the IO pad 108 and node Nd1. In some embodiments, a current IDS2 flows through the PMOS transistor P1. In some embodiments, the current IDS2 is at least one of the currents I3 or I4 of the integrated circuits 100A to 100B, therefore similar detailed descriptions are omitted.

[0135] In some embodiments, PMOS transistor P1 is replaced by more than one PMOS transistor. In some embodiments, PMOS transistor P1 is replaced by one or more NMOS transistors.

[0136] Other numbers of transistors or transistor types of PMOS transistor P1 are within the scope of this disclosure.

[0137] In some embodiments, a set of diodes 212 have a trigger voltage Vtrigger2.

[0138] In some embodiments, diode D1b has a threshold voltage Vth_D1b, diode D2b has a threshold voltage Vth_D2b, and diode D3b has a threshold voltage Vth_D3b. In some embodiments, the trigger voltage Vtrigger2 is equal to the sum of the threshold voltages of each of the diodes in the set 212 (e.g., Vth_D1b + Vth_D2b + Vth_D3b).

[0139] In some embodiments, where each diode in a set of diodes 212 has a substantially equal threshold voltage (e.g., Vth_D1b), the trigger voltage Vtrigger2 is equal to the product of the number of diodes in the set of diodes 212 (e.g., 3) and the threshold voltage of each diode in the set of diodes 212 (e.g., 3 * Vth_D1b).

[0140] In some embodiments, when the voltage VESD of an ESD event is greater than the trigger voltage Vtrigger2, a set of diodes 212 is turned on, thus the integrated circuit 200B is configured to operate in ESD mode where the ESD event is discharged by the PMOS transistor P1. For example, when an ESD event occurs at the IO pad 108 (e.g., ND mode) (e.g., ESD current I4 or ESD current I3 in the reverse ESD direction), the ESD current or voltage at node Nd1 rises rapidly. In some embodiments, if the ESD voltage is greater than the trigger voltage of the set of diodes 212, the set of diodes 212 is turned on or becomes forward biased. In response to the turn-on or forward bias of the set of diodes 212, the voltage at node Nd4 (e.g., across resistor R2) rises rapidly. In response to the rapidly rising voltage at node Nd4, the gate of the PMOS transistor P1 is charged by the ESD detection circuit 211. In response to the charging by the ESD detection circuit 211, the PMOS transistor P1 of the discharge circuit is turned on and couples the IO pad 108 to node Nd1. By being turned on and coupled to node Nd1, the channel of the PMOS transistor P1 discharges the ESD current I2 in the reverse ESD direction from node Nd1 to the IO pad 108.

[0141] In some embodiments, when the voltage VESD of an ESD event is less than or equal to the trigger voltage Vtrigger2, a set of diodes 212 is turned off, and thus the integrated circuit 200B is configured to operate in a normal mode where no ESD event has occurred, and therefore the PMOS transistor P1 is turned off. For example, when no ESD event occurs at IO pad 108 (e.g., normal mode), the voltage at IO pad 108 is less than the trigger voltage of the set of diodes 212, thereby causing the set of diodes 212 to be turned off. In response to the turn-off of the set of diodes 212, the voltage at node Nd4 is insufficient to turn on the PMOS transistor P1. In some embodiments, in response to the turn-off of the PMOS transistor P1, IO pad 108 and node Nd1 are electrically decoupled from each other.

[0142] In some embodiments, the resistance of resistor R2 varies with the PVT. In some embodiments, integrated circuit 200B is a self-biased adjustment circuit, thus overcoming the resistance variation of R2, thereby enabling a more flexible design with better performance than other methods.

[0143] For example, in some embodiments, any fluctuations in the gate-to-source voltage VGS of the PMOS transistor P1 caused by changes in the resistance of resistor R2 are self-compensating. In some embodiments, as the resistance of resistor R2 increases, the gate-to-source voltage VGS of the PMOS transistor P1 begins to increase, which reduces the voltage Vout of the IO pad 108. In some embodiments, reducing the voltage Vout of the IO pad 108 reduces the current I6, which in turn reduces the gate-to-source voltage VGS of the PMOS transistor P1. Therefore, using integrated circuit 200B increases the resistance of resistor R2, resulting in a reduction in the self-compensating gate-to-source voltage VGS of the PMOS transistor P1.

[0144] In some embodiments, as the resistance of resistor R2 decreases, the gate-to-source voltage VGS of PMOS transistor P1 begins to decrease, which increases the voltage Vout of IO pad 108. In some embodiments, increasing the voltage Vout of IO pad 108 increases the current I6, which in turn increases the gate-to-source voltage VGS of PMOS transistor P1. Therefore, using integrated circuit 200B reduces the resistance of resistor R2, resulting in a self-compensating increase in the gate-to-source voltage VGS of PMOS transistor P1.

[0145] Other types of circuits, configurations, and arrangements of a set of diodes 212, resistors R2, or PMOS transistors P1 are within the scope of this disclosure.

[0146] In some embodiments, the integrated circuit 200B is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0147] Other configurations or quantities of circuits in integrated circuit 200B are within the scope of this disclosure.

[0148] Figure 3A is a circuit diagram of an integrated circuit 300A according to some embodiments.

[0149] The integrated circuit 300A is an embodiment of the ESD clamp 120, therefore a similar detailed description is omitted.

[0150] Integrated circuit 300A is a variant of integrated circuit 200A in Figure 2A, therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 300A also includes diode D4a, therefore a similar detailed description is omitted.

[0151] The integrated circuit 300A includes a set of diodes 202, resistors R1, NMOS transistors N1 and D4a.

[0152] Diode D4a is located between IO pad 108 and the drain of NMOS transistor N1. Compared to the integrated circuit 200A in Figure 2A, the NMOS transistor N1 in Figure 3A is located between the cathode of diode D4a and the reference voltage source node 106 (or node Nd2).

[0153] In Figure 3A, each of the anode of diode D4a, the anode of diode D1a, and IO pad 108 is coupled together. In some embodiments, each of the anode of diode D4a, the anode of diode D1a, IO pad 108, and the output of buffer circuit 116 is coupled together.

[0154] The cathode of diode D4a is coupled to the drain of NMOS transistor N1.

[0155] In some embodiments, diode D4a has a threshold voltage Vth_D4a.

[0156] In some embodiments, current IDS2 flows through at least one of diode D4a or PMOS transistor P1. In some embodiments, current IDS2 is at least one of current I3 or I4 of integrated circuits 100A to 100B, therefore similar detailed descriptions are omitted.

[0157] In some embodiments, one or more of the diodes in a set of diodes 202 or diodes D4a are the corresponding diode-coupled transistors as shown in FIG6.

[0158] A set of diodes 202 or other number of diodes or threshold voltages D4a are within the scope of this disclosure.

[0159] In some embodiments, diode D4a is configured to provide protection for NMOS transistor N1 during an ESD event at IO pad 108 or node Nd2. For example, when an ESD event occurs at IO pad 108 or node Nd2, diode D4a is configured to provide a voltage drop (e.g., equal to the threshold voltage of diode D4a) that reduces the voltage VESD of the ESD event applied across NMOS transistor N1 (e.g., VESD - Vth_4a), thereby reducing the ESD stress across NMOS transistor N1 and thus providing protection for NMOS transistor N1.

[0160] In some embodiments, the description of the ESD detection circuit 201 of FIG3A when an ESD event occurs at node Nd2 (e.g., ESD current I3 or ESD current I1 in the reverse ESD direction) is similar to the description of the ESD detection circuit 201 of FIG2A when an ESD event occurs at node Nd2, and therefore such detailed descriptions are omitted for the sake of brevity.

[0161] Other types of circuits, configurations, and arrangements, such as diode D4a, a set of diodes 202, resistor R1, or NMOS transistor N1, are within the scope of this disclosure.

[0162] In some embodiments, the integrated circuit 300A is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0163] Other configurations or quantities of circuits in integrated circuit 300A are within the scope of this disclosure.

[0164] Figure 3B is a circuit diagram of an integrated circuit 300B according to some embodiments.

[0165] Integrated circuit 300B is an embodiment of ESD clamp 130, therefore similar detailed descriptions are omitted.

[0166] Integrated circuit 300B is a variant of integrated circuit 200B in Figure 2B, therefore a similar detailed description is omitted. Compared to integrated circuit 200B, integrated circuit 300B also includes diode D4b, therefore a similar detailed description is omitted.

[0167] The integrated circuit 300B includes a set of diodes 212, resistors R2, PMOS transistors P1 and D4b.

[0168] Diode D4b is located between IO pad 108 and the drain of PMOS transistor P1. Compared to the integrated circuit 200B in Figure 2B, in Figure 3B, PMOS transistor P1 is located between the anode of diode D4b and IO pad 108.

[0169] In Figure 3B, the anode of diode D4b is coupled to the drain of PMOS transistor P1.

[0170] In Figure 3B, each of the cathodes of diode D4b, diode D3b, and IO pad 108 is coupled together. In some embodiments, each of the cathodes of diode D4b, diode D3b, IO pad 108, and the output of buffer circuit 116 is coupled together. In some embodiments, each of the cathodes of diode D4b, diode D3b, IO pad 108, anode of diode D4a, anode of diode D1a, and the output of buffer circuit 116 is coupled together.

[0171] In some embodiments, diode D4b has a threshold voltage Vth_D4b.

[0172] In some embodiments, current IDS2 flows through at least one of diode D4b or PMOS transistor P1. In some embodiments, current IDS2 is at least one of current I3 or I4 of integrated circuits 100A to 100B, therefore similar detailed descriptions are omitted.

[0173] In some embodiments, one or more of the diodes in a set of diodes 212 or diodes D4b are the corresponding diode-coupled transistors as shown in FIG6.

[0174] A group of diodes 212 or diode D4b, or other numbers of diodes or threshold voltages, are within the scope of this disclosure.

[0175] In some embodiments, diode D4b is configured to provide protection for PMOS transistor P1 during an ESD event at IO pad 108 or node Nd1. For example, when an ESD event occurs at IO pad 108 or node Nd1, diode D4b is configured to provide a voltage drop (e.g., equal to the threshold voltage of diode D4b) that reduces the voltage VESD (e.g., VESD - Vth_4b) of the ESD event applied across PMOS transistor P1, thereby reducing the ESD stress across PMOS transistor P1 and thus providing protection for PMOS transistor P1.

[0176] In some embodiments, the description of the ESD detection circuit 211 of FIG3B when an ESD event occurs at node Nd1 (e.g., ESD current I4 or ESD current I2 in the reverse ESD direction) is similar to the description of the ESD detection circuit 211 of FIG2B when an ESD event occurs at node Nd1, and therefore such detailed descriptions are omitted for the sake of brevity.

[0177] Other types of circuits, configurations, and arrangements, such as diode D4b, a set of diodes 212, resistor R2, or PMOS transistor P1, are within the scope of this disclosure.

[0178] In some embodiments, the integrated circuit 300B is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0179] Other configurations or quantities of circuits in integrated circuit 300B are within the scope of this disclosure.

[0180] Figure 4A is a circuit diagram of an integrated circuit 400A according to some embodiments.

[0181] The integrated circuit 400A is an embodiment of the ESD clamp 120, therefore a similar detailed description is omitted.

[0182] Integrated circuit 400A is a variant of integrated circuit 300A in Figure 3A, therefore a similar detailed description is omitted. Compared to integrated circuit 300A, integrated circuit 400A also includes diode D5a, therefore a similar detailed description is omitted.

[0183] Compared to integrated circuit 300A, a set of diodes 402 replaces a set of diodes 202 in Figure 3A, therefore a similar detailed description is omitted.

[0184] Compared to integrated circuit 300A, ESD detection circuit 401 replaces ESD detection circuit 201 in Figure 3A, therefore a similar detailed description is omitted.

[0185] The integrated circuit 400A includes a set of diodes 402, resistors R1, NMOS transistors N1 and diodes D4a.

[0186] A set of diodes 402 includes at least diodes D1a, D2a, D3a, or D5a coupled together in series. In some embodiments, each diode in the set of diodes 402 has the same threshold voltage. In some embodiments, at least one diode in the set of diodes 402 has a different threshold voltage than another diode in the set of diodes 402.

[0187] In Figure 4A, the cathode of diode D3a is coupled to the anode of diode D5a.

[0188] In Figure 4A, each of the cathode of diode D5a, node Nd3, the first end of resistor R1, and the gate of NMOS transistor N1 is coupled together.

[0189] In some embodiments, current I5 flows through a set of diodes 402.

[0190] In some embodiments, one or more of the diodes in a set of diodes 402 or diodes D4a are the corresponding diode-coupled transistors as shown in FIG6.

[0191] A group of diodes 402 or diodes D4a, or other numbers of diodes or threshold voltages, are within the scope of this disclosure.

[0192] In some embodiments, a set of diodes 402 and resistors R1 are referred to as “ESD detection circuit 401”.

[0193] ESD detection circuit 401 is coupled between IO pad 108 and reference voltage source node 106 (or node Nd2).

[0194] ESD detection circuit 402 is configured to detect an ESD event at IO pad 108 (e.g., ESD current I2 or ESD current I1 in the reverse ESD direction) and, in response to the ESD event, charge node Nd3, thereby turning on NMOS transistor N1 (e.g., a discharge circuit). In some embodiments, in response to being turned on, NMOS transistor N1 (e.g., a discharge circuit) couples IO pad 108 and reference voltage source node 106 (or node Nd2), thereby providing an ESD discharge path between IO pad 108 and reference voltage source node 106 (or node Nd2).

[0195] In some embodiments, a set of diodes 402 have a trigger voltage Vtrigger3.

[0196] In some embodiments, diode D5a has a threshold voltage Vth_d5a. In some embodiments, trigger voltage Vtrigger3 is equal to the sum of the threshold voltages of each of the diodes in the set of diodes 402 (e.g., Vth_d1a + Vth_d2a + Vth_d3a + Vth_d5a).

[0197] In some embodiments, where each diode in a set of diodes 402 has a substantially equal threshold voltage (e.g., Vth_d1a), the trigger voltage Vtrigger3 is equal to the product of the number of diodes in the set of diodes 402 (e.g., 4) and the threshold voltage of each diode in the set of diodes 402 (e.g., 4*Vth_d1a).

[0198] In some embodiments, when the voltage VESD of an ESD event is greater than the trigger voltage Vtrigger3, a set of diodes 402 is turned on, thus the integrated circuit 400A is configured to operate in ESD mode where the ESD event is discharged by the NMOS transistor N1. For example, when an ESD event occurs at the IO pad 108 (e.g., PS mode) (e.g., ESD current I2 or ESD current I1 in the reverse ESD direction), the ESD current or voltage at node Nd1 rises rapidly. In some embodiments, if the ESD voltage is greater than the trigger voltage of the set of diodes 402, the set of diodes 402 is turned on or becomes forward biased. In response to the turn-on or forward bias of the set of diodes 402, the voltage at node Nd3 (e.g., across resistor R1) rises rapidly. In response to the rapidly rising voltage at node Nd3, the gate of the NMOS transistor N1 is charged by the ESD detection circuit 401. In response to the charging by the ESD detection circuit 401, the NMOS transistor N1 of the discharge circuit is turned on and couples the IO pad 108 to node Nd2. By being turned on and coupled to node Nd2 by the IO pad 108, the channel of the NMOS transistor N1 discharges the ESD current I2 in the reverse ESD direction from the IO pad 108 to node Nd2.

[0199] In some embodiments, when the voltage of the ESD event VESD is less than or equal to the trigger voltage Vtrigger3, a set of diodes 402 is turned off, and the integrated circuit 400A is configured to operate in a normal mode where no ESD event has occurred, thus turning off the NMOS transistor N1. For example, when no ESD event occurs at the IO pad 108 (e.g., in normal mode), the voltage at the IO pad 108 is less than the trigger voltage of the set of diodes 402, causing the set of diodes 402 to turn off. In response to the turn-off of the set of diodes 402, the voltage at node Nd3 is insufficient to turn on the NMOS transistor N1. In some embodiments, in response to the turn-off of the NMOS transistor N1, the IO pad 108 and node Nd2 are electrically decoupled from each other. In some embodiments, the NMOS transistor N1 is turned off when the voltage at node Nd3 is substantially equal to 0 V.

[0200] In some embodiments, diode D5a is configured to provide protection for NMOS transistor N1 during an ESD event at IO pad 108 or node Nd2, similar to the details provided in FIG3A, and therefore such detailed descriptions are omitted.

[0201] In some embodiments, a diode D5a is included in a set of diodes 402 such that the trigger voltage Vtrigger3 of the set of diodes 402 increases the threshold voltage Vth_d5a of diode D5a. In some embodiments, by increasing the trigger voltage Vtrigger3 of the set of diodes 402, the set of diodes is turned on by a higher trigger voltage Vtrigger3 than the set of diodes 402 without trigger voltage Vtrigger3 during an ESD event at IO pad 108 or node Nd2 or during a period when no ESD event occurs at IO pad 108 (e.g., normal mode).

[0202] In some embodiments, during normal operation (e.g., non-ESD mode), a set of diodes 402 is configured to be turned on by a higher trigger voltage Vtrigger3 compared to other methods, resulting in a reduction in leakage current of the set of diodes 402 compared to other methods. For example, in some embodiments, the voltage Vout of the IO pad 108 is distributed across four diodes (e.g., diodes D1a, D2a, D3a, and D5a), so the voltage across each diode in the set of diodes 402 is lower than in a method where the voltage Vout of the IO pad 108 is distributed across fewer diodes, thereby reducing the leakage current of the set of diodes 402 compared to other methods.

[0203] In some embodiments, by increasing the trigger voltage Vtrigger3 of a set of diodes 402, the set of diodes 402 are turned on by a higher trigger voltage Vtrigger3 during an ESD event at the IO pad 108 or node Nd2, thereby increasing the voltage of the ESD event VESD at the IO pad 108 or node Nd2.

[0204] In some embodiments, increasing the trigger voltage Vtrigger3 of a set of diodes 402 causes the voltage VESD of an ESD event at the IO pad 108 or node Nd2 to increase before the integrated circuit 400A is configured to discharge the ESD current. However, increasing the voltage VESD of an ESD event at the IO pad 108 or node Nd2 may also cause ESD stress on the NMOS transistor N1 when no additional protection is provided to the NMOS transistor N1.

[0205] As described with at least reference to FIG3A, diode D4a is configured to provide protection for NMOS transistor N1 by reducing ESD stress on NMOS transistor N1. For example, when an ESD event occurs at IO pad 108 or node Nd2, diode D4a is configured to provide a voltage drop (e.g., equal to the threshold voltage of diode D4a) that reduces the voltage VESD of the ESD event applied across NMOS transistor N1 (e.g., VESD - Vth_4a), thereby reducing ESD stress across NMOS transistor N1 and thus providing protection for NMOS transistor N1. Therefore, the inclusion of diode D4a in integrated circuit 400A counteracts the increased voltage VESD of the ESD event caused by the higher trigger voltage Vtrigger3 of a set of diodes 402, thereby reducing ESD stress across NMOS transistor N1.

[0206] In some embodiments, the integrated circuit 400A can be modified by including additional diodes in a set of diodes 402. In some embodiments, for each additional diode included in a set of diodes 402, the corresponding additional diode is included between diode D4a and NMOS transistor N1. For example, in some embodiments, if one additional diode is included in a set of diodes 402, then one additional diode will be included between diode D4a and NMOS transistor N1. For example, in some embodiments, if two additional diodes are included in a set of diodes 402, then two additional diodes will be included between diode D4a and NMOS transistor N1. Other numbers of diodes in a set of diodes 402 or between diode D4a and NMOS transistor N1 are within the scope of this disclosure.

[0207] Other types of circuits, configurations, and arrangements, such as diode D5a, a set of diodes 402, resistor R1, or NMOS transistor N1, are within the scope of this disclosure.

[0208] In some embodiments, the integrated circuit 400A is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0209] Other configurations or quantities of circuits in the integrated circuit 400A are within the scope of this disclosure.

[0210] Figure 4B is a circuit diagram of an integrated circuit 400B according to some embodiments.

[0211] The integrated circuit 400B is an embodiment of the ESD clamp 130, therefore a similar detailed description is omitted.

[0212] Integrated circuit 400B is a variant of integrated circuit 300B in Figure 3B, therefore a similar detailed description is omitted. Compared to integrated circuit 300B, integrated circuit 400B also includes diode D5b, therefore a similar detailed description is omitted.

[0213] Compared to integrated circuit 300B, a set of diodes 412 replaces a set of diodes 212 in Figure 3B, therefore a similar detailed description is omitted.

[0214] Compared to integrated circuit 300B, ESD detection circuit 411 replaces ESD detection circuit 211 in Figure 3B, therefore a similar detailed description is omitted.

[0215] The integrated circuit 400B includes a set of diodes 412, resistors R2, PMOS transistors P1 and D4b.

[0216] A set of diodes 412 includes at least diodes D1b, D2b, D3b, or D5b coupled together in series. In some embodiments, each diode in the set of diodes 412 has the same threshold voltage. In some embodiments, at least one diode in the set of diodes 412 has a different threshold voltage than another diode in the set of diodes 412.

[0217] In Figure 4B, the cathode of diode D3b is coupled to the anode of diode D5b.

[0218] In Figure 4B, each of the cathode of diode D5b, node Nd4, the first end of resistor R2, and the gate of PMOS transistor P1 is coupled together.

[0219] In some embodiments, current I6 flows through a set of diodes 412.

[0220] In some embodiments, one or more of the diodes in a set of diodes 412 or diodes D4b are the corresponding diode-coupled transistors as shown in FIG6.

[0221] A group of diodes 412 or diodes D4b, or other numbers of diodes or threshold voltages, are within the scope of this disclosure.

[0222] In some embodiments, a set of diodes 412 and resistors R2 are referred to as “ESD detection circuit 411”.

[0223] ESD detection circuit 411 is coupled between IO pad 108 and voltage source rail 109 (or node Nd1).

[0224] ESD detection circuit 411 is configured to detect an ESD event at IO pad 108 (e.g., ESD current I4 or ESD current I3 in the reverse ESD direction) and, in response to the ESD event, charge node Nd4 to turn on PMOS transistor P1 (e.g., a discharge circuit). In some embodiments, in response to being turned on, PMOS transistor P1 (e.g., a discharge circuit) couples IO pad 108 and voltage source rail 109 (or node Nd1) to provide an ESD discharge path between IO pad 108 and voltage source rail 109 (or node Nd1).

[0225] In some embodiments, a set of diodes 412 have a trigger voltage Vtrigger4.

[0226] In some embodiments, diode D5b has a threshold voltage Vth_d5b. In some embodiments, the trigger voltage Vtrigger4 is equal to the sum of the threshold voltages of each of the diodes in the set of diodes 412 (e.g., Vth_d1b + Vth_d2b + Vth_d3b + Vth_d5b).

[0227] In some embodiments, where each diode in a set of diodes 412 has a substantially equal threshold voltage (e.g., Vth_d1b), the trigger voltage Vtrigger4 is equal to the product of the number of diodes in the set of diodes 412 (e.g., 4) and the threshold voltage of each diode in the set of diodes 412 (e.g., 4 * Vth_d1b).

[0228] In some embodiments, when the voltage VESD of an ESD event is greater than the trigger voltage Vtrigger4, a set of diodes 412 is turned on, thus the integrated circuit 400B is configured to operate in ESD mode where the ESD event is discharged by the PMOS transistor P1. For example, when an ESD event occurs at the IO pad 108 (e.g., ND mode) (e.g., ESD current I4 or ESD current I3 in the reverse ESD direction), the ESD current or voltage at node Nd1 rises rapidly. In some embodiments, if the ESD voltage is greater than the trigger voltage of the set of diodes 412, the set of diodes 412 is turned on or becomes forward biased. In response to the turn-on or forward bias of the set of diodes 412, the voltage at node Nd4 (e.g., across resistor R2) rises rapidly. In response to the rapidly rising voltage at node Nd4, the gate of the PMOS transistor P1 is charged by the ESD detection circuit 411. In response to the charging by the ESD detection circuit 411, the PMOS transistor P1 of the discharge circuit is turned on and couples the IO pad 108 to node Nd1. By being turned on and coupled to node Nd1, the channel of the PMOS transistor P1 discharges the ESD current I4 in the reverse ESD direction from the IO pad 108 to node Nd1.

[0229] In some embodiments, when the voltage VESD of an ESD event is less than or equal to the trigger voltage Vtrigger4, a set of diodes 411 is turned off, and the integrated circuit 400B is configured to operate in a normal mode where no ESD event has occurred, thus turning off the PMOS transistor P1. For example, when no ESD event occurs at IO pad 108 (e.g., in normal mode), the voltage at IO pad 108 is less than the trigger voltage of a set of diodes 412, causing the set of diodes 412 to turn off. In response to the turn-off of the set of diodes 412, the voltage at node Nd4 is insufficient to turn on the PMOS transistor P1. In some embodiments, in response to the turn-off of the PMOS transistor P1, IO pad 108 and node Nd1 are electrically decoupled from each other.

[0230] In some embodiments, diode D5b is configured to provide protection for PMOS transistor P1 during an ESD event at IO pad 108 or node Nd1, similar to the details provided in Figure 3B, and therefore such detailed descriptions are omitted.

[0231] In some embodiments, including diode D5b in a set of diodes 412 causes the trigger voltage Vtrigger4 of the set of diodes 412 to increase the threshold voltage Vth_D5b of diode D5b. In some embodiments, by increasing the trigger voltage Vtrigger4 of the set of diodes 412, the set of diodes is turned on by a higher trigger voltage Vtrigger3 than the set of diodes 412 without trigger voltage Vtrigger4 during an ESD event at IO pad 108 or node Nd1 or during a period when no ESD event occurs at IO pad 108 (e.g., normal mode).

[0232] In some embodiments, during normal operation (e.g., non-ESD mode), a set of diodes 412 is configured to be turned on by a higher trigger voltage Vtrigger 4 compared to other methods, resulting in a reduction in leakage current of the set of diodes 412 compared to other methods. For example, in some embodiments, the voltage Vout of the IO pad 108 is distributed across four diodes (e.g., diodes D1b, D2b, D3b, and D5b), so the voltage across each diode in the set of diodes 412 is lower than in a method where the voltage Vout of the IO pad 108 is distributed across fewer diodes, thereby reducing the leakage current of the set of diodes 412 compared to other methods.

[0233] In some embodiments, by increasing the trigger voltage Vtrigger4 of a set of diodes 412, the set of diodes 412 are turned on by a higher trigger voltage Vtrigger4 during an ESD event at the IO pad 108 or node Nd1, thereby increasing the voltage of the ESD event VESD at the IO pad 108 or node Nd1.

[0234] In some embodiments, increasing the trigger voltage Vtrigger4 of a set of diodes 412 causes the voltage VESD of an ESD event at the IO pad 108 or node Nd1 to increase before the integrated circuit 400B is configured to discharge the ESD current. However, increasing the voltage VESD of an ESD event at the IO pad 108 or node Nd1 may also cause ESD stress on the PMOS transistor P1 when no additional protection is provided to the PMOS transistor P1.

[0235] As described with at least reference to Figure 3B, diode D4b is configured to provide protection for PMOS transistor P1 by reducing ESD stress on PMOS transistor P1. For example, when an ESD event occurs at IO pad 108 or node Nd1, diode D4b is configured to provide a voltage drop (e.g., equal to the threshold voltage of diode D4b) that reduces the voltage VESD of the ESD event applied across PMOS transistor P1 (e.g., VESD - Vth_4b), thereby reducing ESD stress across PMOS transistor P1 and thus providing protection for PMOS transistor P1. Therefore, the inclusion of diode D4b in integrated circuit 400B counteracts the increased voltage VESD of the ESD event caused by the higher trigger voltage Vtrigger4 of a set of diodes 412, thereby reducing ESD stress across PMOS transistor P1.

[0236] In some embodiments, the integrated circuit 400B can be modified by including additional diodes in a set of diodes 412. In some embodiments, for each additional diode included in a set of diodes 412, the corresponding additional diode is included between diode D4b and PMOS transistor P1. For example, in some embodiments, if one additional diode is included in a set of diodes 412, then one additional diode will be included between diode D4b and PMOS transistor P1. For example, in some embodiments, if two additional diodes are included in a set of diodes 412, then two additional diodes will be included between diode D4b and PMOS transistor P1. Other numbers of diodes in a set of diodes 412 or between diode D4b and PMOS transistor P1 are within the scope of this disclosure.

[0237] Other types of circuits, configurations, and arrangements, such as diode D5b, a set of diodes 412, resistor R2, or PMOS transistor P1, are within the scope of this disclosure.

[0238] In some embodiments, the integrated circuit 400B is configured to achieve one or more of the benefits described herein, including the details discussed herein.

[0239] Other configurations or quantities of circuits in integrated circuit 400B are within the scope of this disclosure.

[0240] Figure 5A is a circuit diagram of an integrated circuit 500A according to some embodiments.

[0241] The integrated circuit 500A is an embodiment of the ESD clamp 120, therefore a similar detailed description is omitted.

[0242] Integrated circuit 500A is a variant of integrated circuit 400A in Figure 4A, therefore a similar detailed description is omitted. Compared to integrated circuit 400A, integrated circuit 500A also includes PMOS transistor P3 and NMOS transistor N2, therefore a similar detailed description is omitted.

[0243] Compared to integrated circuit 400A, PMOS transistor P2 replaces diode D1a in FIG4A, therefore a similar detailed description is omitted. In some embodiments, PMOS transistor P2 is diode-coupled transistor 504, and the operation of PMOS transistor P2 is similar to that of diode D1a in FIG4A, therefore a similar detailed description is omitted.

[0244] The integrated circuit 500A includes a set of diodes 502, resistors R1, NMOS transistors N1, NMOS transistors N2, PMOS transistors P2, PMOS transistors P3 and diode D4a.

[0245] A set of diodes 502 is a variant of a set of diodes 402 in Figure 4A, therefore a similar detailed description is omitted. Compared to a set of diodes 402, a set of diodes 502 does not include diode D1a, therefore a similar detailed description is omitted.

[0246] In some embodiments, one or more of the diodes in a group of diodes 502 or diodes D4a are the corresponding diode-coupled transistors as shown in FIG6.

[0247] A group of diodes 502 or diode D4a, or other numbers of diodes or threshold voltages, are within the scope of this disclosure.

[0248] PMOS transistor P2 is coupled between IO pad 108 and the anode of diode D2a. PMOS transistor P2 is a diode-coupled transistor 504.

[0249] The gate of PMOS transistor P2, the drain of PMOS transistor P2, the gate of PMOS transistor P3, and the anode of diode D2a are each coupled to each other.

[0250] In Figure 5A, each of the PMOS transistor P2 source, PMOS transistor P3 source, diode D4a anode and IO pad 108 is coupled to each other.

[0251] PMOS transistor P3 is coupled between IO pad 108 and the drain of NMOS transistor N2.

[0252] Each of the drains of PMOS transistor P3 and NMOS transistor N2 is coupled to each other.

[0253] The NMOS transistor N2 is coupled between the PMOS transistor P3 and the reference voltage source node 106 (or node Nd2).

[0254] The source of NMOS transistor N2, the source of NMOS transistor N1, the second terminal of resistor R1, and each of the reference voltage source nodes 106 (or node Nd2) are coupled to each other.

[0255] In Figure 5A, each of the gates of NMOS transistor N2, NMOS transistor N1, node Nd3, the first terminal of resistor R1, and the cathode of diode D5a is coupled to each other.

[0256] In some embodiments, current ICM1 ​​flows through PMOS transistor P3 and NMOS transistor N2.

[0257] In some embodiments, current I5 flows through PMOS transistor P2, a set of diodes 502 and resistor R1.

[0258] In some embodiments, PMOS transistor P2, a set of diodes 502, resistor R1, diode D4a, and NMOS transistor N1 are part of circuit 501. In some embodiments, circuit 501 is the integrated circuit 400A of FIG. 4A, therefore a similar detailed description is omitted.

[0259] In some embodiments, the integrated circuit 500A is configured to operate in ESD mode and normal mode.

[0260] In some embodiments, no ESD event occurs at IO pad 108 in the normal mode of integrated circuit 500A (e.g., normal mode). In some embodiments, PMOS transistors P2 and PMOS transistor P3 are configured as current mirrors, so current ICM1 ​​is configured to mirror current I5, and vice versa. In some embodiments, the first path 550 (e.g., current ICM1) is the main branch of the current mirror, while the second path 552 (e.g., current I5) is a tracking branch. In some embodiments, the second path 552 is configured to track the first path 550a of the current mirror.

[0261] In some embodiments, when no ESD event occurs at the IO pad 108 (e.g., normal mode), the current mirrors (e.g., PMOS transistors P2 and P3) and a set of diodes 502 of the integrated circuit 500A cause the integrated circuit 500A to have less leakage current than in other ways.

[0262] In some embodiments, at least the current mirrors in the integrated circuit 500A (e.g., PMOS transistors P2 and P3), NMOS transistor N2, or circuit 501 are used to make the integrated circuit 500A have less leakage current than in other ways.

[0263] In some embodiments, in the ESD mode of integrated circuit 500A, an ESD event occurs at IO pad 108 or node Nd2. In some embodiments, during an ESD event at IO pad 108 or node Nd1, circuit 501 is configured to operate in a manner similar to that of integrated circuit 400A, and therefore a similar detailed description is omitted.

[0264] In some embodiments, the PMOS transistor P2, a set of diodes 502 and resistor R1 are referred to as an ESD detection circuit (unlabeled), but the ESD detection circuit (unlabeled) of FIG5A is configured to operate in a manner similar to that of the ESD detection circuit 401 of FIG4A, so a similar detailed description is omitted.

[0265] Diode D4a, a set of diodes 502, resistor R1, NMOS transistor N1, NMOS transistor N2, PMOS transistor P2 and PMOS transistor P3, and other types of circuits, configurations and arrangements are within the scope of this disclosure.

[0266] In some embodiments, the integrated circuit 500A is configured to achieve one or more of the benefits described herein.

[0267] Other configurations or quantities of circuits in the integrated circuit 500A are within the scope of this disclosure.

[0268] Figure 5B is a circuit diagram of an integrated circuit 500B according to some embodiments.

[0269] The integrated circuit 500B is an embodiment of the ESD clamp 130, therefore a similar detailed description is omitted.

[0270] Integrated circuit 500B is a variant of integrated circuit 400B in Figure 4B, therefore a similar detailed description is omitted. Compared to integrated circuit 400B, integrated circuit 500B also includes NMOS transistor N4 and PMOS transistor P4, therefore a similar detailed description is omitted.

[0271] Compared to integrated circuit 400B, NMOS transistor N3 replaces diode D5b in FIG4B, therefore a similar detailed description is omitted. In some embodiments, NMOS transistor N3 is diode-coupled transistor 514, and the operation of NMOS transistor N3 is similar to that of diode D5b in FIG4B, therefore a similar detailed description is omitted.

[0272] The integrated circuit 500B includes a set of diodes 512, resistors R2, PMOS transistors P1, PMOS transistors P4, NMOS transistors N3, NMOS transistors N4 and diode D4b.

[0273] A set of diodes 512 is a variant of the set of diodes 412 in Figure 4B, therefore a similar detailed description is omitted. Compared to the set of diodes 412, the set of diodes 512 does not include diode D5b, therefore a similar detailed description is omitted.

[0274] In some embodiments, one or more of the diodes in a group of diodes 512 or diodes D4b are the corresponding diode-coupled transistors as shown in FIG6.

[0275] A group of diodes 512 or diode D4b, or other numbers of diodes or threshold voltages, are within the scope of this disclosure.

[0276] The NMOS transistor N3 is coupled between the IO pad 108 and the cathode of diode D3b. The NMOS transistor N3 is a diode-coupled transistor 514.

[0277] The gate of NMOS transistor N3, the drain of NMOS transistor N3, the gate of NMOS transistor N4, and the cathode of diode D3b are each coupled to each other.

[0278] In Figure 5B, each of the sources of NMOS transistor N3, NMOS transistor N4, cathode of diode D4b, and IO pad 108 is coupled to each other.

[0279] The NMOS transistor N4 is coupled between the IO pad 108 and the drain of the PMOS transistor P4.

[0280] Each of the drains of NMOS transistor N4 and PMOS transistor P4 is coupled to each other.

[0281] PMOS transistor P4 is coupled between NMOS transistor N4 and voltage source rail 109 (or node Nd1).

[0282] The source of PMOS transistor P4, the source of PMOS transistor P1, the second terminal of resistor R2, and each of the voltage source rails 109 (or node Nd1) are coupled to each other.

[0283] In Figure 5B, each of the following is coupled to each other: the gate of PMOS transistor P4, the gate of PMOS transistor P1, node Nd4, the first terminal of resistor R2, and the anode of diode D1b.

[0284] In some embodiments, current ICM2 flows through NMOS transistor N4 and PMOS transistor P4.

[0285] In some embodiments, current I6 flows through NMOS transistor N3, a set of diodes 512 and resistor R2.

[0286] In some embodiments, NMOS transistor N3, a set of diodes 512, resistor R2, diode D4b, and PMOS transistor P1 are part of circuit 511. In some embodiments, circuit 511 is the integrated circuit 400B of FIG. 4B, therefore a similar detailed description is omitted.

[0287] In some embodiments, the integrated circuit 500B is configured to operate in ESD mode and normal mode.

[0288] In some embodiments, no ESD event occurs at IO pad 108 in the normal mode of integrated circuit 500B (e.g., normal mode). In some embodiments, NMOS transistors N3 and NMOS transistors N4 are configured as current mirrors, so current ICM2 is configured to mirror current I6, and vice versa. In some embodiments, the first path 560 (e.g., current ICM2) is the main branch of the current mirror, while the second path 562 (e.g., current I6) is a tracking branch. In some embodiments, the second path 562 is configured to track the first path 560 of the current mirror.

[0289] In some embodiments, when no ESD event occurs at the IO pad 108 (e.g., normal mode), the current mirrors (e.g., NMOS transistors N3 and N4) and a set of diodes 512 of the integrated circuit 500B cause the integrated circuit 500B to have less leakage current than in other ways.

[0290] In some embodiments, at least the current mirrors (e.g., NMOS transistors N3 and N4), PMOS transistor P4, or circuit 511 in the integrated circuit 500B are used to make the integrated circuit 500B have less leakage current than in other ways.

[0291] In some embodiments, in the ESD mode of integrated circuit 500B, an ESD event occurs at IO pad 108 or node Nd1. In some embodiments, during an ESD event at IO pad 108 or node Nd1, circuit 511 is configured to operate in a manner similar to that of integrated circuit 400B, and therefore a similar detailed description is omitted.

[0292] In some embodiments, the NMOS transistor N3, a set of diodes 512 and resistor R2 are referred to as an ESD detection circuit (unlabeled), but the ESD detection circuit (unlabeled) of FIG5B is configured to operate in a similar manner to the ESD detection circuit 411 of FIG4B, so a similar detailed description is omitted.

[0293] Diode D4b, a set of diodes 512, resistor R2, PMOS transistor P1, PMOS transistor P4, NMOS transistor N3 and NMOS transistor N4, and other types of circuits, configurations and arrangements are within the scope of this disclosure.

[0294] In some embodiments, the integrated circuit 500B is configured to achieve one or more of the benefits described herein.

[0295] Other configurations or quantities of circuits in integrated circuit 500B are within the scope of this disclosure.

[0296] Figure 6 is a diagram of a circuit 600 according to some embodiments.

[0297] In some embodiments, circuit 600 may be used in Figures 2A to 2B, 3A to 3B, 4A to 4B and 5A to 5B according to some embodiments.

[0298] In some embodiments, circuit 600 may be used as at least one of diodes D1a, D2a, D3a, D4a, D5a, D1b, D2b, D3b, D4b or D5b of Figures 2A to 2B, 3A to 3B, 4A to 4B and 5A to 5B, and therefore similar detailed descriptions are omitted.

[0299] Circuit 600 includes transistor 602. In some embodiments, transistor 602 is an N-type transistor. In some embodiments, transistor 602 is an NFET. In some embodiments, transistor 602 is an NMOS transistor. Other transistor types or numbers in transistor 602 are within the scope of this disclosure. In some embodiments, transistor 602 is a P-type transistor. In some embodiments, transistor 602 is a PFET. In some embodiments, transistor 602 is a PMOS transistor.

[0300] Transistor 602 is a diode-coupled transistor.

[0301] Each of the gate terminal G1 and drain terminal D1 of transistor 602 is coupled to each other.

[0302] In some embodiments, the gate terminal G1 and drain terminal D1 of transistor 602 correspond to at least one of the anodes of diodes D1a, D2a, D3a, D4a, D5a, D1b, D2b, D3b, D4b, or D5b, and the source terminal S1 of transistor 602 corresponds to at least one of the cathodes of diodes D1a, D2a, D3a, D4a, D5a, D1b, D2b, D3b, D4b, or D5b. Therefore, similar detailed descriptions are omitted.

[0303] Other configurations of circuit 600 are within the scope of this disclosure.

[0304] Other configurations or quantities of circuits in integrated circuit 600 are within the scope of this disclosure.

[0305] Figures 7A to 7G are block diagrams of corresponding resistor networks 700A, 700B, 700C, 700D, 700E, 700F and 700G according to some embodiments.

[0306] Resistor networks 700A, 700B, 700C, 700D, 700E, 700F, and 700G are embodiments of at least one of resistor R1 or resistor R2, therefore similar detailed descriptions are omitted.

[0307] In some embodiments, resistor networks 700A, 700B, 700C, 700D, 700E, 700F, and 700G may be used as at least one of resistors R1 or R2, and therefore similar detailed descriptions are omitted.

[0308] The resistor network 700A includes cell regions 718B(0) to 718B(m-1).

[0309] Cell regions 718B(0) to 718B(m-1) are coupled together in a manner that represents resistors (e.g., at least one of resistor R1 or resistor R2) having a first terminal and a second terminal (in various ways, in series and / or in parallel (Figures 7B to 7D) etc.). In some embodiments, each of cell regions 718B(0) to 718B(m-1) includes a first resistive subnetwork and a second resistive subnetwork.

[0310] In Figure 7A, the resistor network 700A includes cell regions 718B(0), 718B(1), ..., 718B(m-2) and 718B(m-1), which are adjacent to each other with respect to a first direction X (e.g., parallel to the X-axis), and where m is a positive integer equal to or greater than 1.

[0311] Relative to the X-axis, Figure 7A shows pairs of adjacent cell regions (e.g., 718B(1) and 718B(2)) that are horizontally adjacent with virtually no space between them. In some embodiments (not shown), depending on design considerations (e.g., wiring, etc.), not every pair of adjacent cell regions is horizontally adjacent; that is, there is a noticeable space between one or more pairs of corresponding adjacent cell regions 718B(0) to 718B(m-1).

[0312] Regarding Figures 7B to 7D and Figures 7F to 7G, in each cell region, each first resistor subnetwork and second resistor subnetwork is represented by the corresponding resistor symbol. For example, in Figure 7B, cell region 718B(1) is shown with resistor symbols 780(1) and 782(1), while cell region 718B(m-1) is shown with resistor symbols 780(m-1) and 782(m-1).

[0313] In Figure 7A, the first and second resistor networks are coupled together in a manner that represents at least one of resistors R1 or R2 having a first terminal and a second terminal (in various ways in series and / or in parallel (Figures 7B to 7D) etc.).

[0314] In Figure 7B, in some embodiments, one or more of the cell regions 718B(0) to 718B(m-1) are fully internally coupled in series (ESCI), that is, the first resistive subnetwork 784(1) is coupled together in series. For example, according to some embodiments, each of the resistors 780(0), ..., 780(m-1) in the first resistive subnetwork 784(1) is coupled together in series with each other.

[0315] In Figure 7B, in some embodiments, one or more of the cell regions 718B(0) to 718B(m-1) are fully internally coupled in series (ESCI), that is, the second resistive subnetwork 784(2) is coupled together in series. For example, according to some embodiments, each of the resistors 782(0), ..., 782(m-1) in the second resistive subnetwork 784(2) is coupled together in series with each other.

[0316] In Figure 7C, in some embodiments, the first resistive subnetwork 784(1) and the second resistive subnetwork 784(2) are coupled together in series. For example, according to some embodiments, each of the resistors 780(0), ..., 780(m-1) in the first resistive subnetwork 784(1) is coupled together in series with each of the resistors 782(0), ..., 782(m-1) in the second resistive subnetwork 784(2) through the conductor M1 772(13) and the via 770.

[0317] In some embodiments, the first resistive subnetwork 784(1) and the second resistive subnetwork 784(2) are part of the current path 784(3). In some embodiments, the current path 784(3) is described as having a meandering shape.

[0318] Regarding Figure 7D, resistor network 700D shows cell regions 718D(0) to 718D(1), but cell regions 718D(2) to 718D(m-1) are not shown, as the latter are omitted for simplicity. In some embodiments, each of cell regions 718D(0) to 718D(m-1) has an ESCI configuration.

[0319] In cell region 718D(0), resistor 780(0) is coupled in series to resistor 782(0), as shown in current path 784(4). In cell region 718D(1), resistor 780(1) is coupled in series to resistor 782(1), as shown in current path 784(5). Current paths 784(4) and 784(5) are coupled to each other, as shown in current path 784(6). In some embodiments, each of current paths 784(4) and 784(5) is described as having a meandering shape.

[0320] In Figure 7D, cell region 718D(0) has a first orientation relative to the long axis of symmetry parallel to the second direction Y (e.g., parallel to the Y-axis). More generally, even-numbered cell regions in cell regions 718D(0) to 718D(m-1) have a first orientation, i.e., cell region 718D(j) has a first orientation, where j is an integer in the range (0)≤j≤(m-1) and j=2k, where k is a non-negative integer.

[0321] Also in Figure 7D, cell region 718D(1) has a second orientation relative to the long axis of symmetry parallel to the Y-axis. The second orientation is mirror-symmetric with respect to the first axis relative to the Y-axis. More generally, the odd-numbered cell regions in cell regions 718D(0) to 718D(m-1) have a second orientation, that is, cell region 718D(q) has a second orientation, where q is an integer, q is in the range (0)≤q≤(m-1), and q=(2k+1), where k is a non-negative integer.

[0322] In Figure 7E, the resistor network 700E includes cell regions 718B(0) to 718B(m-1) that are adjacent to each other relative to the Y-axis.

[0323] Relative to the Y-axis, Figure 7E shows pairs of adjacent cell regions, such as 718B(1) and 718B(2), which are vertically adjacent with virtually no space between them. In some embodiments (not shown), depending on design considerations (e.g., wiring, etc.), not every pair of adjacent cell regions is vertically adjacent; that is, there is a noticeable space between one or more pairs of corresponding adjacent cell regions 718B(0) to 718B(m-1).

[0324] Regarding Figure 7F, resistor network 700F shows cell regions 718F(0) to 718F(1), but cell regions 718F(2) to 718F(m-1) are not shown, the latter being omitted for the sake of simplicity.

[0325] In Figure 7F, in some embodiments, resistor 780(0) is coupled in series with resistor 782(0) through conductor M1 772(14) and via 770 and is part of current path 784(7); resistor 782(0) is coupled in series with resistor 780(1) through conductor M1 772(15) and via 770 and is part of current path 784(8); resistor 780(1) is coupled in series with resistor 782(16) through conductor M1 772(16) and via 770 and is part of current path 784(9), and so on.

[0326] Regarding Figure 7G, the resistor network 700G shows cell regions 718G(0) to 718G(1), but cell regions 718G(2) to 718G(m-1) are not shown, as the latter are omitted for simplicity. In some embodiments, each of cell regions 718G(0) to 718G(m-1) has an ESCI configuration.

[0327] In cell region 718G(0), resistor 780(0) is coupled in series to resistor 782(0), as shown in current path 784(10). In cell region 718G(1), resistor 780(1) is coupled in series to resistor 782(1), as shown in current path 784(12). In some embodiments, each of current path 784(10) and current path 784(12) is described as having a meandering shape.

[0328] In Figure 7G, in some embodiments, resistor 782(0) is coupled in series with resistor 780(1) through conductor M1 772(17) and via 770, and is part of current path 784(11).

[0329] In some embodiments, at least one of the resistor networks 700A, 700B, 700C, 700D, 700E, 700F, or 700G is configured to achieve one or more of the benefits described herein.

[0330] Other configurations or quantities of circuitry in at least one of the resistor networks 700A, 700B, 700C, 700D, 700E, 700F, or 700G are within the scope of this disclosure.

[0331] Figures 8A and 8B are illustrations of an integrated circuit 800 according to some embodiments. Figures 8C to 8D are corresponding cross-sectional views of the integrated circuit 800 according to some embodiments.

[0332] Figure 8A is a simplified top view of a portion of the integrated circuit 800A for ease of illustration.

[0333] Figure 8B is a simplified top view of a portion of the integrated circuit 800B for ease of illustration.

[0334] Figure 8C is a cross-sectional view of an integrated circuit 800 intersecting plane A-A' according to some embodiments.

[0335] Figure 8D is a cross-sectional view of an integrated circuit 800 intersecting with plane B-B' according to some embodiments.

[0336] This 800A section includes one or more features of oxide diffusion (OD) level or active level, metal diffusion (MD) level, gate (POLY) level, via gate (VG) level, via diffusion (VD) level and metal O (MO) level.

[0337] This 800B section includes one or more features of MD, POLY, VG, VD, and MO grades.

[0338] For ease of illustration, some of the labeled elements in one or more of Figures 8A to 8D are not labeled in one or more of Figures 8A to 8D. In some embodiments, the integrated circuit 800 includes additional elements not shown in Figures 8A to 8D.

[0339] The integrated circuit 800 is an embodiment of at least one of the resistor networks 700A, 700B, 700C, 700D, 700E, 700F and 700G of the corresponding Figures 7A, 7B, 7C, 7D, 7E, 7F and 7G, and therefore similar detailed descriptions are omitted.

[0340] In some embodiments, the integrated circuit 800 may be used as at least one of resistor R1 or resistor R2, therefore a similar detailed description is omitted.

[0341] The integrated circuit 800 is manufactured using a corresponding layout design similar to that of the integrated circuit 800. For simplicity, Figures 8A to 8D are described as integrated circuit 800. In some embodiments, each of Figures 8A to 8D is also a corresponding layout design, and each structural element of the integrated circuit 800 is a corresponding layout pattern. The structural relationships (including alignment, length, and width) of the integrated circuit 800, as well as the configuration and layers of the corresponding layout design, are similar to the structural relationships, configuration, and layers of the integrated circuit 800. For simplicity, similar detailed descriptions will not be provided.

[0342] The integrated circuit 800 includes a cell 801. Cell 801 has cell boundaries 801a and 801b extending in a first direction X, and cell boundaries 801c and 801d extending in a second direction Y. In some embodiments, the second direction Y is different from the first direction X. In some embodiments, the integrated circuit 800 is adjacent to other cells (not shown) along cell boundaries 801c and 801d. In some embodiments, the integrated circuit 800 is adjacent to other cells (not shown) along cell boundaries 801a and 801b extending in the first direction X. In some embodiments, the integrated circuit 800 is a single height-standard cell.

[0343] In some embodiments, cell 801 is a standard cell defined by cell boundaries 801a, 801b, 801c, and 801d. In some embodiments, cell 801 is defined by cell boundaries 801a, 801b, 801c, and 801d, and therefore corresponds to a region of a circuit element or device that is part of a standard cell.

[0344] In some embodiments (e.g., the embodiments depicted in Figures 8A to 8D discussed below), a given cell has cell boundaries 801c and 801d that overlap with the corresponding gates 804a and 804f. For example, in some embodiments, the cell boundaries 801c and 801d of cell 801 are identified by gates 804a and 804f.

[0345] The integrated circuit 800 includes a substrate 890 (Figures 8C to 8D). In some embodiments, substrate 890 is a p-type substrate. In some embodiments, substrate 890 is a p-type well in a lower substrate (not shown). In some embodiments, substrate 890 includes a basic semiconductor (including silicon or germanium with crystalline, polycrystalline, or amorphous structures); a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide); an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP); any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature, wherein the Si and Ge composition varies from one ratio at one location of the gradient SiGe feature to another ratio at another location. In some embodiments, alloy SiGe is formed on a silicon substrate. In some embodiments, substrate 890 is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate comprises a multilayer compound semiconductor structure.

[0346] In some embodiments, the integrated circuit 800 is incorporated on a single integrated circuit (IC) or a single semiconductor substrate. In some embodiments, the integrated circuit 800 includes one or more ICs incorporated on one or more single semiconductor substrates.

[0347] The integrated circuit 800 also includes one or more active regions 802a or 802b (collectively referred to as "a set of active regions 802") extending in the first direction X.

[0348] A set of active regions is embedded in substrate 890. Substrate 890 has a front side (unmarked) and a rear side opposite to the front side (unmarked).

[0349] A set of active regions 802, specifically active regions 802a or 802b, are separated from each other in a second direction Y. In some embodiments, the second direction Y is different from the first direction X. The set of active regions 802 is manufactured by a set of corresponding active region layout patterns similar to the layout design of an integrated circuit 800.

[0350] In some embodiments, a set of active regions 802 are located on the front side (not labeled) of at least the integrated circuit 800. In some embodiments, active regions 802a or 802b of the set of active regions 802 are manufactured by corresponding active region layout patterns in a set of active region layout patterns.

[0351] In some embodiments, a set of active regions 802 is referred to as oxide diffusion (OD) regions, which define at least the source or drain diffusion regions of the integrated circuit 800.

[0352] In some embodiments, the active regions 802a of a set of active regions 802 are source and / or drain regions of one or more NMOS transistors, while the active regions 802a of a set of active regions 802 are source and / or drain regions of one or more PMOS transistors. In some embodiments, the active regions 802a of a set of active regions 802 are source and / or drain regions of one or more PMOS transistors, while the active regions 802a of a set of active regions 802 are source and / or drain regions of one or more NMOS transistors.

[0353] In some embodiments, one of the active regions 802a or 802b is an N-type doped S / D region embedded in the electrical medium material of the substrate 890, while the other of the active regions 802a or 802b is a P-type doped S / D region embedded in the electrical medium material of the substrate 890.

[0354] In some embodiments, a set of active regions 802 are located on a first stage. In some embodiments, the first stage corresponds to an active stage or an off-center stage of an integrated circuit 800.

[0355] The other number of active regions in a set of active regions 802 are within the scope of this disclosure.

[0356] Other configurations, arrangements at other levels, or the number of zones in a set of active zones 802 are within the scope of this disclosure.

[0357] The integrated circuit 800 also includes an insulating region 803.

[0358] Insulating regions 803 are configured to electrically isolate one or more elements of a set of active regions 802, a set of gates 804, or a set of contacts 806 from each other or from other elements (not shown). In some embodiments, insulating regions 803 include a plurality of insulating regions deposited at different times during method 8100 (FIG. 11). In some embodiments, insulating regions 803 are electrical media materials. In some embodiments, electrical media materials include silicon dioxide, silicon oxynitride, etc.

[0359] Other configurations, arrangements, or other quantities of parts at other layout levels in the insulation region 803 are within the scope of this disclosure.

[0360] The integrated circuit 800 also includes one or more of gates 804a, 804b, 804c, 804d, 804e, or 804f (collectively referred to as a "set of gates 804") extending in the second direction Y. Each gate in the set of gates 804 is spaced apart from adjacent gates in the set of gates 804 by a distance CPP in the first direction X. In some embodiments, adjacent elements are elements that are directly adjacent to each other. For example, if a first element is adjacent to a second element, then the second element and the first element are directly adjacent to each other.

[0361] In some embodiments, a set of gates 804 is manufactured using a set of corresponding gate layout patterns. In some embodiments, gates 804a, 804b, 804c, 804d, 804e, or 804f in a set of gates 804 are manufactured using corresponding gate layout patterns in a set of gate layout patterns.

[0362] In some embodiments, one or more of gates 804b, 804c, 804d or 804e in a set of gates 804 are gates of the corresponding transistors.

[0363] In some embodiments, one or more of gates 804a or 804f in a set of gates 804 are dummy gates. In some embodiments, the dummy gate is a non-functional gate. In some embodiments, the dummy gate is also referred to as a continuous polysilicon diffusion edge (CPODE) gate. In some embodiments, at least one of gates 804a or 804f overlaps with a corresponding cell boundary 801c or 801d. Other gates configured as dummy gates are within the scope of this disclosure.

[0364] A set of gates 804 is located above a set of active regions 802. The set of gates 804 is located on a second stage, distinct from the first stage. In some embodiments, the second stage differs from the first stage. In some embodiments, the second stage corresponds to the POLY stage of the integrated circuit 800.

[0365] In some embodiments, the POLY level is above the OD level.

[0366] Other configurations in a set of gates 804, arrangements on other stages, or the number of gates are within the scope of this disclosure.

[0367] The integrated circuit 800 also includes one or more of contacts 806a, 806b, 806c, 806d or 806e (collectively referred to as "a set of contacts 806") extending in the second direction Y.

[0368] Each of the set of contacts 806 is separated from its adjacent contacts in the set of contacts 806 at least in the first direction X. In some embodiments, adjacent elements are elements that are directly adjacent to each other. For example, if a first element is adjacent to a second element, then the second element and the first element are directly adjacent to each other.

[0369] A set of contacts 806 is manufactured using a set of corresponding contact layout patterns. In some embodiments, contacts 806a, 806b, 806c, 806d, or 806e in a set of contacts 806 are manufactured using corresponding contact layout patterns in a set of contact layout patterns.

[0370] In some embodiments, a set of contacts 806 is also referred to as a set of metal diffusion (MD) structures.

[0371] In some embodiments, at least one of contacts 806a, 806b, 806c, 806d or 806e in a group of contacts 806 is the source or drain terminal of the corresponding NMOS transistor or the corresponding PMOS transistor.

[0372] In some embodiments, a set of contacts 806 overlaps with a set of active regions 802. The set of contacts 806 is located on a third level. In some embodiments, the third level corresponds to one or more contact levels or MD levels in the integrated circuit 800. In some embodiments, the third level is the same as the second level. In some embodiments, the third level is different from the first level.

[0373] Other configurations in a set of contacts 806, arrangements at other levels, or the number of contacts are within the scope of this disclosure.

[0374] The integrated circuit 800 also includes one or more conductors 820a, 820b, ..., 820j or 820k (collectively referred to as "a set of conductors 820") extending at least in the first direction X.

[0375] Each of conductors 820a, 820b, ..., 820j or 820k in a group of conductors 820 is separated from each other at least in the second direction Y.

[0376] In some embodiments, although each of conductors 820a, 820b, ..., 820j or 820k is shown as a continuous pattern, one or more of conductors 820a, 820b, ..., 820j or 820k are spaced apart to form a discontinuous pattern. In some embodiments, conductors 820a, 820b, and 820c are a continuous pattern. In some embodiments, conductors 820d, 820e, and 820f are a continuous pattern. In some embodiments, conductors 820g, 820h, and 820i are a continuous pattern. In some embodiments, conductors 820j and 820k are a continuous pattern.

[0377] A set of conductors 820 is manufactured using a set of corresponding conductive feature layout patterns. In some embodiments, conductors 820a, 820b, ..., 820j or 820k in a set of conductors 820 are manufactured using corresponding conductive feature layout patterns in a set of conductive feature layout patterns.

[0378] In some embodiments, a set of conductors 820 are located on the front side (not labeled) of the integrated circuit 800.

[0379] A set of conductors 820 overlaps with a set of gates 804, a set of active regions 802, and a set of contacts 806. In some embodiments, the set of conductors 820 is on a fourth level. In some embodiments, the fourth level is different from the first, second, and third levels. In some embodiments, the fourth level corresponds to the M0 level of the integrated circuit 800. In some embodiments, the M0 level is above the OD, POLY, MD, VG, and VD levels. In some embodiments, the set of conductors 820 is located on other metal layers (e.g., metal-1 (M1), metal-2 (M2), etc.).

[0380] Each conductor in a set of conductors 820 is separated from its adjacent conductor in the second direction Y by a certain distance (not marked).

[0381] In some embodiments, a set of conductors 820 corresponds to five M0 wiring traces in the integrated circuit 800.

[0382] In some embodiments, a set of conductors 820 corresponds to five M0 wiring traces in the integrated circuit 800 (e.g., a set of grid lines 830).

[0383] In some embodiments, a set of grid lines 830 extends in a first direction and specifies the corresponding M0 wiring trace in the integrated circuit 800. In some embodiments, the set of grid lines 830 includes grid lines 830a, 830b, ..., 830e.

[0384] In some embodiments, grid lines 830a overlap with conductors 820a, 820b and 820c.

[0385] In some embodiments, grid lines 830b overlap with conductors 820d, 820e, and 820f.

[0386] In some embodiments, grid lines 830d overlap with conductors 820g, 820h and 820i.

[0387] In some embodiments, grid lines 830e overlap with conductors 820j and 820k.

[0388] Other numbers of M0 wiring traces are within the scope of this disclosure.

[0389] Other configurations, layouts, or the number of conductors in a group of conductors 820 are within the scope of this disclosure.

[0390] The integrated circuit 800 also includes one or more vias 810a, 810b, ..., 810i or 810j (collectively referred to as "a set of vias 810").

[0391] A set of vias 810 is manufactured using a set of corresponding via patterns in the integrated circuit 800. In some embodiments, vias 810a, 810b, ..., 810i or 810j in the set of vias 810 are manufactured using corresponding via patterns in a set of via patterns in the integrated circuit 800.

[0392] A set of vias 810 is located in the via diffusion (VD) stages of the integrated circuit 800. In some embodiments, the VD stage is above the MD and OD stages. In some embodiments, the VD stage is between the MD and MO stages. In some embodiments, the VD stage is between the third and fourth stages. Other stages are also within the scope of this disclosure.

[0393] In some embodiments, a set of vias 810 is located where a set of contacts 806 overlaps with a set of conductors 820. In some embodiments, a set of vias 810 is located between a set of contacts 806 and a set of conductors 820.

[0394] In some embodiments, each of conductors 820d, 820g, 820e, 820h, 820f, and 820i is electrically coupled to each other in series, thereby forming a first or second resistive subnetwork of Figures 7A to 7G. For example, each of conductors 820d, 820g, 820e, 820h, 820f, and 820i is electrically coupled to each other in series and corresponds to resistor symbols 780(1) or 782(1) of Figure 7B, therefore similar detailed descriptions are omitted.

[0395] In some embodiments, each of conductors 820d, 820g, 820e, 820h, 820f, and 820i is electrically coupled to each other in series. For example, in some embodiments, conductor 820d is electrically coupled to contact 806a through via 810a, contact 806a is further electrically coupled to conductor 820g through via 810f, conductor 820g is further electrically coupled to contact 806b through via 810g, contact 806b is further electrically coupled to conductor 820e through via 810b, conductor 820e is further electrically coupled to contact 806c through via 810c, contact 806c is further electrically coupled to conductor 820h through via 810h, conductor 820h is further electrically coupled to contact 806d through via 810i, contact 806d is further electrically coupled to conductor 820f through via 810d, conductor 820f is further electrically coupled to contact 806e through via 810e, and contact 806e is further electrically coupled to conductor 820i through via 810j.

[0396] The number of other configurations, other layouts, or patterns in at least one set of vias 810 is within the scope of this disclosure.

[0397] The integrated circuit 800 also includes one or more vias 812a, 812b, ..., 812g or 812h (collectively referred to as "a set of vias 812").

[0398] A set of vias 812 is manufactured using a set of corresponding via patterns in the integrated circuit 800. In some embodiments, vias 812a, 812b, ..., 812g or 812h in the set of vias 812 are manufactured using corresponding via patterns in a set of via patterns in the integrated circuit 800.

[0399] A set of vias 812 is located at the via gate (VG) level of the integrated circuit 800. In some embodiments, the VG level is between the POLY level and the M0 level. In some embodiments, the VG level is between the second level and the fourth level. Other levels are also within the scope of this disclosure.

[0400] In some embodiments, a set of vias 812 is located at a position where a set of gates 804 overlaps with a set of conductors 820. In some embodiments, a set of vias 812 is located between a set of gates 804 and a set of conductors 820.

[0401] In some embodiments, each of conductors 820a, 820j, 820b, 820k, and 820c is electrically coupled to each other in series, thereby forming a first or second resistive subnetwork of Figures 7A to 7G. For example, each of conductors 820a, 820j, 820b, 820k, and 820c is electrically coupled to each other in series and corresponds to resistor symbols 780(1) or 782(1) of Figure 7B, therefore similar detailed descriptions are omitted.

[0402] In some embodiments, each of conductors 820a, 820j, 820b, 820k, and 820c is electrically coupled to each other in series. For example, in some embodiments, conductor 820a is electrically coupled to gate 804b through via 812a, gate 804b is further electrically coupled to conductor 820j through via 812e, conductor 820j is electrically coupled to gate 804c through via 812f, gate 804c is further electrically coupled to conductor 820b through via 812b, conductor 820b is further electrically coupled to gate 804d through via 812c, gate 804d is further electrically coupled to conductor 820k through via 812g, conductor 820k is further electrically coupled to gate 804e through via 812h, and gate 804e is further electrically coupled to conductor 820c through via 812d.

[0403] The number of other configurations, layouts, or patterns in at least one set of vias 812 is within the scope of this disclosure.

[0404] In some embodiments, at least one gate in a set of gates 804 is formed using doped or undoped polycrystalline silicon (or polycrystalline silicon). In some embodiments, at least one gate in a set of gates 804 comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0405] In some embodiments, at least one conductor of a set of contacts 806, at least one conductor of a set of conductors 820, at least one via of a set of vias 810, or at least one via of a set of vias 812 comprises one or more layers of conductive material, metal, metal compound, or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or combinations thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, etc. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, etc. In some embodiments, the doped semiconductor comprises at least doped silicon, etc.

[0406] In some embodiments, the integrated circuit 800 is configured to achieve one or more of the benefits described herein.

[0407] The quantity of other materials, configurations, arrangements on other levels, or elements in the integrated circuit 800 is within the scope of this disclosure.

[0408] Figure 9 is a diagram of a circuit 900 according to some embodiments.

[0409] In some embodiments, circuit 900 may be used as header circuit 110 of Figures 1A to 1B, therefore a similar detailed description is omitted.

[0410] Circuit 900 includes transistor 902. In some embodiments, transistor 902 is a P-type transistor. In some embodiments, transistor 902 is a PFET. In some embodiments, transistor 902 is a PMOS transistor.

[0411] Other transistor types or numbers in transistor 902 are within the scope of this disclosure. In some embodiments, transistor 902 is an N-type transistor. In some embodiments, transistor 902 is an NFET. In some embodiments, transistor 902 is an NMOS transistor.

[0412] Transistor 902 is coupled between voltage source node 104 and voltage source rail 109.

[0413] Transistor 902 is coupled to voltage source node 104 and voltage source rail 109 of voltage source TVDD. Transistor 902 is configured to receive a first voltage from the first voltage source TVDD.

[0414] Transistor 902 is also configured to receive a control signal GC. In some embodiments, the control signal GC is sent by a source (not shown). In some embodiments, transistor 902 is configured to be turned on or off in response to the control signal GC. In some embodiments, when transistor 902 is configured to be turned on, transistor 902 is configured to supply voltage to voltage source rail 109 (referred to as virtual voltage source (VDD) or second voltage source VDD).

[0415] In some embodiments, gate terminal G2 is configured to receive control signal GC. In some embodiments, drain terminal D2 is coupled to voltage source rail 109. In some embodiments, source terminal S2 is coupled to voltage source node 104 of voltage source TVDD.

[0416] Other configurations or quantities of transistor 902 are within the scope of this disclosure.

[0417] Other configurations or quantities of circuits in integrated circuit 900 are within the scope of this disclosure.

[0418] Figure 10 is a flowchart of a method 1000 for operating an ESD circuit according to some embodiments. In some embodiments, the circuitry of method 1000 includes at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400C, and 500A to 500C (Figures 1A to 1B, 2A to 2B, 3A to 3B, 4A to 4C, and 5A to 5C). It should be understood that additional operations may be performed before, during, and / or after the method 1000 depicted in Figure 10, and some other processes may only be briefly described herein. It should be understood that method 1000 utilizes features of one or more of integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 700A to 700G or 800 or circuit 600 or 900.

[0419] At operation 1002 of method 1000, a first ESD voltage is received at a first node. In some embodiments, the first node of method 1000 includes an IO pad 108. In some embodiments, the first ESD voltage is greater than the reference supply voltage VSS of the reference voltage source node 106. In some embodiments, the first ESD voltage corresponds to a first ESD event (e.g., PS mode).

[0420] At operation 1004 of method 1000, the first ESD detection circuit detects a first ESD event at the first node, thereby turning on the first ESD detection circuit and charging the first gate of the first transistor of the first discharge circuit.

[0421] In some embodiments, the detection of a first ESD event at a first node by the first ESD detection circuit includes: in response to a first ESD voltage being greater than a first trigger voltage of the first ESD detection circuit, the first ESD event at the first node is detected by the first ESD detection circuit.

[0422] In some embodiments, the first ESD detection circuit of method 1000 includes at least ESD detection circuit 201 or ESD detection circuit 401. In some embodiments, the first ESD detection circuit of method 1000 includes at least a set of diodes 502, resistors R1 or PMOS transistors P2.

[0423] In some embodiments, the first discharge circuit of method 1000 includes at least an NMOS transistor N1.

[0424] In some embodiments, a first transistor is coupled between a first node and a second node. In some embodiments, the second node is node 106 or VSS. In some embodiments, a first ESD detection circuit is coupled at least between the first node and the second node.

[0425] At operation 1006 of method 1000, the first transistor is turned on in response to the first gate of the first transistor of the first discharge circuit being charged or in response to the first ESD voltage being greater than the first trigger voltage of the first ESD detection circuit.

[0426] In some embodiments, the first trigger voltage is equal to the sum of the threshold voltages of each corresponding diode in the first set of diodes, which is part of a first ESD detection circuit.

[0427] In some embodiments, the first trigger voltage of method 1000 includes at least Vtrigger1 or Vtrigger3.

[0428] In some embodiments, the first set of diodes in method 1000 includes at least one set of diodes 202 or one set of diodes 402. In some embodiments, the first set of diodes in method 1000 includes at least one set of diodes 502 and a PMOS transistor P2.

[0429] At operation 1008 of method 1000, in response to the first transistor being turned on, the first node is coupled to the second node.

[0430] At operation 1010 of method 1000, the first ESD current of the first ESD event at the first node is discharged by the first transistor in the first ESD direction from the first node to the second node.

[0431] In some embodiments, the first ESD current corresponds to the reverse ESD direction. In some embodiments, the first ESD current includes an ESD current I2 or an ESD current I1 in the reverse ESD direction from IO pad 108 to node Nd2.

[0432] At operation 1012 of method 1000, a second ESD voltage is received at the second node.

[0433] In some embodiments, the second ESD voltage corresponds to a second ESD event (ND mode). In some embodiments, the second ESD event is negative to VDD mode.

[0434] At operation 1014 of method 1000, the second ESD detection circuit detects a second ESD event at the first node or the third node, thereby turning on the second ESD detection circuit and charging the second gate of the second transistor of the second discharge circuit.

[0435] In some embodiments, the detection of a second ESD event at a first node by the second ESD detection circuit includes: in response to a second ESD voltage being greater than a second trigger voltage of the second ESD detection circuit, the second ESD event at the first node is detected by the second ESD detection circuit.

[0436] In some embodiments, the second ESD detection circuit of method 1000 includes at least ESD detection circuit 211 or ESD detection circuit 411. In some embodiments, the second ESD detection circuit of method 1000 includes at least a set of diodes 512, resistors R2 or NMOS transistors N3.

[0437] In some embodiments, the second discharge circuit of method 1000 includes at least a PMOS transistor P1.

[0438] In some embodiments, a second transistor is coupled between a first node and a third node. In some embodiments, the third node is a voltage source rail 109 or VVDD. In some embodiments, a second ESD detection circuit is coupled between at least the first node and the third node.

[0439] At operation 1016 of method 1000, the gate of the first transistor of the discharge circuit is charged or the second transistor is turned on in response to the second ESD voltage being greater than the second trigger voltage of the second ESD detection circuit.

[0440] In some embodiments, the second trigger voltage is equal to the sum of the threshold voltages of each corresponding diode in the second set of diodes, which is part of a second ESD detection circuit.

[0441] In some embodiments, the second trigger voltage of method 1000 includes at least Vtrigger2 or Vtrigger4.

[0442] In some embodiments, the second set of diodes in method 1000 includes at least one set of diodes 212 or one set of diodes 412. In some embodiments, the second set of diodes in method 1000 includes at least one set of diodes 512 and an NMOS transistor N3.

[0443] At operation 1018 of method 1000, in response to the second transistor being turned on, the first node is coupled to the third node.

[0444] At operation 1020 of method 1000, the second ESD current of the second ESD event is discharged by the second transistor in the second ESD direction from the third node to the first node.

[0445] In some embodiments, the second ESD current corresponds to the reverse ESD direction. In some embodiments, the second ESD current includes an ESD current I4 or an ESD current I3 in the reverse ESD direction from the voltage source rail 109 to the IO pad 108.

[0446] In some embodiments, one or more operations of method 1000 are not performed.

[0447] For the sake of brevity, method 1000 is described with reference to at least a portion of Figures 1A to 1B, 2A to 2B, 3A to 3B, 4A to 4B, 5A to 5B, 6, 7A to 7G, 8A to 8D, and 9. However, according to some embodiments, method 1000 also includes operations of each of Figures 1A to 1B, 2A to 2B, 3A to 3B, 4A to 4B, 5A to 5B, 6, 7A to 7G, 8A to 8D, and 9.

[0448] In some embodiments, other operational orders of method 1000 are within the scope of this disclosure. Method 1000 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated in accordance with the spirit and scope of the disclosed embodiments.

[0449] Figure 11 is a functional flowchart of a method 1100 for manufacturing an IC device according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1100 depicted in Figure 11, and some other processes may only be briefly described herein.

[0450] In some embodiments, other operational orders of methods 1100 to 1300 are within the scope of this disclosure. Methods 1100 to 1300 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more of the operations of methods 1100, 1200, or 1300 are not performed.

[0451] In some embodiments, method 1100 is an embodiment of operation 1204 of method 1200. In some embodiments, methods 1100 to 1300 can be used to manufacture or produce at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900. In some embodiments, method 1100 can be used to manufacture or produce at least integrated circuit 800. In some embodiments, although method 1100 is described as manufacturing or producing at least integrated circuit 800, method 1100 can also be used to manufacture or produce at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, or 900.

[0452] In operation 1102 of method 1100, a set of active regions is formed.

[0453] In some embodiments, a set of active regions in method 1100 includes a set of active regions 802.

[0454] In some embodiments, operation 1102 further includes forming a set of source and drain regions of transistors in the first well. In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown on a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after its formation. In some embodiments, the first well is formed by doping the substrate. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration ranging from 1 × 10¹² atoms / cm³ to 1 × 10¹⁴ atoms / cm³.

[0455] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the concentration of the n-type dopant ranges from about 1 × 10¹² atoms / cm³ to about 1 × 10¹⁴ atoms / cm³.

[0456] In some embodiments, forming source / drain features includes: removing a portion of the substrate to form a recess at the edge of the spacer, and then performing a fill process by filling the recess in the substrate. In some embodiments, the recess is etched (e.g., wet or dry etching) after removing the pad oxide layer or sacrificial oxide layer. In some embodiments, an etching process is performed to remove a portion of the top surface of the active region adjacent to the isolation region (e.g., an STI region). In some embodiments, the fill process is performed by epitaxy or epitaxial (epi) processes. In some embodiments, a growth process occurring concurrently with the etching process is used to fill the recess, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of growth and etching processes is used to fill the recess. For example, a layer of material is grown in the recess, and then the grown material is etched to remove a portion of the material. Then, a subsequent growth process is performed on the etched material until the desired thickness of the material in the recess is achieved. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, semiconductor material is deposited in the recess to form source / drain features. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the recess. In some embodiments, the epitaxial process includes selective epitaxial growth (SEG), CVD, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gas and / or liquid precursors that interact with the composition of the substrate. In some embodiments, the source / drain features include epitaxially grown silicon (epi Si), silicon carbide, or silicon-germanium. In some instances, the source / drain features of the IC device associated with the gate structure are either in-situ doped or undoped during the epitaxial process. In some instances, when the source / drain features are undoped during the epitaxial process, they are doped during a subsequent process. Subsequent doping processes are achieved through ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain features are further exposed to an annealing process after the formation of the source / drain features and / or after subsequent doping processes.

[0457] In operation 1104 of method 1100, a set of gates is formed.

[0458] In some embodiments, a set of gates includes a set of gates 804.

[0459] In some embodiments, fabricating the gate region of operation 1104 includes performing one or more deposition processes to form one or more electrical dielectric material layers. In some embodiments, the deposition processes include chemical vapor deposition (CVD), plasma-enhanced CVD (PE CVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one electrical dielectric layer, such as a gate electrical dielectric. In some embodiments, the gate region is formed using doped or undoped polycrystalline silicon (or polycrystalline silicon). In some embodiments, the gate region includes a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0460] In operation 1106 of method 1100, a first conductive material is deposited on the first stage to form a set of contacts. In some embodiments, the first stage is an MD stage.

[0461] In some embodiments, a set of contacts includes a set of contacts 806.

[0462] In operation 1108 of method 1100, a first set of vias is formed on the front side of a substrate or wafer at a VD level (e.g., VD). In some embodiments, the first set of vias in method 1100 includes at least one or more portions of a set of vias 810.

[0463] In some embodiments, operation 1108 includes forming a first set of self-aligned contacts (SACs) in an insulating layer above the front side of the wafer. In some embodiments, the first set of vias is electrically coupled to at least one set of contacts.

[0464] In operation 1110 of method 1100, a second set of vias is formed on the front side of a substrate or wafer at the VG level (e.g., VG). In some embodiments, the second set of vias in method 1100 includes at least one or more portions of a set of vias 812.

[0465] In some embodiments, operation 1110 includes forming a second set of self-aligned contacts (SACs) in an insulating layer above the front side of the wafer. In some embodiments, the second set of vias is electrically coupled to at least one set of gates.

[0466] In operation 1112 of method 1100, a second conductive material is deposited on the second stage to form a first set of conductors. In some embodiments, the second stage is an M0 stage.

[0467] In some embodiments, the first set of conductors includes a set of conductors 820.

[0468] In operation 1114 of method 1100, at least one of a set of gates or a set of contacts is electrically coupled to a first set of conductors. In some embodiments, operation 1114 is part of operation 1112.

[0469] In some embodiments, one or more of operations 1104, 1106, 1108, 1110, or 1112 of method 1100 include forming an opening in an insulating layer (not shown) on a substrate using a combination of photolithography and material removal processes. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive or negative photoresist. In some embodiments, the photolithography process includes forming a hard photomask, an anti-reflective structure, or another suitable photolithographic structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, a RIE process, laser drilling, or other suitable etching processes. The opening is then filled with a conductive material (e.g., copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material). In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the opening.

[0470] In some embodiments, at least one or more operations of method 1100 are performed by system 1500 of FIG. 15. In some embodiments, at least one method (e.g., method 1100 described above) is performed wholly or partially by at least one manufacturing system (including system 1500). One or more operations of method 1100 are performed by IC fab 1540 (FIG. 15) to manufacture IC device 1560. In some embodiments, one or more operations of method 1100 are performed by manufacturing tool 1552 to manufacture wafer 1542.

[0471] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the openings and trenches. In some embodiments, after depositing the conductive material in one or more of operations 1104, 1106, 1108, 1110, or 1112, the conductive material is planarized to provide a level surface for subsequent steps.

[0472] In some embodiments, one or more of the operations of methods 1100, 1200, or 1300 are not performed.

[0473] One or more of the operations of methods 1200 to 1300 are performed by a processing device configured to execute instructions for manufacturing integrated circuits (e.g., at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900). In some embodiments, one or more operations of methods 1200 to 1300 are performed using the same processing device as used in one or more different operations of methods 1200 to 1300. In some embodiments, a different processing device than the processing device used to perform one or more operations of methods 1200 to 1300 is used to perform one or more different operations of methods 1200 to 1300. In some embodiments, the order of other operations of methods 1100, 1200, or 1300 is within the scope of this disclosure. Methods 1100, 1200, or 1300 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations in methods 1100, 1200, or 1300 may be appropriately added, substituted, rearranged, and / or eliminated, depending on the spirit and scope of the disclosed embodiments.

[0474] Figure 12 is a flowchart of a method 1200 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1200 depicted in Figure 12, and only a few other operations may be briefly described herein. In some embodiments, method 1200 may be used to form an integrated circuit, such as at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900.

[0475] In operation 1202 of method 1200, a layout design for an integrated circuit is generated. Operation 1202 is performed by a processing device (e.g., processor 1402 (FIG. 14)) configured to execute instructions for generating the layout design. In some embodiments, the layout design of method 1200 includes one or more features similar to at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900. In some embodiments, the layout design of this application is a Graphical Database System (GDSII) file format. In some embodiments, operation 1202 corresponds to method 1300 of FIG. 13.

[0476] In operation 1204 of method 1200, an integrated circuit is fabricated based on a layout design. In some embodiments, operation 1204 of method 1200 includes fabricating at least one photomask based on the layout design, and fabricating an integrated circuit based on the at least one photomask. In some embodiments, operation 1204 corresponds to method 1100 of FIG11.

[0477] Figure 13 is a flowchart of a method 1300 for generating a layout design of an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1300 depicted in Figure 13, and this document may only briefly describe some other processes. In some embodiments, method 1300 is an embodiment of operation 1202 of method 1200. In some embodiments, method 1300 can be used to generate one or more patterns or features resembling at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900.

[0478] In some embodiments, method 1300 may be used to generate one or more layout patterns having structural relationships (including alignment, length, and width) and configurations and layers similar to one or more features of at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900. For the sake of brevity, a similar detailed description will not be described in FIG13.

[0479] In operation 1302 of method 1300, a set of active region patterns is generated or laid out in a layout design. In some embodiments, the set of active region patterns of method 1300 includes one or more regions similar to a set of active regions 802. In some embodiments, the set of active region patterns of method 1300 includes one or more patterns or similar patterns in an OD layer.

[0480] In operation 1304 of method 1300, a set of gate patterns is generated or laid out in a layout design. In some embodiments, the set of gate patterns in method 1300 includes one or more patterns similar to a set of gates 804. In some embodiments, the set of gate patterns in method 1300 includes one or more patterns or similar patterns in a POLY layer.

[0481] In operation 1306 of method 1300, a set of contact patterns is generated or laid out in a layout design. In some embodiments, the set of contact patterns in method 1300 includes one or more patterns similar to a set of contacts 806. In some embodiments, the set of contact patterns in method 1300 includes one or more patterns or similar patterns in an MD layer.

[0482] In operation 1308 of method 1300, a first set of via patterns is generated or laid out in a layout design. In some embodiments, the first set of via patterns in method 1300 includes one or more via patterns similar to at least one set of vias 810. In some embodiments, the first set of via patterns in method 1300 includes one or more patterns or similar vias in a VD layer.

[0483] In operation 1310 of method 1300, a second set of via patterns is generated or laid out in the layout design. In some embodiments, the second set of via patterns in method 1300 includes one or more via patterns similar to at least one set of vias 812. In some embodiments, the second set of via patterns in method 1300 includes one or more patterns or similar vias in the VG layer.

[0484] In operation 1312 of method 1300, a first set of conductive feature patterns is generated or laid out in a layout design. In some embodiments, the first set of conductive feature patterns of method 1300 includes one or more patterns resembling a set of conductors 820. In some embodiments, the first set of conductive feature patterns of method 1300 includes one or more patterns or similar patterns in the MO layer.

[0485] Figure 14 is a schematic diagram of a system 1400 for designing IC layout and manufacturing IC circuits according to some embodiments.

[0486] In some embodiments, system 1400 generates or lays out one or more IC layout designs described herein. System 1400 includes a hardware processor 1402 and a non-transitory computer-readable storage medium 1404 (e.g., memory 1404) encoding (i.e., storing) computer program code 1406 (i.e., a set of executable instructions 1406). The computer-readable storage medium 1404 is configured to interface with a manufacturing machine for producing integrated circuits. Processor 1402 is electrically coupled to computer-readable storage medium 1404 via bus 1408. Processor 1402 is also electrically coupled to I / O interface 1410 via bus 1408. Network interface 1412 is also electrically connected to processor 1402 via bus 1408. Network interface 1412 is connected to network 1414, enabling processor 1402 and computer-readable storage medium 1404 to be connected to external components via network 1414. Processor 1402 is configured to execute computer program code 1406 (e.g., non-transient instructions) encoded in computer-readable storage medium 1404 so that system 1400 can be used to perform some or all of the operations described in methods 1200 to 1300.

[0487] In some embodiments, the processor 1402 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0488] In some embodiments, computer-readable storage medium 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage medium 1404 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In some embodiments using optical discs, computer-readable storage medium 1404 includes compact disc read-only memory (CD-ROM), read-write burnable compact disc (CD-R / W), and / or digital video disc (DVD). In some embodiments, computer-readable storage medium 1404 is a non-transitory computer-readable storage medium.

[0489] In some embodiments, storage medium 1404 stores computer program code 1406 configured to cause system 1400 to perform methods 1200 to 1300. In some embodiments, storage medium 1404 also stores information required to perform methods 1200 to 1300, as well as information generated during the performance of methods 1200 to 1300, such as layout design 1416, user interface 1418 and manufacturing unit 1420, and / or a set of executable instructions for performing the operations of methods 1200 to 1300. In some embodiments, layout design 1416 includes one or more patterns or features similar to at least integrated circuit 800.

[0490] In some embodiments, storage medium 1404 stores instructions (e.g., computer program code 1406) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1406) enable processor 1402 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement methods 1200 to 1300 during the manufacturing process.

[0491] System 1400 includes an I / O interface 1410. The I / O interface 1410 is coupled to external circuitry. In some embodiments, the I / O interface 1410 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor arrow keys for transmitting information and commands to processor 1402.

[0492] System 1400 also includes a network interface 1412 coupled to processor 1402. Network interface 1412 allows system 1400 to communicate with a network 1414 to which one or more other computer systems are connected. Network interface 1412 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-2094. In some embodiments, methods 1200 to 1300 are implemented in two or more systems 1400, and information (e.g., layout design) and user interfaces are exchanged between different systems 1400 via network 1414.

[0493] System 1400 is configured to receive layout design related information via I / O interface 1410 or network interface 1412. This information is transmitted via bus 1408 to processor 1402 to determine a layout design for producing at least integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800, or 900. The layout design is then stored in computer-readable medium 1404 as layout design 1416. System 1400 is also configured to receive user interface related information via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as user interface 1418. System 1400 is configured to receive information relating to manufacturing unit 1420 via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as manufacturing unit 1420. In some embodiments, manufacturing unit 1420 includes manufacturing information used by system 1400. In some embodiments, manufacturing unit 1420 corresponds to photomask fabrication 1534 of FIG. 15.

[0494] In some embodiments, methods 1200 to 1300 are implemented as standalone software applications executed by a processor. In some embodiments, methods 1200 to 1300 are implemented as software applications as part of an additional software application. In some embodiments, methods 1200 to 1300 are implemented as plug-ins to a software application. In some embodiments, methods 1200 to 1300 are implemented as software applications as part of an EDA tool. In some embodiments, methods 1200 to 1300 are implemented as software applications used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout diagram of integrated circuit devices. In some embodiments, the layout diagram is stored on a non-transitory computer-readable medium. In some embodiments, the layout diagram is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout diagram generation tool. In some embodiments, the layout diagram is generated from a netlist created based on a schematic design. In some embodiments, methods 1200 to 1300 are implemented by a manufacturing apparatus to manufacture integrated circuits using a set of photomasks manufactured based on one or more layout designs generated by system 1400. In some embodiments, system 1400 is a manufacturing apparatus configured to fabricate integrated circuits using a set of photomasks fabricated based on one or more layout designs of this disclosure. In some embodiments, system 1400 of FIG. 14 generates integrated circuit layout designs that are smaller than others. In some embodiments, system 1400 of FIG. 14 generates integrated circuit structure layout designs that occupy less area and provide better wiring resources than others.

[0495] Figure 15 is a block diagram of an integrated circuit (IC) manufacturing system 1500 according to at least one embodiment of the present disclosure and an associated IC manufacturing process. In some embodiments, based on the layout diagram, the manufacturing system 1500 is used to manufacture at least one of the following: (A) one or more semiconductor photomasks or (B) at least one element in a layer of a semiconductor integrated circuit.

[0496] In Figure 15, IC manufacturing system 1500 (hereinafter referred to as "System 1500") includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC device 1560, such as design room 1520, photomask room 1530, and IC manufacturer / fab ("fab") 1540. The entities in System 1500 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of design room 1520, photomask room 1530, and IC fab 1540 are owned by a single, larger company. In some embodiments, one or more of the design room 1520, the light mask room 1530, and the IC fab 1540 coexist in a common facility and use common resources.

[0497] Design studio (or design team) 1520 generates IC design layout 1522. IC design layout 1522 includes various geometric patterns designed for IC device 1560. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various elements of the integrated circuit device 1560 to be manufactured. The various layers are combined together to form various IC features. For example, a portion of IC design layout 1522 includes various IC features such as active regions, gate electrodes, source electrodes and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1520 implements appropriate design procedures to form IC design layout 1522. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1522 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1522 may be represented in GDSII or DFII file format.

[0498] Photomask chamber 1530 includes data preparation 1532 and photomask fabrication 1534. Photomask chamber 1530 uses an IC design layout 1522 to fabricate one or more photomasks 1545 for fabricating various layers of an IC device 1560 according to the IC design layout 1522. Photomask chamber 1530 performs photomask data preparation 1532, in which the IC design layout 1522 is converted into a representative data file (RDF). Photomask data preparation 1532 provides the RDF to photomask fabrication 1534. Photomask fabrication 1534 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate (e.g., a photomask (reticle) 1545 or a semiconductor wafer 1542). The IC design layout 1522 is manipulated by photomask data preparation 1532 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fab 1540. In Figure 15, photomask data preparation 1532 and photomask fabrication 1534 are shown as separate elements. In some embodiments, photomask data preparation 1532 and photomask fabrication 1534 may be collectively referred to as photomask data preparation.

[0499] In some embodiments, mask preparation 1532 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1522. In some embodiments, mask preparation 1532 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0500] In some embodiments, mask preparation 1532 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout already processed in the OPC. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 1534, and can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0501] In some embodiments, mask preparation 1532 includes a lithography process check (LPC) that simulates the process to be implemented by IC fab 1540 to manufacture IC device 1560. The LPC simulates this process based on IC design layout 1522 to create an analog-manufactured device, such as IC device 1560. Process parameters in the LPC analog can include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after the analog-manufactured device is created by the LPC, if the shape of the simulated device is insufficient to meet design rules, the OPC and / or MRC are repeated to further refine the IC design layout 1522.

[0502] It should be understood that the above description of photomask preparation 1532 has been simplified for clarity. In some embodiments, photomask preparation 1532 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1522 during photomask preparation 1532 can be performed in various different sequences.

[0503] Following photomask preparation 1532 and during photomask fabrication 1534, a photomask 1545 or a set of photomasks 1545 is fabricated based on a modified IC design layout 1522. In some embodiments, photomask fabrication 1534 includes performing one or more photolithographic exposures based on the IC design layout 1522. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the photomask (photomask or scribe line) 1545 based on the modified IC design layout 1522. The photomask 1545 can be formed using various techniques. In some embodiments, a binary technique is used to form the photomask 1545. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, the binary version of photomask 1545 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary photomask. In another example, photomask 1545 is formed using a phase-shifting technique. In the phase-shifted photomask (PSM) version of photomask 1545, various features in the pattern formed on the photomask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifted photomask can be a decaying PSM or an alternating PSM. The photomask(s) produced by photomask fabrication 1534 are used in various processes. For example, such photomasks(s) are used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0504] IC fab 1540 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 1540 is a semiconductor foundry. For example, there may be a manufacturing facility (front-end process (FEOL) manufacturing) for front-end manufacturing of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging of IC products, and a third manufacturing facility may provide additional services to the foundry entity.

[0505] IC fab 1540 includes manufacturing tool 1552 (hereinafter referred to as "manufacturing tool 1552"), which is configured to perform various manufacturing operations on semiconductor wafer 1542 to manufacture IC device 1560 based on one or more photomasks (e.g., photomask 1545). In various embodiments, manufacturing tool 1552 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment as discussed herein capable of performing one or more suitable manufacturing processes.

[0506] IC fab 1540 manufactures IC device 1560 using one or more photomasks 1545 manufactured by photomask chamber 1530. Therefore, IC fab 1540 manufactures IC device 1560 at least indirectly using IC design layout 1522. In some embodiments, semiconductor wafer 1542 is manufactured by IC fab 1540 using one or more photomasks 1545 to form IC device 1560. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1522. Semiconductor wafer 1542 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1542 also includes one or more of various doped regions, electrical media features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0507] System 1500 is shown having a design chamber 1520, a photomask chamber 1530, or an IC fab 1540 as separate components or entities. However, it should be understood that one or more of the design chamber 1520, photomask chamber 1530, or IC fab 1540 are part of the same component or entity.

[0508] At least one of the following diode types or quantities of integrated circuits 100A to 100B, 200A to 200B, 300A to 300B, 400A to 400B, 500A to 500B, 600, 700A to 700G, 800 or 900, or other diode types or other quantities of transistors, are included within the scope of this disclosure.

[0509] Furthermore, the various NMOS or PMOS transistors shown in Figures 2A to 6 and Figure 9 have specific dopant types (e.g., N-type or P-type) and are for illustrative purposes. Embodiments of this disclosure are not limited to specific transistor types, and one or more of the PMOS or NMOS transistors shown in Figures 2A to 6 and Figure 9 can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of various signals used in the above description are also for illustrative purposes. Embodiments of this disclosure are not limited to specific logic values ​​when enabling and / or disabling signals. Different logic values ​​are selected within the range of various embodiments. Different numbers of PMOS transistors are selected within the range of various embodiments in Figures 2A to 6 and Figure 9.

[0510] One aspect of this specification relates to integrated circuits. In some embodiments, the integrated circuit includes a buffer circuit coupled between a first node and a second node. In some embodiments, the integrated circuit also includes an input / output (I / O) pad coupled to the buffer circuit, the buffer circuit being configured to output a first signal to the I / O pad. In some embodiments, the integrated circuit also includes a first clamping circuit coupled between the I / O pad and the second node and configured to clamp a first electrostatic discharge (ESD) event at the I / O pad or the second node. In some embodiments, the integrated circuit also includes a second clamping circuit coupled between the I / O pad and the first node and configured to clamp a second ESD event at the I / O pad or the first node.

[0511] Another aspect of this specification relates to integrated circuits. In some embodiments, the integrated circuit includes a buffer circuit having an input and an output and being coupled between a first node and a second node. In some embodiments, the integrated circuit also includes an input / output (I / O) pad coupled to the output of the buffer circuit, the I / O pad being configured to receive a first signal from the buffer circuit. In some embodiments, the integrated circuit also includes a first clamping circuit coupled between the I / O pad and the second node and configured to clamp a first electrostatic discharge (ESD) event at the I / O pad or the second node. In some embodiments, the integrated circuit also includes a second clamping circuit coupled between the I / O pad and the first node and configured to clamp a second ESD event at the I / O pad or the first node. In some embodiments, the integrated circuit also includes a header circuit coupled between the first node and a third node, the header circuit being coupled to a first voltage source having a first power supply voltage and configured to provide the first power supply voltage to the first node in response to a control signal.

[0512] Another aspect of this specification relates to a method of operating an ESD circuit. In some embodiments, the method includes receiving a first ESD voltage at a first node, the first ESD voltage being greater than a reference supply voltage of a reference voltage source, the first ESD voltage corresponding to a first ESD event. In some embodiments, the method further includes detecting the first ESD event at the first node by a first ESD detection circuit, thereby causing the first ESD detection circuit to conduct and charge a first gate of a first transistor of a first discharge circuit, the first transistor being coupled between the first node and a second node, and the first ESD detection circuit being coupled between at least the first node and the second node. In some embodiments, the method further includes discharging a first ESD current of the first ESD event by the first transistor in a first ESD direction from the first node to the second node.

[0513] Several embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of this disclosure. For example, various transistors of a particular dopant type (e.g., N-type or P-type metal-oxide-semiconductor (NMOS or PMOS)) are shown for illustrative purposes. Embodiments of this disclosure are not limited to a particular type. Different dopant types are selected for a particular transistor within the scope of various embodiments. The low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. Embodiments of this disclosure are not limited to a particular logic value when the signal is enabled and / or disabled. Different logic values ​​are selected within the scope of various embodiments. In various embodiments, the transistor is used as a switch. Switching circuits used instead of transistors are within the scope of various embodiments. In various embodiments, the source of the transistor can be configured as a drain, and the drain can be configured as a source. Therefore, the terms source and drain can be used interchangeably. Various signals are generated by corresponding circuits, but these circuits are not shown for simplicity.

[0514] For illustration, the accompanying figures show capacitor circuits using discrete capacitors. Equivalent circuits can be used. For example, capacitor elements, circuits, or networks (e.g., combinations of capacitors, capacitor elements, devices, circuits, etc.) can be used instead of discrete capacitors. The above description includes exemplary steps, but these steps are not necessarily performed in the order shown. Steps may be appropriately added, substituted, changed in order, and / or eliminated according to the spirit and scope of the disclosed embodiments.

[0515] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0516] 100A, 100B, 200A, 200B, 300A, 300B, 400A, 400B, 500A, 500, 600, 800, 900: Integrated circuits 102: Internal Circuitry 104: Voltage source node 106: Reference Voltage Source Node 108: Input / Output Pads 109: Voltage Source Rail 110: Header Circuit 112: Electric clamping device 114: Electric Clamping Device 116: Buffer circuit 120, 130: ESD clamp 201, 211, 401, 411: ESD detection circuits 202, 212, 402, 412, 502, 512: A group of diodes 501, 511: Circuits 550, 550a: First path 552: Second Path 514: Diode-coupled transistor 602, 902: Transistors 700A, 700B, 700C, 700D, 700E, 700F, 700G: Resistor Networks 718B(0) to 718B(m-1), 718F(0) to 718F(m-1), 718G(0) to 718G(m-1): Unit region 780(0), ..., 780(m-1): Resistors 782(0), ..., 782(m-1): Resistors 784(1): First Resistor Subnet 784(2): Second Resistor Network 772, 772(14), 772(15), 772(16), 772(17): M1 conductor 770: Via 784(3), 784(4), 784(5), 784(6), 784(7), 784(8), 784(9), 784(10), 784(11), 784(12): Current path 800A, 800B: Partial 801: Unit 801a, 801b, 801c and 801d: Element boundaries 802, 802a, 802b: Active regions 803: Insulation Area 804: A set of gates 804a, 804b, 804c, 804d, 804e, 804f: Gate 806: A set of contacts 806a, 806b, 806c, 806d, 806e: Contact elements 810: A set of vias 810a, 810b, ..., 810j: Vias 812: A set of vias 812a, 812b, ..., 812h: Vias 820: In a group of conductors 820a, 820b, ..., 820k: Conductors 830: A set of grid lines 830, 830a, 830b, 830c, 830d, 830e: Grid lines 820a, 820b and 820c: Conductors 890: Substrate 1000: Method 1002-1020: Operation 1100: Method 1102-1114: Operation 1200: Method 1202-1204: Operation 1300: Method 1302-1312: Operation 1000: Method 1002-1020: Operation 1400: System 1402: Processor 1404: Storage Media 1406: Instruction 1408: Busbar 1410:I / O interface 1412: Network Interface 1414: Internet 1416: Layout Design 1418: User Interface 1420: Manufacturing Unit 1500: IC Manufacturing System 1520: Design Studio 1522: IC Design Layout Diagram 1530: Light Cover Chamber 1532: Data Preparation 1534: Photomask Manufacturing 1540: IC Manufacturer 1542: Wafer 1545: Light Mask 1552 Manufacturing Tools 1560: IC Devices

Claims

1. An electrostatic discharge protection circuit, comprising: A buffer circuit is coupled between the first node and the second node; Input / output (IO) pads coupled to the buffer circuit, the buffer circuit being configured to output a first signal to the IO pads; a first clamping circuit coupled between the IO pads and the second node and configured to clamp a first electrostatic discharge (ESD) event at the IO pads or the second node. And a second clamping circuit, coupled between the IO pad and the first node and configured to clamp a second ESD event at the IO pad or the first node.

2. The electrostatic discharge protection circuit as described in claim 1, wherein, The first clamping circuit includes: a first ESD detection circuit coupled between the IO pad and the second node; and a first transistor of a first type, the first transistor including a first gate coupled to at least the first ESD detection circuit via a third node, a first drain coupled to the IO pad, and a first source coupled to the second node.

3. The electrostatic discharge protection circuit as described in claim 2, wherein, The first ESD detection circuit includes: a first set of diodes coupled in series with each other and coupled between the IO pad and the third node; and a first resistor coupled between the third node and the second node.

4. The electrostatic discharge protection circuit as described in claim 3, wherein, The first set of diodes includes: a first diode including a first anode and a first cathode, the first anode being coupled to the IO pad; a second diode including a second anode and a second cathode, the second anode being coupled to the first cathode; and a third diode including a third anode and a third cathode, the third anode being coupled to the second cathode.

5. The electrostatic discharge protection circuit as described in claim 4, wherein, The third cathode is coupled to the third node, the first gate, and the first end of the first resistor.

6. The electrostatic discharge protection circuit as described in claim 4, wherein, The first clamping circuit further includes: a fourth diode, comprising a fourth anode and a fourth cathode, the fourth anode being coupled to the IO pad and the fourth cathode being coupled to the first drain.

7. The electrostatic discharge protection circuit as described in claim 6, wherein, The first set of diodes further includes: a fifth diode, comprising a fifth anode and a fifth cathode, wherein the fifth anode is coupled to the third cathode, and the fifth cathode is coupled to the third node, the first gate, and the first end of the first resistor.

8. The electrostatic discharge protection circuit as described in claim 7, wherein, The second clamping circuit includes: a second ESD detection circuit coupled between the IO pad and the first node; and a second transistor of a second type different from the first type, the second transistor including a second gate coupled to at least the second ESD detection circuit via a fourth node, a second drain coupled to the IO pad, and a second source coupled to the second node.

9. An electrostatic discharge protection circuit, comprising: A buffer circuit, including an input and an output, coupled between a first node and a second node; an input / output (IO) pad coupled to the output of the buffer circuit, the IO pad being configured to receive a first signal from the buffer circuit; and a first clamping circuit coupled between the IO pad and the second node and configured to clamp a first electrostatic discharge (ESD) event at the IO pad or the second node. A second clamping circuit is coupled between the IO pad and the first node and is configured to clamp a second ESD event at the IO pad or the first node. A header circuit is coupled between the first node and the third node, the header circuit being coupled to a first voltage source having a first power supply voltage and configured to provide the first power supply voltage to the first node in response to a control signal.

10. A method for operating an electrostatic discharge protection circuit, the method comprising: A first ESD voltage is received at the first node, the first ESD voltage being greater than the reference supply voltage of the reference voltage source, and the first ESD voltage corresponding to a first ESD event. The first ESD event at the first node is detected by the first ESD detection circuit, thereby turning on the first ESD detection circuit and charging the first gate of the first transistor of the first discharge circuit. The first transistor is coupled between the first node and the second node, and the first ESD detection circuit is coupled between at least the first node and the second node. And the first ESD current discharge of the first ESD event caused by the first transistor in the first ESD direction from the first node to the second node.

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