Semiconductor device and methods of forming the same

Abstract

A method includes forming a stack of semiconductor layers over a substrate; etching the stack to form a first fin and a second fin, the first fin having a first width and the second fin having a second width greater than the first width; etching a first groove in the first fin and etching a second groove in the second fin; performing a deposition process to grow a first epitaxial region in the first groove and a second epitaxial region in the second groove; wherein at a first point in the deposition process, a first protrusion height of the first epitaxial region is higher than a second protrusion height of the second epitaxial region; and wherein at a second point in the deposition process, a third protrusion height of the first epitaxial region is lower than a fourth protrusion height of the second epitaxial region, the second point being after the first point.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on them.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, more challenges may arise that need to be addressed. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] When read with reference to the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates a three-dimensional view of an exemplary nanostructured field-effect transistor (nano-FET) according to some embodiments. Figure 2-18E illustrates different views of intermediate steps in the fabrication of nano-FET transistors according to some embodiments. Figures 19A-24B illustrate different views of the intermediate steps in forming the source / drain regions of a nano-FET, according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0008] In various embodiments, a transistor is formed above a semiconductor substrate. The transistor may be a nanoFET (e.g., a p-type nanoFET), although any suitable type of transistor may be used in the embodiments disclosed herein. According to some embodiments, a first fin and a second fin are formed above the semiconductor substrate, a first dummy gate structure is formed across the first fin, and a second dummy gate structure is formed across the second fin. The first fin has a narrower width, and the second fin has a wider width. A first groove may be etched in the first fin between the first dummy gate structures, and a second groove may be etched in the second fin between the second dummy gate structures. Epitaxial source / drain regions are formed such that a first epitaxial region is formed in the first groove and a second epitaxial region is formed in the second groove. Embodiments of forming epitaxial source / drain regions can prevent or reduce certain loading effects associated with the difference between the first and second widths. For example, in the initial stage, the growth rate of the first epitaxial region is faster than the growth rate of the second epitaxial region. In later stages, the growth rate of the second epitaxial region is faster than the growth rate of the first epitaxial region. The dynamic relationship between growth rates provides better control, such as ensuring that the bump height of the second epitaxial region is greater than or equal to the bump height of the first epitaxial region. Therefore, contact plugs to each epitaxial source / drain region can then be formed simultaneously, providing sufficient contact area in both cases to improve the yield and performance of the transistor and the overall integrated circuit element.

[0009] The embodiments described below are in the specific context of a wafer including nano-FETs. However, various embodiments can be applied to wafers including other types of transistors (e.g., stacked transistors, etc.) to replace or combine with nano-FETs.

[0010] Figure 1 illustrates an example of nano-FETs (e.g., nanosheets, nanowires, or the like) in a three-dimensional view according to some embodiments. For ease of illustration, certain features are simplified and / or omitted in Figure 1. The nano-FETs include nanostructures 54 (e.g., nanosheets, nanowires, etc.) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 54 serve as channel regions for the nano-FETs. The nanostructures 54 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 (also referred to as STI structures or STI regions) are disposed between adjacent fins 66, which may protrude above and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of fin 66 is depicted as a single, continuous material together with substrate 50, the bottom portion of fin 66 and / or substrate 50 may comprise a single material or multiple materials. In this document, fin 66 refers to the portion extending between adjacent STI regions 68.

[0011] In some embodiments, the semiconductor substrate may have a (001) or (110) lattice orientation. As discussed in more detail below, the (110) orientation facilitates some advantageous growth modes for epitaxial layers formed in subsequent steps, such as the formation of source / drain regions. This provides better control and additional options for forming such epitaxial layers along semiconductor surfaces of different shapes and sizes. According to various embodiments, the source / drain regions formed on a (110) oriented substrate may have an upper facet along the Z-plane to the Y-plane at an angle of 35.3°, while on a (001) oriented substrate, the facet angle may be 54.7°. Therefore, the flake coverage of the (110) oriented substrate may be improved. Furthermore, the final critical size of the source / drain regions along the Y direction on a (110) oriented substrate may be larger than that on a (001) oriented substrate. Therefore, the protrusion height of the source / drain regions in the Z direction on the (110) crystal orientation substrate may be lower than that on the (001) crystal orientation substrate (e.g., due to slower growth rate). Furthermore, the height difference between source / drain regions of different sizes (e.g., different channel widths) will also decrease as the (110) direction decreases.

[0012] The gate dielectric layer 100 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 54. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite side of the gate dielectric layer 100 and the gate electrode 102. The source / drain regions 92 may refer individually or collectively to the source or drain, depending on the context.

[0013] Figure 1 further illustrates the reference cross-sections used in subsequent figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 102 and, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the nano-FET fin 66, and along, for example, the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the nano-FETs. For clarity, these reference cross-sections are referenced in subsequent figures.

[0014] Some of the embodiments discussed herein are discussed in the context of nano-FETs formed using a post-gate fabrication process. In other embodiments, a gate-first fabrication process may be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0015] Figures 2-24B are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Figures 2, 3, 4, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, and 18A show the reference cross-section A-A' shown in Figure 1. Figures 5B, 6B, 7B, 8B, 9B, 10B, 10C, 10D, 11B, 12B, 13B, 14B, 15B, 15C, 16B, 17B, and 18B show the reference cross-section B-B' shown in Figure 1. Figures 7C, 11C, 11D, 11E, 11F, 16C, 17C, 18C, 18D, 18E, 22A, 22B, 23A, 23B, 24A, and 25B show the reference section C-C' shown in Figure 1. Figures 11E, 11F, 18D, 18E, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, and 24B show the planar section D-D' shown in the corresponding figures.

[0016] In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is located on the substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0017] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, or n-type nano-FETs, while the p-type region 50P can be used to form p-type devices, such as PMOS transistors, or p-type nano-FETs. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator line 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. Unless otherwise stated, subsequent figures describe the process steps that can be performed in the n-type region 50N or the p-type region 50P.

[0018] In Figure 2, a multilayer stack 64 is formed above the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A, 51B, and 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A, 53B, and 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 will be removed, and the second semiconductor layer 53 will be patterned to form channel regions for nano-FETs in the n-type region 50N and the p-type region 50P. However, in some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form channel regions for nano-FETs in the n-type region 50N and the p-type region 50P. For example, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or other semiconductor materials) and be formed simultaneously.

[0019] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of nano-FETs in the p-type region 50P, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of nano-FETs in the n-type region 50N. In another embodiment, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of nano-FETs in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of nano-FETs in the p-type region 50P. In such embodiments, the channel region of the n-type region 50N may have a different material composition than the channel region of the p-type region 50P. The first semiconductor layer 51 and the second semiconductor layer 53 may be selectively removed from each of the n-type region 50N and the p-type region 50P through additional masking and etching steps. For example, the channel region of the n-type region 50N can be a silicon channel region, while the channel region of the p-type region 50P can be a silicon-germanium channel region.

[0020] For ease of illustration, the multilayer stack 64 is shown as including each of three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar processes.

[0021] In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material, such as silicon, silicon carbon, or the like. The first and second semiconductor materials may be materials with high etch selectivity to each other. In this way, the first semiconductor layer 51 composed of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 composed of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form channel regions for nano-FETs.

[0022] Referring now to Figure 3, according to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in a multilayer stack 64 (as shown in Figure 2). In some embodiments, nanostructures 55 and fins 66 can be formed in the multilayer stack 64 (as shown in Figure 2) and the substrate 50 respectively by etching trenches 58 in the multilayer stack 64 (as shown in Figure 2). This etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching can be anisotropic. During the etching process, a hard mask can be used to define the pattern of fins 66 and nanostructures 55. The hard mask can include any suitable insulating material, such as oxides, nitrides, oxynitrides, oxycarbonitrides, or similar materials. In some embodiments (not shown separately), the hard mask can be a multilayer structure. The hard mask can be formed over the nanostructures 55 using acceptable processes such as thermal oxidation, physical vapor deposition (PVD), CVD, ALD, combinations thereof, etc.

[0023] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns, for example, with a smaller pitch than those obtained using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Then, spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 66 and nanostructures 55 are patterned using the remaining spacers.

[0024] Nanostructure 55 is formed by etching multiple layers stacked 64 (as shown in Figure 2). First nanostructures 52A, 52B, and 52C (collectively referred to as first nanostructure 52) can be further defined from the first semiconductor layer 51, and second nanostructures 54A, 54B, and 54C (collectively referred to as second nanostructure 54) can be defined from the second nanolayer 53. First nanostructure 52 and second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0025] Figure 3 illustrates fins 66 with substantially equal widths for illustrative purposes. In some embodiments, the width of fin 66 in the n-type region 50N is smaller than the width of fin 66 in the p-type region 50P. Furthermore, although Figure 3 shows each of the fins 66 and nanostructures 55 having a consistently consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 continuously increases along the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0026] In Figure 4, a shallow trench isolation (STI) region 68 is formed adjacent to fin 66. The STI region 68 can be formed by filling the trench 58 with an insulating material deposited over the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, similar materials, or combinations thereof, and can be formed using high-density plasma CVD (HDP-CVD), flow CVD (FCVD), similar materials, or combinations thereof. Other insulating materials can be formed using any acceptable process. In this embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process is performed when the insulating material is formed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is depicted as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fin 66, and nanostructure 55. Subsequently, a filler material as described above can be formed on the liner.

[0027] Next, a removal process is performed on the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, or a combination thereof, can be used. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the nanostructure 55 and the top surface of the insulating material are at the same level.

[0028] Next, the insulating material is recessed to form STI region 68. The recessed insulating material causes the upper portion of fin 66 to protrude from between adjacent STI regions 68. Furthermore, the top surface of STI region 68 can be a plane, a convex surface, a concave surface (e.g., recessed), or a combination thereof, as shown. The top surface of STI region 68 can be formed as flat, convex, and / or recessed by appropriate etching. An acceptable etching process can be used to recess STI region 68, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the materials of fin 66 and nanostructure 55). For example, dilute hydrofluoric acid (dHF) can be used to remove oxides. Subsequently, an optional hard mask (not shown separately) can be formed on the top surface of STI region 68 to cover STI region 68. The hard mask can be formed from nitrides or other materials with etching selectivity for STI region 68 (e.g., etching selectivity for the filling material of STI region 68).

[0029] Additionally, in Figure 4, suitable wells (not shown separately) may be formed in the first semiconductor layer 51, the second semiconductor layer 53, and / or the substrate 50. In embodiments with different types of wells, photoresist or other masks (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist may be formed over the structure of the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using spin coating techniques and patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type dopant is implanted into the p-type region 50P, and the photoresist may act as a mask to substantially prevent the n-type dopant from being implanted into the n-type region 50N. The n-type dopant may be phosphorus, arsenic, antimony, or similar substances, implanted into the region at a concentration ranging from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed by an acceptable ashing process.

[0030] After or before implantation in the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the structure in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type dopant is implanted in the n-type region 50N, and the photoresist acts as a mask to substantially prevent the implantation of the p-type dopant into the p-type region 50P. The p-type dopant can be boron, boron fluoride, indium, or a similar dopant, implanted into the region at a concentration ranging from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed by an acceptable ashing process.

[0031] After implantation into the n-type region 50N and the p-type region 50P, an annealing process is performed to repair implantation damage and activate the implanted p-type and / or n-type dopants. In some embodiments, the substrate 50 may be implanted before the formation of the first semiconductor layer 51 and the second semiconductor layer 53. Subsequently, the growth materials of the first semiconductor layer 51 and / or the semiconductor layer 53 may be in-situ doped during the growth process. Alternatively, one or more of the first semiconductor layer 51 and / or the second semiconductor layer 53 may be implanted.

[0032] In Figures 5A and 5B, a dummy gate 76 is formed along and above the sidewalls of nanostructure 55 and fin 66. To form the dummy gate 76, a dummy dielectric layer is first formed on fin 66 and / or nanostructure 55. The dummy dielectric layer can be made of silicon oxide, silicon nitride, combinations thereof, or similar materials, and can be deposited or thermally grown according to acceptable techniques. The dummy gate layer is formed above the dummy dielectric layer, and a masking layer is formed above the dummy gate layer. The dummy gate layer can be deposited above the dummy dielectric layer and then planarized, for example, through a CMP process. The masking layer can be deposited above the dummy gate layer. The dummy gate layer can be a conductive or non-conductive material, and can be one of amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline silicon germanium), metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer can be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer can be made of other materials that exhibit high etch selectivity with the etching of the isolation region. The masking layer can include, for example, silicon nitride, silicon oxynitride, etc.

[0033] Subsequently, a mask layer is patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of mask 78 can then be transferred to a dummy gate layer and a dummy dielectric layer to form a dummy gate 76 and a dummy gate dielectric 70, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66. It should be noted that, for illustrative purposes, the dummy gate dielectric 70 shown only covers the fin 66 and the nanostructure 55. In some embodiments, the dummy gate dielectric 70 may be deposited such that the dummy gate dielectric 70 covers the STI region 68, such that the dummy gate dielectric 70 extends between the dummy gate 76 and the STI region 68.

[0034] In Figures 6A and 6B, a gate spacer 81 is formed above the nanostructure 55 and the STI region 68, on the exposed sidewalls of the mask 78 (if present), above the dummy gate 76, and above the dummy gate dielectric 70. The gate spacer 81 can be formed by conformally forming one or more dielectric materials and subsequently etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or similar materials, which can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar deposition processes. Other insulating materials formed through any acceptable process can be used. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to pattern the dielectric material. The etching can be anisotropic. During etching, a portion of the dielectric material remains on the sidewalls of the dummy gate 76 (thus forming the gate spacer 81). As will be described in more detail later, some dielectric material may remain on the sidewalls of the semiconductor fin 66 and / or nanostructure 55 during etching (thus forming fin spacers 83, see Figure 7C). After etching, the fin spacers 83 and / or gate spacers 81 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0035] In Figures 7A-7C, according to some embodiments, a first groove is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in Figure 7C, the top surface of the STI region 68 may be level with the bottom surface of the first groove 86. In other embodiments, the fin 66 may be etched to position the bottom surface of the first groove 86 above or below the top surface of the STI region 68. The first groove 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process, such as RIE, NBE, or a similar process. Gate spacers 81, fin spacers 83, and a mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the first groove 86. Each layer of nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first groove 86 after it reaches the desired depth.

[0036] In Figures 8A-9B, the first nanostructure 52 is replaced by a sacrificial material 72 (also referred to as a one-time oxide interposer (DOI) 72). Replacing the first nanostructure 52 may include etching it away using a suitable etching process (e.g., an isotropic etching process) through the first groove 86, as shown in Figures 8A-8B. The etching process may selectively select the material of the first nanostructure 52 and remove it without significantly removing the second nanostructure 54 or the semiconductor fin 66. Therefore, the etching process may result in gaps or voids (not specifically described) between adjacent second nanostructures 54. In some embodiments, during the removal of the first nanostructure 52, the second nanostructures 54, particularly the corner regions of the second nanostructure 54, may be slightly etched. For example, due to the removal of the first nanostructure 52, the corner regions of the second nanostructure 54 may be further apart than the central regions of the second nanostructure 54 (see Figure 18C). In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process can be performed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or similar substances to remove the first nanostructure 52.

[0037] Subsequently, a sacrificial material layer 71 is deposited in the first groove 86 and in the space after the removal of the first nanostructure 52. The sacrificial material layer 71 can be deposited using a conformal deposition process, such as CVD, ALD, or a similar process. The sacrificial material layer may include an insulating material, such as silicon oxide (e.g., SiO2) or similar materials, which can be selectively etched from the second nanostructure 54. In Figures 9A and 9B, the sacrificial material layer 71 can then be etched to form a sacrificial material 72. This etching can be isotropic or anisotropic. For example, diluted HF or similar materials can be used as an etchant to etch the sacrificial material layer using a wet etching process. In some embodiments, etching is performed until the sidewalls of the sacrificial material 72 are recessed into the sidewalls of the nanostructure 54. Although the sidewalls of the sacrificial material 72 are shown as straight in Figure 9B, the sidewalls can be concave or convex (e.g., see Figure 10C).

[0038] Replacing the first nanostructure 52 with sacrificial material 72 can offer advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes can be performed, such as activating dopants in the source / drain regions. When the material of the first nanostructure 52 (e.g., SiGe) is exposed to high temperatures, it can lead to germanium mixing and increased roughness at the interface between nanostructure 52 and nanostructure 54. Such manufacturing defects can degrade the performance of the final transistor device. For example, when germanium diffuses into the second nanostructure 54, germanium residues may remain in the channel regions of the resulting transistor device, negatively impacting the performance of the channel regions. By replacing the first nanostructure 52 with an insulating material prior to high-temperature processes (e.g., source / drain annealing processes), manufacturing defects can be reduced and device performance improved (e.g., increased current drive, reduced capacitance, and improved short-channel effects).

[0039] In Figures 10A and 10B, an inner spacer 90 is formed in a first groove 86 on the sidewall of the sacrificial material 72. The inner spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first groove 86, and the sacrificial material 72 will be replaced by the corresponding gate structure. The inner spacer 90 also serves to prevent subsequent etching processes (e.g., etching processes used to form the gate structure) from damaging the subsequently formed source / drain regions.

[0040] The inner spacer 90 can be formed by depositing an inner spacer layer (not shown separately) on the structure shown in Figures 9A and 9B. The inner spacer layer can be deposited using a conformal deposition process (e.g., CVD, ALD, etc.). The inner spacer layer can include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The inner spacer layer can then be anisotropically etched to form the inner spacer 90. The inner spacer layer can be etched using anisotropic etching processes (e.g., RIE, NBE, etc.).

[0041] Although the outer side of the inner spacer 90 is necessarily drawn flush with the sidewall of the second nanostructure 54, the outer sidewall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (see, for example, Figure 10C). Furthermore, although the outer sidewall of the inner spacer 90 is drawn straight in Figure 10B, it may be concave or convex. As an example, Figure 10C shows an embodiment where the sidewall of the sacrificial material 72 is concave, the outer sidewall of the inner spacer 90 is concave, and the inner spacer 90 is recessed from the sidewall of the second nanostructure 54. Other configurations are also possible. For example, Figure 10D shows an embodiment where the sidewall of the sacrificial material 72 is concave, the outer sidewall of the inner spacer 90 is straight, and the inner spacer 90 is flush with the sidewall of the second nanostructure 54.

[0042] In Figures 11A-11F, epitaxial source / drain regions 92 are formed in a first recess 86. In some embodiments, the source / drain regions 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. As shown in Figure 11B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, while inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the sacrificial material 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit with the gates of subsequently formed nano-FETs.

[0043] Epitaxial source / drain regions 92 in the n-type region 50N (e.g., NMOS region) can be formed by shielding the p-type region 50P (e.g., PMOS region). Next, the epitaxial source / drain regions 92 are epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for n-type nano-FETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 in the n-type region 50N can comprise a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or similar materials.

[0044] Epitaxial source / drain regions 92 in the p-type region 50P (e.g., PMOS region) can be formed by shielding the n-type region 50N (e.g., NMOS region). Next, the epitaxial source / drain regions 92 are epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain regions 92 can include any acceptable material suitable for p-type nano-FETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 in the p-type region 50P can include materials that apply tensile strain to the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or similar materials.

[0045] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the process for forming lightly doped source / drain regions discussed earlier, followed by annealing. The impurity concentration of the source / drain region can be between about 1 x 10¹⁹ atoms / cm³ and about 1 x 10²¹ atoms / cm³. The n-type and / or p-type impurities in the source / drain region can be any impurities discussed earlier. In some embodiments, the epitaxial source / drain region 92 can be in-situ doped during growth.

[0046] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nano-FET to merge, as shown in Figure 11C. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in Figure 11D. In the embodiments shown in Figures 11C and 11D, fin spacers 83 may be formed on the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, the fin spacers 83 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the fin spacers 83 may be omitted entirely, and the epitaxial growth region may extend to the top surface of the STI region 68.

[0047] Epitaxial source / drain regions 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials, and may be doped with different dopant concentrations. In some embodiments, the doping concentration of the first semiconductor material layer 92A may be less than that of the second semiconductor material layer 92B, and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0048] In some embodiments, the first semiconductor material layer 92A may include two distinct layers (not separately labeled). For example, the first semiconductor material layer 92A may include an initial layer L0 and a first layer L1. The initial layer L0 may include boron-doped silicon (Si:B) or boron-doped silicon germanium (Si1-xGex:B, where 0<x<0.1) with a boron concentration of up to 1.0E21 atoms / cm3, and may be formed over the exposed semiconductor material (e.g., nanostructures 54 and the substrate 50) at a relatively high temperature between 600°C and 800°C. The first layer L1 may include boron-doped silicon germanium (Si1-xGex:B, where 0.1≤x≤0.4) with a boron concentration of up to 7.0E20 atoms / cm3, and may be formed over the exposed semiconductor material (e.g., the initial layer L0) at a lower temperature between 400°C and 600°C.

[0049] Furthermore, the second semiconductor material layer 92B and the third semiconductor material layer 92C may sometimes be discussed together or separately. The second semiconductor material layer 92B is sometimes referred to as the second layer L2, and the third semiconductor material layer 92C is sometimes referred to as the third layer L3. The second layer L2 may include boron-doped silicon germanium (Si1-xGex:B, where 0.4≤x≤0.9) with a boron concentration greater than or equal to 7.0E20 atoms / cm3, and may be formed on the exposed semiconductor material (e.g., the first layer L1) at a lower temperature between 400°C and 600°C. The third layer L3 may be formed within the above parameters related to forming the second layer L2, although its dopant concentration is lower than that of the other layers.

[0050] Figures 11E and 11F illustrate additional views of forming an exemplary epitaxial source / drain region 92 according to some embodiments. In some embodiments, the epitaxial source / drain region 92 shown may be a component of a PMOS transistor (e.g., p-type nano-FETs). It should be noted that each top view depicts a side cross-sectional view similar to Figures 11C and 11D, along with some components of the foreground or background (e.g., dashed outlines) for reference. Each bottom view depicts a plan view of the reference cross-section D-D' marked in the corresponding top view.

[0051] Figure 11E shows the epitaxial source / drain region 92N of one or more narrow-channel nano-FETs (e.g., narrow nanostructure 54N and narrow fin 66N), and Figure 11F shows the epitaxial source / drain region 92W of one or more wide-channel nano-FETs (e.g., wide nanostructure 54W and wide fin 66W). As shown, the terms "narrow" and "wide" can refer to the width W (e.g., width WN and width WW, respectively) of the fin 66 of each nano-FET (e.g., narrow-channel region 54N and wide-channel region 54W of nanostructure 54). For simplicity, the respective epitaxial source / drain regions 92 can be referred to as narrow epitaxial 92N and wide epitaxial 92W.

[0052] In some embodiments, narrow epitaxial 92N is formed along nanostructure 54N, with a width WN ranging from 5 nm to 20 nm, and wide epitaxial 92W is formed along nanostructure 54W, with a width WW ranging from 60 nm to 100 nm. Furthermore, the distance DN between adjacent dummy gates 76N can be substantially equal to the distance DW between adjacent dummy gates 76W (e.g., substantially the same pitch). For example, the distances DN and DW can range from 10 nm to 50 nm, or can be from width WN to width WW. Furthermore, in embodiments where substrate 50 has a (110) lattice orientation, fins 66N can be parallel or perpendicular to fins 66W without intersecting, and dummy gates 76N can be parallel or perpendicular to dummy gates 76W without intersecting. As shown, narrow epitaxial 92N and wide epitaxial 92W can be grown simultaneously, wherein the wide epitaxial 92W has a faster overall growth rate than the narrow epitaxial 92N. The fabrication process can be terminated when the bump height hW of the wide epitaxial layer 92W is approximately equal to or greater than the bump height hN of the narrow epitaxial layer 92N. It should be noted that the bump height hN / hW can be measured starting from the lower fin 66 (e.g., the point on the epitaxial source / drain region 92 closest to the substrate 50), however, any suitable reference point can be used to determine the desired height. Therefore, the bump height difference Δh (e.g., hW-hN) can range from 0 nm to 60 nm.

[0053] As further shown in the figures, the epitaxial source / drain regions can be formed in various shapes. For example, the general shapes provided in Figures 11E and 11F differ from those provided in Figures 11C and 11D. Referring to Figures 11E and 11F, the epitaxial material can be grown with certain facets having a flatter angle (e.g., an angle of 35.3°) relative to the horizontal plane (e.g., the main plane of the substrate 50). This flatter angle allows for better control over the formation of the epitaxial source / drain regions 92 to achieve the desired bump height hN / hW (e.g., the desired bump height difference Δh) for each type.

[0054] Many advantages can be achieved through the above-described process for forming the epitaxial source / drain regions 92. The geometry of the narrow epitaxial layer 92N and the wide epitaxial layer 92W is advantageous for certain growth rates throughout the process, thereby allowing for better control over the final dimensions of the corresponding epitaxial source / drain regions 92. For example, the growth rate of the first semiconductor material layer 92AN of the narrow epitaxial layer 92N is typically greater than that of the first semiconductor material layer 92AW of the wide epitaxial layer 92W, due to the reduced circulation within the first groove 86W of the wide epitaxial layer 92W caused by WW>WN and DW≈DN. Specifically, this results in reduced circulation of the deposition precursor reaching the sidewalls of the nanostructure 54W. However, as shown in the figure below, the trapezoidal growth pattern eventually becomes a triangular pattern of the first semiconductor material layer 92AN of the narrow epitaxial layer 92N, or a merged trapezoidal pattern of the first semiconductor material layer 92AW of the wide epitaxial layer 92W. In some embodiments, when a triangular pattern is used, the growth rate of the first semiconductor material layer 92AN is significantly slower, less than the growth rate of the first semiconductor material layer 92AW. Therefore, the ratio of the surface area of ​​the first semiconductor material layer 92AW to the surface area of ​​the first semiconductor material layer 92AN is greater than the corresponding width ratio (e.g., WW:WN). It should be noted that Figure 11B shows a single first semiconductor material layer 92AN with narrow epitaxial 92N (e.g., Figure 11E), and provides a dashed outline for the first semiconductor material layer 92AW with wide epitaxial 92W (e.g., Figure 11F).

[0055] Furthermore, the growth rates of the second semiconductor material layer 92B and the third semiconductor material layer 92C (referred to as the second semiconductor material layer 92B in this discussion for simplicity) may also be affected by the relevant geometry and the size of the corresponding first semiconductor material layer 92A. For example, the growth rate of the second semiconductor material layer 92BW with a wide epitaxial layer 92W can be greater than the growth rate of the second semiconductor material layer 92BN with a narrow epitaxial layer 92N. Specifically, this is caused by the disproportionately large surface area of ​​the first semiconductor material layer 92AW. In addition, the merging growth pattern of the first semiconductor material layer 92AW makes the exposed surface area more easily contacted by the deposition precursor, thus allowing it to continue growing, compared to the initial growth of the first semiconductor material layer 92AW. Therefore, after a sufficient period of time, the bump height of the wide epitaxial layer 92W may equal and eventually exceed the bump height of the narrow epitaxial layer 92N, as shown in the figure. For a further discussion of the growth processes of the narrow epitaxial layer 92N and the wide epitaxial layer 92W, please see Figures 19A to 24B and the description below.

[0056] In Figures 12A and 12B, a first interlayer dielectric (ILD) 96 is deposited over the structures shown in Figures 11A and 11B. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed through any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the gate spacer 81. The CESL 94 can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or similar materials, having an etch rate different from that of the overlying first ILD 96.

[0057] After depositing the first ILD 96, a planarization process (e.g., CMP) can be performed to make the top surface of the first ILD 96 level with the top surface of the dummy gate 76 (as shown) or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the gate spacer 81, and the first ILD 96 are level during the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD 96 level with the top surfaces of the mask 78 and the gate spacer 81.

[0058] In Figures 13A and 13B, the dummy gate 76 and mask 78 (if present) are removed through one or more etching steps to form a second recess 98. A portion of the dummy gate dielectric 70 in the second recess 98 may also be removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 70 are removed through an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the gate spacer 81. Each second recess 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nano-FETs. The portion of the nanostructure 55 serving as the channel region is located between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 70 may serve as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric 70 may then be removed after the dummy gate 76 is removed.

[0059] In Figures 14A and 14B, sacrificial material 72 is removed, extending the second groove 98. Removal of sacrificial material 72 may include performing an isotropic etching process using an etchant selective for the material of sacrificial material 72, such as wet etching or a similar process, while the second nanostructure 54 remains relatively unetched compared to the sacrificial material 72. Sacrificial material 72 may be completely removed, or residues of sacrificial material 72 may remain on the sidewalls of the inner spacers in the second groove 98 (e.g., see Figure 15C).

[0060] In some embodiments, the STI region 68 can be etched while removing the sacrificial material 72, but the total loss in the STI region 68 can be reduced by controlling the etching parameters (e.g., time) while removing the sacrificial material 72. In other embodiments, the STI region 68 may have a hard mask (not shown separately) at its top surface to protect the underlying STI region 68 from etching during patterning and removal of the sacrificial material 72. In this embodiment, the hard mask may include, for example, a nitride.

[0061] In Figures 15A-15C, a gate dielectric layer 100 and a gate electrode 102 are formed to form an alternative gate. The gate dielectric layer 100 is conformally disposed in the second recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be disposed on the top surface of the first ILD 96, CESL 94, gate spacer 81, and STI region 68.

[0062] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, similar materials, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0063] Gate electrodes 102 are deposited above gate dielectric layer 100 and fill the remaining portion of second groove 98. Gate electrodes 102 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although figures 15A-15C illustrate a single-layer gate electrode 102, gate electrode 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of the layers constituting gate electrode 102 may be deposited between adjacent second nanostructures 54 and in the n-type region 50N between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0064] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0065] After filling the second recess 98, a planarization process (e.g., CMP) can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, which are located above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus forms the alternative gate structure of the resulting nano-FETs. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0066] Figure 15C shows a detailed view of the various components in Figure 15B, including the epitaxial source / drain region 92, the gate dielectric layer 100, the gate electrode 102, the second nanostructure 54, and the inner spacer 90. In some embodiments, as shown in Figure 15C, residues of the sacrificial material 72 may remain on the inner spacer 90, for example, between the inner spacer 90 and the gate dielectric layer 100 / gate electrode 102. For example, the sacrificial material 72 may not be completely removed, and the gate dielectric layer 100 may be formed on the remaining sacrificial material 72. Since the sacrificial material 72 is an insulating material (e.g., silicon oxide), the remaining residue may not significantly affect the electrical performance of the resulting component.

[0067] In Figures 16A-16C, the gate structure (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed, forming a groove between the gate structure and the opposite portion of the gate spacer 81. A gate mask 104 containing one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the groove, followed by a planarization process to remove excess dielectric material extending above the first ILD 96. The subsequently formed gate contact (e.g., gate contact 114, discussed below with reference to Figures 18A-18C) penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0068] As further shown in Figures 16A-16C, the second ILD 106 is deposited above the first ILD 96 and above the gate shield 104. In some embodiments, the second ILD 106 is a flowable thin film formed using FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, or similar methods.

[0069] In Figures 17A-17C, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a third groove 108 on the exposed surface of the epitaxial source / drain region 92 and / or gate structure. The third groove 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, or similar processes). In some embodiments, the third groove 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the gate mask 104 can be etched using a second etching process; and then the CESL 94 can be etched using a third etching process. A mask (e.g., photoresist) can be formed and patterned over the second ILD 106 to shield portions of the second ILD 106 from the effects of the first and second etching processes. In some embodiments, due to the possibility of over-etching during the etching process, the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be at the same level (e.g., on the same horizontal plane) or below the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate). Although Figure 17B shows the third groove 108 exposing the epitaxial source / drain region 92 and gate structure in the same cross-section, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross-sections, thereby reducing the risk of short circuits in subsequently formed contacts.

[0070] After the third groove 108 is formed, a silicide region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) that can react with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region. For example, metals such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof can be used. The metal can be deposited above the exposed portion of the epitaxial source / drain region 92. The silicide region 110 can then be formed using a thermal annealing process. Unreacted portions of the deposited metal are then removed by, for example, an etching process. Although the silicate region 110 is referred to as a silicate region, it can also be a germanide region, or a silica-germanide region (e.g., a region containing both silicate and germanide). In one embodiment, the silicate region 110 comprises TiSi with a thickness ranging from about 2 nm to about 10 nm.

[0071] Next, in Figures 18A-18E, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 may each include a barrier layer and a conductive material, and be electrically connected to an underlying conductive feature (e.g., the gate electrode 102 and / or the silicate region 110 in the illustrated embodiment). Contact 114 is electrically connected to the gate electrode 102 and may be referred to as a gate contact, while contact 112 is electrically connected to the silicate region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or similar materials. A planarization process (e.g., CMP) can be performed to remove excess material from the surface of the second ILD 106.

[0072] Figures 18D and 18E show the contact 112 formed above the exemplary epitaxial source / drain region 92 of Figures 11E and 11F, respectively. Each top view depicts a side cross-sectional view similar to Figure 18C, along with certain components of the foreground or background (e.g., dashed outlines) for reference. Each bottom view depicts a plan view of the reference section D-D' marked in the corresponding top view.

[0073] As shown in the figure, the above embodiment ensures that the wide epitaxial wafer 92W is grown to a sufficient bump height to allow the contact 112W to make adequate contact. For example, conversely, if the bump height of the wide epitaxial wafer 92W is lower than that of the narrow epitaxial wafer 92N (e.g., the bump height difference Δh is negative), the contact 112W may have a relatively small contact area with the relatively large wide epitaxial wafer 92W. Such a small contact area may reduce the efficiency and reliability of this part of the integrated circuit. Therefore, a positive bump height difference Δh ensures that any depth between the contact 112N and the narrow epitaxial wafer 92N is sufficient for the contact 112W and the wide epitaxial wafer 92W. In some embodiments, the contact area between the contact 112W and the wide epitaxial wafer 92W may be greater than or equal to the contact area between the contact 112N and the narrow epitaxial wafer 92N.

[0074] Figures 19A-24B illustrate, according to some embodiments, the growth processes of narrow epitaxial 92N and wide epitaxial 92W (see Figures 11E and 11F) of various epitaxial source / drain regions 92. Figures 19A-21B include planar cross-sections showing the formation of various first semiconductor material layers 92A. Figures 22A-24B include side views and planar cross-sections showing the formation of corresponding second semiconductor material layers 92B and third semiconductor material layers 92C (referred to as second semiconductor material layer 92B for brevity in this discussion).

[0075] In Figures 19A and 19B, during the initial stage, the initial growth rate of the first semiconductor material layer 92AN of the narrow epitaxial layer 92N may be greater than that of the first semiconductor material layer 92AW of the wide epitaxial layer 92W, for reasons similar to those discussed earlier. Specifically, the deposition precursor gas can reach and circulate between fins 66N more easily than that of fins 66W. This difference leads to relative dilution of the deposition precursor at fins 66W and nanostructure 54W, resulting in a slower growth rate. Therefore, after the initial stage, the gap GW between the first semiconductor material layers 92AW is greater than the gap GN between the first semiconductor material layers 92AN.

[0076] In Figures 20A and 20B, during the intermediate stage, the intermediate growth rate of the first semiconductor material layer 92AW (wide epitaxial 92W) can become the same as or greater than the intermediate growth rate of the first semiconductor material layer 92AN (narrow epitaxial 92N). Specifically, the larger exposed surface area of ​​the first semiconductor material layer 92AW can facilitate an increased growth rate, thereby balancing the lower circulation of the deposition precursor gas between the fins 66W. This may cause the growth of the first semiconductor material layer 92AW to begin catching up with (and potentially exceeding) the growth of the first semiconductor material layer 92AN. Therefore, after the intermediate stage, the gap GN may be substantially equal to or greater than the gap GW.

[0077] In Figures 21A and 21B, in the final stage, the final growth rate of the wide epitaxial 92W first semiconductor material layer 92AW may be greater than that of the narrow epitaxial 92N first semiconductor material layer 92AN, for reasons similar to those discussed earlier. Specifically, the growth rate of the first semiconductor material layer 92AN slows down due to the change from a trapezoidal growth pattern to a triangular growth pattern, while the growth rate of the first semiconductor material layer 92AW can continue to increase or remain relatively constant. This difference causes the opposite trapezoidal growth patterns of the final first semiconductor material layers 92AW to meet and merge. Therefore, after the final stage, the gap GN between the opposing first semiconductor material layers 92AN still exists (albeit smaller than before), and is thus larger than the gap GW that no longer exists. In some embodiments, the gap GN can be as high as 10 nm.

[0078] In Figures 22A and 22B, in the initial stage, for reasons similar to those discussed earlier, the initial growth rate of the narrow epitaxial 92N second semiconductor material layer 92BN may be greater than the initial growth rate of the wide epitaxial 92W second semiconductor material layer 92BW. Specifically, the narrow epitaxial 92N can grow faster than the larger size of the wide epitaxial 92W. Therefore, after the initial stage, the protrusion height of the second semiconductor material layer 92BN is greater than the protrusion height of the second semiconductor material layer 92BW, making the protrusion height difference Δh negative.

[0079] In Figures 23A and 23B, during the intermediate stage, the intermediate growth rate of the second semiconductor material layer 92BW of the wide epitaxial layer 92W can become the same as or greater than the intermediate growth rate of the second semiconductor material layer 92BN of the narrow epitaxial layer 92N. Specifically, the larger exposed surface area of ​​the second semiconductor material layer 92BW can promote an increase in growth rate, thereby reducing the difference between the larger size of the wide epitaxial layer 92W and the smaller size of the narrow epitaxial layer 92N. Furthermore, this effect may be amplified as the upper portion of the narrow epitaxial layer 92N becomes narrower and approaches the triangle at a faster rate than the upper portion of the wide epitaxial layer 92W. Therefore, the protrusion height of the second semiconductor material layer 92BW can be close to, substantially the same as, or greater than the protrusion height of the second semiconductor material layer 92BN, such that the protrusion height difference Δh is substantially zero.

[0080] In Figures 24A and 24B, in the final stage, for reasons similar to those discussed earlier, the final growth rate of the second semiconductor material layer 92BW of the wide epitaxial 92W may be greater than that of the second semiconductor material layer 92BN of the narrow epitaxial 92N. Specifically, as the upper portion approaches the triangle at a disproportionately faster rate than the upper portion of the wide epitaxial 92W, the growth rate of the second semiconductor material layer 92BN continues to slow down. Therefore, the protrusion height of the second semiconductor material layer 92BW can be substantially equal to or greater than the protrusion height of the second semiconductor material layer 92BN, such that the protrusion height difference Δh is substantially zero or positive.

[0081] Referring to Figures 19A-24B, the formation of the epitaxial source / drain regions 92 can be controlled in a way that results in a height difference Δh that is essentially zero (or closer to zero). For example, the first semiconductor material layer 92A can be completed in an early stage before Figures 21A and 21B. Specifically, the formation of the first semiconductor material layer 92A can be stopped at Figures 20A and 20B, or even earlier at Figures 19A and 19B. In this way, the gap GW between opposing first semiconductor material layers 92AW remains unchanged and can be greater than or substantially equal to the gap GN between opposing first semiconductor material layers 92AN. Then, the formation of the second semiconductor material layer 92B will continue through the merging of the epitaxial source / drain regions 92, and semiconductor material layers 92B and 92C will complete the growth of the epitaxial source / drain regions. By forming a smaller first semiconductor material layer 92AW, the second semiconductor material layer 92BW has a smaller initial surface area for growth, and its growth rate is also slower than in other cases. The growth rate of the second semiconductor material layer 92BW will increase and is generally greater than the growth rate of the second semiconductor material layer 92BN. In this embodiment, compared to embodiments that include all growth stages of the first semiconductor material layer 92A, both the epitaxial source / drain region 92N and the epitaxial source / drain region 92W will include a larger volume of the second semiconductor material layer 92B (e.g., as shown in the figures and see the embodiments described above and in all of Figures 19A-21B). In any set of embodiments, the contact resistance between the epitaxial source / drain region and the subsequently formed contact 112 will be improved.

[0082] Several advantages are achieved. The formation of some nano-FETs includes the selection of lattice orientation (e.g., (110) wafer orientation), the width of fin 66, the pitch of dummy gate 76 (e.g., including alternative gate electrode 102), and the stopping points at various stages of the fabrication process of epitaxial source / drain region 92. The embodiments disclosed herein provide better control over the resulting epitaxial source / drain region 92. The individual fins 66 can have various widths (e.g., WN and WW), which can lead to loading effects during the formation of the epitaxial source / drain region 92. These loading effects can be avoided by utilizing the embodiments disclosed herein. Specifically, narrow epitaxial 92N in narrow fin 66N can be formed simultaneously with wide epitaxial 92W in wide fin 66W to achieve the desired features. For example, the embodiments disclosed herein ensure that the wide epitaxial 92W can be formed to a sufficient bump height (e.g., relative to the bump height of the narrow epitaxial 92N) so that the subsequently formed contact 112 has sufficient contact area with the underlying epitaxial source / drain region 92N and epitaxial source / drain region 92W. Therefore, the corresponding nano-FETs (and the entire integrated circuit) can be manufactured at higher yields with better performance and reliability.

[0083] In one embodiment, a method includes: forming a stack of semiconductor layers over a substrate; etching the stack to form a first fin and a second fin over the substrate, the first fin having a first width and the second fin having a second width greater than the first width; etching a first groove in the first fin and etching a second groove in the second fin; performing a deposition process to grow a first epitaxial region in the first groove and a second epitaxial region in the second groove; wherein at a first point in the deposition process, a first protrusion height of the first epitaxial region is higher than a second protrusion height of the second epitaxial region; and wherein at a second point in the deposition process, a third protrusion height of the first epitaxial region is lower than a fourth protrusion height of the second epitaxial region, the second point being after the first point. In another embodiment, the substrate comprises a semiconductor substrate in a (110) lattice orientation. In another embodiment, the first fin is parallel to the second fin. In another embodiment, the first fin and the second fin are perpendicular but do not intersect. In another embodiment, a first growth rate of the first epitaxial region reaching the first point is greater than a second growth rate of the second epitaxial region reaching the first point. In another embodiment, the third growth rate of the first epitaxial region from the first point to the second point is less than the fourth growth rate of the second epitaxial region from the first point to the second point. In another embodiment, prior to performing the deposition process, the process further includes: forming a first gate structure across a first fin and a second gate structure across a second fin; removing a first semiconductor layer from the stack to form a void between the second semiconductor layers remaining in the stack; and forming a sacrificial material in the void. In another embodiment, after performing the deposition process, the process further includes: replacing the first gate structure with a third gate structure; and replacing the second gate structure with a fourth gate structure.

[0084] In one embodiment, a method includes: forming a stack of alternating first and second semiconductor layers over a substrate; etching the stack to form a first fin and a second fin, the first fin having a first width and the second fin having a second width greater than the first width; forming a first gate across the first fin and a second gate across the second fin; etching a first groove between the first gates and a second groove between the second gates; and performing epitaxial growth to form a first epitaxial region in the first groove and a second epitaxial region in the second groove, the epitaxial growth comprising: a first step comprising forming a first relative epitaxial layer in the first groove and forming a second relative epitaxial layer in the second groove, wherein after the first step: a first gap separates the first relative epitaxial layer; and a second gap separates the second relative epitaxial layer; and a second step comprising expanding the first relative epitaxial layer and the second relative epitaxial layer, wherein after the second step, a third gap separates the first relative epitaxial layer; and the second relative epitaxial layer and the second relative epitaxial layer merge to form a second merged epitaxial layer. In another embodiment, performing epitaxial growth further includes a third step, the third step including expanding the first opposing epitaxial layer and the second merged epitaxial layer, wherein after the third step, the first opposing epitaxial layer and the second opposing epitaxial layer are merged to form a first merged epitaxial layer. In another embodiment, after the third step, the first height of the first merged epitaxial layer is greater than the second height of the second merged epitaxial layer. In another embodiment, performing epitaxial growth further includes a fourth step, the fourth step including expanding the first merged epitaxial layer and the second merged epitaxial layer, wherein after the fourth step, the third height of the first merged epitaxial layer is less than the fourth height of the second merged epitaxial layer. In another embodiment, the second width is at least twice the first width. In another embodiment, the first pitch of the first gate and the second pitch of the second gate are substantially the same. In another embodiment, the substrate is a portion of the wafer comprising a semiconductor substrate, and wherein the semiconductor substrate has a (110) lattice orientation.

[0085] In one embodiment, a semiconductor element includes: a semiconductor substrate; a first nanometer field-effect transistor including: a first gate structure disposed across a first fin, the first fin having a first width; and a first source / drain region embedded in the first fin adjacent to the first gate structure, the first source / drain region having a first protrusion height from the semiconductor substrate; and a second nanometer field-effect transistor including: a second gate structure disposed across a second fin, the second fin having a second width greater than the first width; and a second source / drain region embedded in the second fin adjacent to the second gate structure, the second source / drain region having a second protrusion height from the semiconductor substrate, the second protrusion height being greater than the first protrusion height. In another embodiment, the first nanometer field-effect transistor and the second nanometer field-effect transistor are disposed above the semiconductor substrate in a (110) lattice orientation. In another embodiment, the semiconductor element further includes: an interlayer dielectric disposed above the first nanometer field-effect transistor and the second nanometer field-effect transistor; a first contact plug extending through the interlayer dielectric to a first source / drain region; and a second contact plug extending through the interlayer dielectric to a second source / drain region. In another embodiment, the first contact plug has a first total contact area with the first source / drain region, wherein the second contact plug has a second total contact area with the second source / drain region, and wherein the second total contact area is greater than or equal to the first total contact area. In another embodiment, the second total contact area is substantially the same as the first total contact area.

[0086] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0087] 001, 110: Lattice orientation 20: Separator line 50:Substrate 50N: n-type region 50P:p-type area 51, 51A, 51B, 51C: Semiconductor layers 52, 52A, 52B, 52C: Nanostructures 53, 53A, 53B, 53C: Semiconductor layers 54, 54A, 54B, 54C, 54N, 54W: Nanostructures 55: Nanostructure 58: Trench 64: Stacking 66, 66N, 66W: Fins 68: Shallow Trench Isolation Area (STI Area) (STI Structure) 70: Dummy gate dielectric 71: Sacrificial Material Layer 72: Sacrificial Materials 76, 76N, 76W: Dummy gate 78: Mask 81: Gate spacer 83: Fin spacers 86, 86W: First groove 90: Internal spacer 92: Source / Drain Region 92A, 92AN, 92AW: Semiconductor material layers 92B, 92BN, 92BW: Semiconductor material layers 92C: Semiconductor material layer 92N: Epitaxial source / drain region (narrow epitaxial) 92W: Epitaxial source / drain region (wide epitaxial layer) 94: Etching Stop Layer (CESL) 96: Interlayer Dielectric (ILD) 98: Second groove 100: Gate dielectric layer 102: Gate electrode 104: Gate shield 106: Second ILD 108: Third Groove 110: Silicone region 112, 112N, 112W: Contact elements (contact plugs) 114: Contact element (contact plug) A-A': Cross-section B-B': Cross section C-C': Cross section D-D': Cross section DN, DW: Distance GN, GW: gaps hN, hW: Height L0: Initial layer L1: First layer L2: Second layer (second semiconductor material layer) L3: Third layer (third semiconductor material layer) W, WN, WW: Width x, y, z: Direction Δh: height difference

[0088] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: forming a stack of a plurality of semiconductor layers over a substrate; etching the stack to form a first fin and a second fin over the substrate, the first fin having a first width and the second fin having a second width, the second width being greater than the first width; etching a first groove in the first fin and etching a second groove in the second fin; performing a deposition process to grow a first epitaxial region in the first groove and a second epitaxial region in the second groove; wherein at a first point in the deposition process, a first protrusion height of the first epitaxial region is higher than a second protrusion height of the second epitaxial region; and wherein at a second point in the deposition process, a third protrusion height of the first epitaxial region is lower than a fourth protrusion height of the second epitaxial region, the second point being after the first point.

2. The method of claim 1, wherein the substrate comprises a semiconductor substrate in a (110) lattice orientation.

3. The method as described in claim 2, wherein the first fin is parallel to the second fin.

4. The method as described in claim 2, wherein the first fin is perpendicular to the second fin but does not intersect it.

5. A method of forming a semiconductor device, comprising: forming a stack of alternating plurality of first semiconductor layers and plurality of second semiconductor layers over a substrate; etching the stack to form a first fin and a second fin, the first fin having a first width and the second fin having a second width greater than the first width; forming a plurality of first gates across the first fin and a plurality of second gates across the second fin; etching a first groove between the first gates and a second groove between the second gates; and performing an epitaxial growth to form a first epitaxial region in the first groove and a second epitaxial region in the second groove, the epitaxial growth comprising: a first step comprising forming a plurality of first opposing epitaxial crystals in the first groove and a plurality of second opposing epitaxial crystals in the second groove, wherein after the first step: A first gap separates the first-pair epitaxial crystals; and a second gap separates the second-pair epitaxial crystals; and a second step includes expanding the first-pair epitaxial crystals and the second-pair epitaxial crystals, wherein after the second step: a third gap separates the first-pair epitaxial crystals; and the second-pair epitaxial crystals merge to form a second merged epitaxial crystal.

6. The method of claim 5, wherein performing the epitaxial growth further comprises a third step, the third step comprising expanding the first relative epitaxial crystals and the second merged epitaxial crystal, wherein after the third step, the first relative epitaxial crystals are merged to form a first merged epitaxial crystal.

7. The method as described in claim 6, wherein after the third step, a first height of the first merged epitaxial layer is greater than a second height of the second merged epitaxial layer.

8. The method of claim 7, wherein performing the epitaxial growth further comprises a fourth step, the fourth step comprising expanding the first merged epitaxial layer and the second merged epitaxial layer, wherein after the fourth step, a third height of the first merged epitaxial layer is smaller than a fourth height of the second merged epitaxial layer.

9. A semiconductor device comprising: a semiconductor substrate; a first nanometer field-effect transistor comprising: a first gate structure disposed across a first fin, the first fin having a first width; and a first source / drain region embedded in the first fin adjacent to the first gate structure, the first source / drain region having a first protrusion height from the semiconductor substrate; and a second nanometer field-effect transistor comprising: a second gate structure disposed across a second fin, the second fin having a second width greater than the first width; and a second source / drain region embedded in the second fin adjacent to the second gate structure, the second source / drain region having a second protrusion height from the semiconductor substrate, the second protrusion height being greater than the first protrusion height.

10. The semiconductor element of claim 9, wherein the first nanometer field-effect transistor and the second nanometer field-effect transistor are disposed above the semiconductor substrate in a (110) lattice orientation.

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