Method of forming semiconductor structure and interconnect structure

Abstract

A method of forming a semiconductor structure includes: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer over the conductive topology; forming a first opening in the second dielectric layer to expose a top surface of the conductive topology; selectively depositing an inhibitor film on the top surface of the conductive topology; depositing a dielectric barrier layer on the sidewall of the first opening; removing the inhibitor film to expose the top surface of the conductive topology; depositing a conductive material on the dielectric barrier layer and filling the first opening; and performing a planarization process to expose the dielectric barrier layer.

Description

[Technical Field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 676,408, filed July 28, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] This disclosure relates to methods for forming semiconductor structures and interconnect structures. [Previous Technology]

[0003] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest component (or circuit) that can be built using a manufacturing process) has decreased. This miniaturization typically benefits production efficiency and reduces associated costs.

[0004] Such miniaturization has also increased the complexity of IC manufacturing processes, and similar advancements in IC processes and manufacturing are required to achieve these progresses. For example, as multilayer interconnect (MLI) topologies become denser with the ever-shrinking size of IC topologies, the interconnects in MLI topologies exhibit increased contact resistance, posing challenges to performance, yield, and cost. It has been observed that the higher contact resistance exhibited by interconnects in advanced IC technology nodes can significantly delay (and in some cases prevent) the efficient routing of signals to and from IC devices (such as transistors), offsetting any performance improvements of such IC devices in advanced technology nodes. Accordingly, while existing interconnects are generally sufficient for their intended uses, they are not entirely satisfactory in all respects. [Summary of the Invention]

[0005] According to some embodiments of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer over the conductive topology; forming a first opening in the second dielectric layer to expose a top surface of the conductive topology; selectively depositing an inhibitor film on the top surface of the conductive topology; depositing a dielectric barrier layer on the sidewall of the first opening; removing the inhibitor film to expose the top surface of the conductive topology; depositing a conductive material on the dielectric barrier layer and filling the first opening; and performing a planarization process to expose the dielectric barrier layer.

[0006] According to some embodiments of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer above the first dielectric layer; forming a contact via through the second dielectric layer and onto a top surface of the conductive topology, wherein the contact via is separated from the second dielectric layer by a dielectric barrier layer; forming a third dielectric layer above the second dielectric layer; and forming a metal line in the third dielectric layer and electrically coupled to the contact via, wherein the metal line includes a metal fill layer separated from the third dielectric layer by a conductive barrier layer.

[0007] According to some embodiments of the present disclosure, an interconnect structure is provided, comprising: a conductive topology disposed in a first dielectric layer; a second dielectric layer above the first dielectric layer; a contact via extending through the second dielectric layer and resting on a top surface of the conductive topology; a dielectric barrier layer separating the contact via from the second dielectric layer; a third dielectric layer above the second dielectric layer; and a metal line disposed in the third dielectric layer and resting on a top surface of the contact via, the metal line including a barrier layer that separates a metal fill layer from the third dielectric layer without contact.

Implementation Method

[0011] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition is for simplification and clarity and does not in itself specify a relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of explanation, this document may use spatial relative terms such as “under,” “below,” “below,” “above,” “on,” and similar to describe the relationship of one element or feature relative to another element(s) as illustrated in the figures. Besides the orientations shown in the figures, these spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, when a number or range of numbers is described using “about,” “approximately,” and similar terms, unless otherwise specified, the term is intended to cover numbers within + / - 10% of the stated number. For example, the term “about 5 nm” covers a size range of 4.5 nm to 5.5 nm.

[0013] IC manufacturing process flows are generally divided into three categories: front-end process (FEOL), mid-end process (MEOL), and back-end process (BEOL). FEOL typically covers processes related to manufacturing IC devices such as transistors. For example, FEOL processes may include forming isolation topologies, gate structures, and source and drain topologies (commonly referred to as source / drain topologies). MEOL typically covers processes related to manufacturing conductive topologies (or conductive regions) contacts for IC devices, such as contacts for gate structures and / or source / drain topologies. BEOL typically covers processes related to manufacturing multilayer interconnect (MLI) topologies that interconnect the IC topologies (referred to as FEOL and MEOL topologies or structures, respectively) manufactured in FEOL and MEOL, thereby enabling the operation of the IC device.

[0014] As IC technology moves towards smaller technology nodes, MEOL and BEOL processes face significant challenges. For example, advanced IC nodes require denser multilayer interconnect (MLI) topologies, thus necessitating a significant reduction in the critical dimensions of interconnect components, such as the width and height of vias and conductive traces. However, these reductions in critical dimensions have led to a significant increase in interconnect resistance, which can degrade IC device performance, for example, due to increased resistance-capacitance (RC) delay. Accordingly, further advancements in processing and manufacturing are needed as ICs continue to shrink. For instance, conventional dummy-mount methods face numerous challenges when shrinking via sizes. As vias become smaller, the proportion of high-resistivity liner material within the via increases, resulting in higher overall resistance that can degrade IC performance. Additionally, conventional dummy-mount processes encounter difficulties in gap filling at smaller via sizes, leading to defects and reduced yield. Furthermore, conventional dummy-mount methods cannot adjust via sizes, potentially causing reliability issues in the connection between the via and the underlying traces. Therefore, while existing mosaicking procedures are generally sufficient for their intended use, they are not entirely satisfactory in all respects.

[0015] This disclosure discloses embodiments of interconnect structures that provide low-resistance vias and metal traces thereon. Interconnect structures typically include a barrier layer. The barrier layer functions to prevent metallic elements (such as copper) in the interconnect structure from diffusing into the dielectric layer surrounding the interconnect structure; it is therefore also called a diffusion barrier layer. The barrier layer typically has a high resistivity, which increases the contact resistance between the interconnect structure and other underlying conductive features (e.g., metal traces in the underlying metal layer hierarchy). In some embodiments of this disclosure, the low-resistance interconnect structure includes a dielectric barrier layer selectively formed on the sidewall of a via but not beneath the bottom surface of the via. By having a barrier layer that does not directly contact the underlying conductive features, contact resistance and therefore the overall resistance of the interconnect structure can be reduced.

[0016] FIG1 illustrates a schematic cross-sectional view of a plurality of layers involved in the semiconductor device 100. It should be noted that FIG1 is schematically illustrated to show various levels of interconnect structures and circuit device regions (e.g., transistors) and may not reflect an actual cross-sectional view of the semiconductor device 100. The interconnect structure includes a contact level, an OD (wherein the term "OD" stands for "active region") level, a via level via_0 level, via_1 level, via_2 level and via_3 level, and metal layer levels M1 level, M2 level, M3 level, M4 level...Mtop level. Each of the illustrated levels includes one or more dielectric layers and conductive features formed therein. Conductive features in the same level may have substantially flush top surfaces and substantially flush bottom surfaces, and may be formed simultaneously. The contact layer may include a gate contact (also called a contact plug) for connecting the gate electrode of a transistor to an overlay layer (such as a via-0 layer), and a source / drain contact (denoted as a "contact") for connecting the source / drain region of the transistor to the overlay layer. The thicknesses of the metal lines in the metal layer layers M1, M2, M3, M4...Mtop are denoted as T1, T2, T3, T4...Ttop, respectively. It is also noted that a metal line in a higher layer may have a greater thickness than a metal line in a lower layer (i.e., T1 < T2 < T3 < T4 < ... < Ttop). Furthermore, metal lines in higher layers may have a larger spacing (e.g., center-to-center or edge-to-edge distance between adjacent metal lines) compared to metal lines in a lower layer.

[0017] Figures 2 to 24 illustrate cross-sectional views of intermediate stages in forming contact structures in a semiconductor device 100 according to some embodiments of the present disclosure. In particular, for simplicity, Figures 2 to 24 illustrate cross-sectional views of intermediate stages in forming interconnect structures of the semiconductor device 100 between two consecutive metal layer levels and corresponding via levels therebetween (e.g., an Mx layer, a via_x layer, and an Mx+1 layer, where x represents an integer, or a contact layer, a via_0 layer, and an M1 layer) according to some embodiments.

[0018] Figure 2 illustrates a cross-sectional view of a semiconductor device 100. According to some embodiments of this disclosure, the semiconductor device 100 is a device wafer that includes active devices such as transistors and / or diodes and possible passive devices such as capacitors, inductors, resistors, or the like. According to alternative embodiments of this disclosure, the semiconductor device 100 is a median wafer that may or may not include active and / or passive devices. According to yet another alternative embodiment of this disclosure, the semiconductor device 100 is a package substrate strip that may include a package substrate with a core or a coreless package substrate. In the following discussion, a device wafer is used as an example of the semiconductor device 100. The teachings of this disclosure can also be applied to median wafers, package substrates, packages, etc.

[0019] According to some embodiments of this disclosure, the semiconductor device 100 includes a semiconductor substrate 102 and a top surface formed on one of the top surfaces of the semiconductor substrate 102. The semiconductor substrate 102 may comprise crystalline silicon, crystalline germanium, silicon-germanium, III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 102 may also be a silicon substrate or a silicon-coated insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown in FIG. 2, but shown in FIG. 1) may be formed in the semiconductor substrate 102 to isolate active regions in the semiconductor substrate 102. Although not shown, vias may be formed extending into the semiconductor substrate 102, wherein these vias are used to electrically couple the top surface on opposite sides of the semiconductor device 100.

[0020] According to some embodiments of this disclosure, circuit device 104 is formed on the top surface of semiconductor substrate 102. Examples of circuit device 104 include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, or the like. Details of circuit device 104 are not illustrated herein.

[0021] Figure 2 further illustrates a dielectric layer 106. The dielectric layer 106 may be an inter-layer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer. According to some embodiments of this disclosure, the dielectric layer 106 is an ILD layer in which a contact plug is formed. The corresponding dielectric layer 106 may be formed from: phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silica oxide (formed using tetraethyl orthosilicate (TEOS)) or the like. The dielectric layer 106 may be formed using spin coating, chemical vapor deposition (CVD), flow-through chemical vapor deposition (F-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), low-pressure chemical vapor deposition (LP-CVD) or the like. According to some embodiments of this disclosure, dielectric layer 106 is an IMD layer in which metal lines and / or vias are formed. The corresponding dielectric layer 106 may be formed from a carbon-containing low-k dielectric material (e.g., organosilates (SiOCH)), hydrosilsesquioxanes (HSQ), methylsilsesquioxanes (MSQ), or the like. According to some embodiments of this disclosure, the formation of dielectric layer 106 includes depositing a dielectric material containing a porogen, followed by a curing process to remove the porogen, thus leaving a porous dielectric layer 106.

[0022] One or more conductive features 108 are formed in the dielectric layer 106. The conductive feature 108 may be a metal line, a conductive via, a contact plug, or the like. According to some embodiments, the conductive feature 108 includes a barrier layer 110, a liner 112, a metal filler layer 114 above the liner 112, and a metal capping layer 116 above the metal filler layer 114. The barrier layer 110 may be formed of a conductive material, also referred to as a conductive barrier layer, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials that can block the diffusion of metal elements, and may be deposited using atomic layer deposition (ALD), CVD, or physical vapor deposition (PVD), and may be formed to have a thickness between about 0.5 nm and about 5 nm.

[0023] Liner 112 is deposited on barrier layer 110. In some embodiments, liner 112 can be deposited using ALD, CVD, or PVD, and can be formed to have a thickness between about 0.5 nm and 3 nm. Liner 112 can be formed of a suitable metal or metal alloy, such as cobalt (Co) or an alloy of cobalt and ruthenium (Ru). In one example, liner 112 is made of Co. Liner 112 serves to increase the adhesion between metal filler layer 114 and barrier layer 110. Liner 112 can also be referred to as an adhesion layer.

[0024] The metal filler layer 114 may be formed of copper (Cu), copper alloy, aluminum (Al), or the like. The barrier layer 110 functions to prevent material (such as copper) in the metal filler layer 114 from diffusing into the dielectric layer 106. In some embodiments, the metal filler layer 114 may be deposited using PVD, CVD, electroplating, electroless deposition, or other suitable deposition processes. After depositing the metal filler layer 114, a planarization process such as a chemical mechanical planarization (CMP) process or a mechanical polishing process may be performed to remove excess portions of the conductive material in the metal filler layer 114.

[0025] A metal capping layer 116 is deposited on the metal filler layer 114. In some embodiments, the CMP process performed before removing excess portions of the conductive material of the metal filler layer 114 also slightly recesses the top surfaces of the metal filler layer 114 and the liner 112. The metal capping layer 116 is deposited on the recessed top surfaces of the metal filler layer 114 and the liner 112. The barrier layer 110 may surround the metal capping layer 116 and separate the metal capping layer 116 from the dielectric layer 106 without contact. In some other embodiments, the CMP process recesses the metal filler layer 114 but not the liner 112, such that the liner 112 may surround the metal capping layer 116 and separate the metal capping layer 116 from the barrier layer 110 without contact. The metal capping layer 116 is formed of a conductive material, such as cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other suitable conductive materials. In some embodiments, the metal capping layer 116 and the liner 112 may have the same material composition. For example, both the metal capping layer 116 and the liner 112 may be formed of Co. In some other embodiments, the metal capping layer 116 and the liner 112 may include different material compositions. For example, the liner 112 may be formed of Co, and the metal capping layer 116 may be formed of Ru. In some embodiments, the metal capping layer 116 is thinner than the liner 112. Alternatively, the metal capping layer 116 may have the same thickness as the liner 112 or be thicker.

[0026] As also shown in FIG2, an etch stop layer 118 is formed over the dielectric layer 106 and the conductive topology 108. The etch stop layer 118 has a high etch selectivity relative to the overlying dielectric layer 120, and therefore the etch stop layer 118 can be used to stop the etching of the dielectric layer 120. In some embodiments, the etch stop layer 118 can be deposited using ALD, plasma-enhanced ALD (PE-ALD), CVD, PE-CVD, or other suitable deposition processes. The etch stop layer 118 can be a single-layer structure or a multi-layer structure. In the illustrated embodiment, the etch stop layer 118 is a two-layer structure, comprising a first sublayer 118a and a second sublayer 118b. The first sublayer 118a and the second sublayer 118b comprise different material compositions, such as oxides and nitrides. According to some embodiments of this disclosure, each sublayer of the etch stop layer 118 may be formed of a dielectric material, such as, but not limited to, oxides, carbides, nitrides, carbon oxides, nitrides, carbonitrides, or carbonitrides of combinations of aluminum, titanium, silicon, zirconium, yttrium, and hafnium. For example, each sublayer of the etch stop layer 118 may be formed from one of the following: aluminum oxide, aluminum carbide, aluminum nitride, aluminum oxycarbide, aluminum oxynitride, aluminum carbonitride, aluminum carbonitride, titanium oxide, titanium carbide, titanium nitride, titanium oxycarbide, titanium oxynitride, titanium carbonitride, titanium carbonitride, silicon oxide, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, zirconium oxide, zirconium carbide, zirconium nitride, zirconium oxycarbide, zirconium oxynitride, zirconium carbonitride, zirconium carbonitride, zirconium carbonitride, yttrium oxide, yttrium carbide, yttrium nitride, yttrium oxycarbide, yttrium oxynitride, yttrium carbonitride, yttrium carbonitride, hafnium oxide, hafnium carbide, hafnium nitride, hafnium oxycarbide, hafnium oxynitride, hafnium carbonitride, and hafnium carbonitride. In various embodiments, the etch stop layer 118 may have a thickness ranging from about 30 Å to about 100 Å. This range is not insignificant or arbitrary. If the thickness of the etch stop layer 118 is less than about 30 Å, the underlying conductive topology 108 (e.g., a metal line) may be oxidized. If the thickness of the etch stop layer 118 is greater than about 100 Å, the thickness of the dielectric layer disposed on the etch stop layer 118 may be reduced, which may adversely affect the performance of the interconnect structure.

[0027] A dielectric layer 120 is formed over the etch stop layer 118. According to some embodiments, the dielectric layer 120 is an IMD layer or an ILD layer. The corresponding dielectric layer 120 may be formed of PSG, BSG, BPSG, FSG, TEOS oxide, HSQ, MSQ, or the like. According to some embodiments of this disclosure, the dielectric layer 120 may be formed of a carbon-containing low-k dielectric material (e.g., an organosilicone (SiOCH)). The dielectric layer 120 may be formed using spin coating, CVD, F-CVD, PE-CVD, LP-CVD, or the like. In some embodiments, the formation of the dielectric layer 120 includes depositing a dielectric material containing a pore-forming agent, followed by a curing process to remove the pore-forming agent, and thus the remaining dielectric layer 120 is porous.

[0028] As shown in FIG. 3, a via opening 124 is formed by etching. The via opening 124 can be formed using a patterned hard mask 122 as an etching mask by, for example, photolithography. According to some embodiments of this disclosure, the etching of the dielectric layer 120 is performed using a process gas containing fluorine and carbon, wherein the fluorine is used for etching, and the carbon has the effect of protecting the sidewalls of the resulting opening. At an appropriate fluorine to carbon ratio, the via opening 124 can have a desired profile. For example, the process gas used for etching includes a fluorine and carbon-containing gas, such as C4F8, CH2F2 and / or CF4, and a carrier gas, such as N2. In one example of the etching process, the flow rate of C4F8 is in the range of about 0 sccm to about 50 sccm, the flow rate of CF4 is in the range of about 0 sccm to about 300 sccm (wherein at least one of C4F8 and CF4 has a non-zero flow rate), and the flow rate of N2 is in the range of about 0 sccm to about 200 sccm. According to an alternative embodiment, the process gas for etching includes CH2F2 and a carrier gas, such as N2. In one example of the etching process, the flow rate of CH2F2 may be in the range of about 10 sccm to about 200 sccm, and the flow rate of N2 is in the range of about 50 sccm to about 100 sccm. During the etching process, the semiconductor device 100 may be maintained at a temperature in the range of about 30 °C to about 60 °C. During the etching process, plasma may be generated from the etching gas. The radio frequency (RF) power supply used for etching can be less than about 700 watts, and the pressure of the process gas is in the range of about 15 mTorr to about 30 mTorr. The etch stop layer 118 is then etched using a suitable etchant, and the metal capping layer 116 is exposed at the bottom of the via opening 124. Extending the via opening 124 through the dielectric layer 120 and further through the etch stop layer 118 is performed in separate photolithography processes. For example, in a first photolithography process, the via opening 124 extends through the dielectric layer 120; in a second photolithography process, the via opening 124 extends through the etch stop layer 118. The patterned hard mask 122 can be consumed during the photolithography process or removed in a separate etching process.

[0029] Next, referring to FIG4, the inhibitor film 140 is selectively formed on the exposed top surface of the metal capping layer 116, but not on the sidewalls of the via opening 124. The inhibitor film 140 can be deposited by ALD, CVD, spin coating, or other suitable deposition processes. In some embodiments, the selective deposition of the inhibitor film 140 is achieved by a selective self-assembled monolayer (SAM) process. In some embodiments, the selective SAM process is a vapor phase or liquid phase process that forms one or more monolayers of molecular SAM material on the surface of the metal capping layer 116. The thickness of the inhibitor film 140 may be less than about 20 Å, which is less than the thickness of the etch stop layer 118 or even less than the thickness of the sublayer 118b of the etch stop layer 118. In some embodiments, the SAM material includes organosilanes or organophosphorus silanes, such as octadecyltrichlorosilane (ODTS), octadecyltrimethoxysilane (OTMS), and (3-aminopropyl)triethoxysilane (APTMS). In some embodiments, the inhibitor film 140 is formed of a thiol, 4,4'-oxydiphthalic anhydride (ODPA), or a polymer containing one of silicon, carbon, nitrogen, and oxygen. The inhibitor film 140 acts as an inhibitor for a subsequent via barrier deposition process. Due to the presence of the selective SAM material, via barrier deposition is suppressed on the surface of the conductive material. As a result, a minimal or zero via barrier layer is formed on the exposed top surface of the metal capping layer 116. It should be noted that because the selective deposition process also prohibits the growth of the inhibitor film 140 on the dielectric sidewalls of the etch stop layer 118, a gap 126 having a tip at the bottom and a push-out opening at the top still exists between the edge of the inhibitor film 140 and the sidewall of the etch stop layer 118, such that a bottom portion of the sidewall of the etch stop layer 118 remains exposed in the gap 126.

[0030] Next, referring to FIG. 5, a barrier layer 142 is deposited to form a liner for the via opening 124 and also covers the top surface of the dielectric layer 120. The barrier layer 142 serves to prevent subsequently deposited metal material (for forming a contact via) from diffusing into the dielectric layer 120. The barrier layer 142 can be deposited using ALD, PE-ALD, CVD, PE-CVD, or another suitable deposition process. An inhibitor film 140 prevents the barrier layer 142 from growing at the bottom of the via opening 124. Without the barrier layer 142 on the bottom surface of the via opening 124, a subsequently formed contact via can directly contact the metal capping layer 116, resulting in reduced contact resistance. Furthermore, since there is no conduction between the contact via and the metal capping layer 116 and therefore no conduction is required from the barrier layer 142, unlike the conductive barrier layer 110, the barrier layer 142 can be formed of a dielectric material. The barrier layer 142 may also be referred to as a dielectric barrier layer. Using a dielectric material as the barrier layer 142 can also promote the adhesion of subsequently deposited metal material to the sidewalls of the via opening 124. Therefore, a liner layer or an adhesive layer can be omitted, which increases the volume of the metal-filled layer of the via and further helps to reduce overall resistance. According to some embodiments of this disclosure, the barrier layer 142 may be formed of a dielectric material, such as, but not limited to, oxides, carbides, nitrides, carbon oxides, oxynitrides, carbonitrides, or carbonitrides of combinations of aluminum, silicon, zirconium, yttrium, and hafnium. For example, the barrier layer 142 may be formed from one of the following: aluminum oxide, aluminum carbide, aluminum nitride, aluminum oxycarbonate, aluminum oxynitride, aluminum carbonitride, aluminum carbonitride, silicon oxide, silicon carbide, silicon nitride, silicon oxycarbonate, silicon oxynitride, silicon carbonitride, silicon carbonitride, zirconium oxide, zirconium carbide, zirconium nitride, zirconium oxycarbonate, zirconium oxynitride, zirconium carbonitride, zirconium carbonitride, zirconium carbonitride, yttrium oxide, yttrium carbide, yttrium nitride, yttrium oxycarbonate, yttrium carbonitride, yttrium carbonitride, hafnium oxide, hafnium carbide, hafnium nitride, hafnium oxycarbonate, hafnium carbonitride, and hafnium carbonitride.

[0031] In some embodiments, the dielectric barrier layer 142 is deposited conformally. Hereinafter, the terms "conformal" or "conformally" are used to describe a material being deposited with a substantially uniform thickness on various exposed surfaces of the semiconductor device 100. In some other embodiments, the dielectric barrier layer 142 is non-conformal, such as having a greater thickness in its horizontal portions (e.g., on the top surface of dielectric layer 120) and a smaller thickness in its vertical portions (e.g., on the sidewalls of via opening 124). In various embodiments, the thinnest portion of the dielectric barrier layer 142 is the tip that fills the gap 126 between the edge of the inhibitor film 140 and the sidewall of the etch stop layer 118. Apart from the tip, the thickness of the dielectric barrier layer 142 above the sidewalls of via opening 124 ranges from about 5 Å to about 25 Å. This range is not insignificant or arbitrary. If the thickness of the dielectric barrier layer 142 is less than about 5 Å, the dielectric barrier layer 142 may have an undesirable formation and cannot effectively prevent the diffusion of metal ions and halide anions (derived from one of the precursor materials used to form the contact via) into the dielectric layer 120. If the thickness of the dielectric barrier layer 142 is greater than about 25 Å, it may adversely affect the size of the contact via or the contact via layer and result in an increased capacitance between the two metal lines disposed in the two dielectric layers.

[0032] Referring to FIG. 6, a post-deposition treatment 150 is performed to remove the inhibitor film 140. The post-deposition treatment 150 may be performed by a heat treatment, an ultraviolet (UV) treatment, or a plasma treatment. In some embodiments, the post-deposition treatment 150 is a plasma process that includes applying a mixture of a process gas of hydrogen and a carrier gas of argon. During the plasma treatment, the temperature of the semiconductor device 100 may be higher than about 200 °C, for example, in the range between about 200 °C and about 300 °C. The treatment duration may be in the range between about 30 seconds and about 60 seconds. The plasma treatment is also referred to as a plasma de-blocking treatment. Due to the post-deposition treatment 150, the inhibitor film 140 is removed. In the post-deposition treatment 150, the inhibitor film 140 is decomposed into gas, which is then removed. With the inhibitor film 140 removed, the top surface of the metal capping layer 116 is exposed in the via opening 124.

[0033] Referring to FIG. 7, a conductive material 152 is deposited to fill the via opening 124. The conductive material 152 may be copper. Alternatively, the conductive material 152 may be a metal other than copper, such as ruthenium, molybdenum, tungsten, or other suitable low-resistivity metals. In some embodiments, the conductive material 152 may be deposited using PVD, CVD, PE-CVD, ALD, PE-ALD, electroplating, electroless deposition, or other suitable deposition processes. After depositing the conductive material 152, a planarization process, such as a CMP process or a mechanical polishing process, may be performed to remove excess portions of the conductive material 152 and horizontal portions of the dielectric barrier layer 142, thereby forming a contact via 152 in the via opening 124, as shown in FIG. 8. The contact via 152 rests directly on the underlying metallic overlay layer 116 of the conductive topography 108, without any barrier layer between them. The bottom portion of the contact via 152 can utilize an extended footing profile to inherit the shape of the inhibitor film 140, so that the minimum width of the contact via 152 can be slightly above the bottom surface but below the top surface of the etch stop layer 118, or even below the top surface of the sublayer 118a of the etch stop layer 118.

[0034] Now, referring to FIG9, an etch stop layer 158 and a dielectric layer 160 are sequentially formed over the contact via 152 and the dielectric layer 120. The etch stop layer 158 has a high etch selectivity relative to the overlying dielectric layer 160, and therefore the etch stop layer 158 can be used to stop the etching of the dielectric layer 160. In some embodiments, the etch stop layer 158 can be deposited using ALD, plasma-enhanced ALD (PE-ALD), CVD, PE-CVD, or other suitable deposition processes. The etch stop layer 158 can be a single-layer structure or a multi-layer structure. In the illustrated embodiment, the etch stop layer 158 is a two-layer structure, comprising a first sublayer 158a and a second sublayer 158b. The first sublayer 158a and the second sublayer 158b comprise different material compositions, such as oxides and nitrides. In some embodiments, the material composition of the etch stop layer 158 is similar to that of the etch stop layer 118. A dielectric layer 160 is formed over an etch stop layer 158. According to some embodiments, the dielectric layer 160 is an IMD layer or an ILD layer. The dielectric layer 160 can be formed using spin coating, CVD, F-CVD, PE-CVD, LP-CVD, or similar methods. In some embodiments, the material composition of the dielectric layer 160 is similar to that of the dielectric layer 120. In some embodiments, the formation of the dielectric layer 160 includes depositing a dielectric material containing a pore-forming agent, followed by a curing process to remove the pore-forming agent, thus leaving a porous dielectric layer 160.

[0035] As shown in FIG. 10, a trench 164 is formed by etching. The trench 164 can be formed using a patterned hard mask 162 as an etching mask by, for example, photolithography. According to some embodiments of this disclosure, the etching of the dielectric layer 160 is performed using a process gas containing fluorine and carbon, wherein the fluorine is used for etching, and the carbon has the effect of protecting the sidewalls of the resulting opening. At an appropriate fluorine to carbon ratio, the trench 164 can have a desired profile. For example, the process gas used for etching includes a fluorine and carbon-containing gas, such as C4F8, CH2F2 and / or CF4, and a carrier gas, such as N2. In one example of the etching process, the flow rate of C4F8 is in the range of about 0 sccm to about 50 sccm, the flow rate of CF4 is in the range of about 0 sccm to about 300 sccm (wherein at least one of C4F8 and CF4 has a non-zero flow rate), and the flow rate of N2 is in the range of about 0 sccm to about 200 sccm. According to an alternative embodiment, the process gas for etching includes CH2F2 and a carrier gas, such as N2. In one example of the etching process, the flow rate of CH2F2 may be in the range of about 10 sccm to about 200 sccm, and the flow rate of N2 is in the range of about 50 sccm to about 100 sccm. During the etching process, the semiconductor device 100 may be maintained at a temperature in the range of about 30 °C to about 60 °C. During the etching process, plasma may be generated from the etching gas. The RF power of the power supply used for etching can be less than about 700 watts, and the pressure of the process gas is in the range of about 15 mTorr to about 30 mTorr. The etch stop layer 158 is then etched using a suitable etchant, and the contact via 152 and dielectric barrier layer 142 are exposed at the bottom of the trench 164. Extending the trench 164 through the dielectric layer 160 and further through the etch stop layer 158 is performed in separate photolithography processes. For example, in a first photolithography process, the trench 164 extends through the dielectric layer 160; in a second photolithography process, the trench 164 extends through the etch stop layer 158. The patterned hard mask 162 can be consumed during the photolithography process or removed in a separate etching process.

[0036] Referring to FIG. 11, a barrier layer 166 is conformally deposited on the exposed surface of the semiconductor device 100, and a liner 168 is conformally deposited on the barrier layer 166. The barrier layer 166 may be formed of a conductive material, also referred to as a conductive barrier layer, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials that can block the diffusion of metal elements, and may be deposited using atomic layer deposition (ALD), CVD, or physical vapor deposition (PVD), and may be formed to have a thickness between about 0.5 nm and about 5 nm. The barrier layer 166 covers the exposed top surface of the contact via 152. The liner 168 is conformally deposited on the barrier layer 166. In some embodiments, the liner 168 may be deposited using ALD, CVD, or PVD, and may be formed to have a thickness between about 0.5 nm and 3 nm. Liner 168 may be formed of a suitable metal or metal alloy, such as cobalt (Co) or an alloy of cobalt and ruthenium (Ru). In one example, liner 168 is made of Co. Liner 168 serves to increase the adhesion between the subsequently deposited metal filler layer and the barrier layer 166. Liner 168 may also be referred to as an adhesive layer.

[0037] Referring to FIG. 12, a conductive material 172 is deposited to fill the trench 164. The conductive material 172 is also referred to as a metal filler layer. The conductive material 172 may be copper. Alternatively, the conductive material 172 may be a metal other than copper, such as ruthenium, molybdenum, tungsten, or other suitable low-resistivity metals. In some embodiments, the conductive material 172 may be deposited using PVD, CVD, PE-CVD, ALD, PE-ALD, electroplating, electroless deposition, or other suitable deposition processes. After the conductive material 172 is deposited, a planarization process, such as a CMP process or a mechanical polishing process, may be performed to remove excess portions of the conductive material 172 (caused by the metal filler layer 172) and horizontal portions of the liner 168 and the barrier layer 166, thereby forming a metal line 174 in the trench 164, as shown in FIG. 13. The metal line 174 includes a barrier layer 166, a liner 168, a metal filler layer 172, and a metal capping layer 176.

[0038] Figure 13 also illustrates the formation of a metal capping layer 176 as the top portion of one of the metal lines 174. The metal capping layer 176 is deposited on the metal filler layer 172. In some embodiments, the CMP process performed before removing excess portions of the conductive material of the metal filler layer 172 also slightly recesses the top surfaces of the metal filler layer 172 and the liner 168. The metal capping layer 176 is deposited on the recessed top surfaces of the metal filler layer 172 and the liner 168. The barrier layer 166 may surround the metal capping layer 176 and separate the metal capping layer 176 from the dielectric layer 160 without contact. In some other embodiments, the CMP process recesses the metal filler layer 172 but not the liner 168, so that the liner 168 may surround the metal capping layer 176 and separate the metal capping layer 176 from the barrier layer 166 without contact. The metal capping layer 176 is formed of a conductive material, such as cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other suitable conductive materials. In some embodiments, the metal capping layer 176 and the liner 168 may have the same material composition. For example, both the metal capping layer 176 and the liner 168 may be formed of Co. In some other embodiments, the metal capping layer 176 and the liner 168 may include different material compositions. For example, the liner 168 may be formed of Co, and the metal capping layer 176 may be formed of Ru. In some embodiments, the metal capping layer 176 is thinner than the liner 168. Alternatively, the metal capping layer 176 may have the same thickness as or thicker than the liner 168.

[0039] In the illustrated embodiment of the semiconductor device 100 shown in FIG. 13, a barrier layer 166 covers the top surface of the contact via 152. FIG. 14-16 illustrate an alternative embodiment. Referring to FIG. 14, after deriving the structure of FIG. 10, an inhibitor film 180 is selectively formed on the exposed top surface of the contact via 152, but not on the sidewalls of the trench 164 and the top surface of the dielectric barrier layer 142. The inhibitor film 180 can be deposited by ALD, CVD, spin coating or other suitable deposition processes. The material composition of the inhibitor film 180 can be similar to that of the inhibitor film 140 as discussed above. The thickness of the inhibitor film 180 can be less than about 20 Å, which is less than the thickness of the etch stop layer 158 or even less than the thickness of the sublayer 158b of the etch stop layer 158. The inhibitor film 180 acts as an inhibitor for subsequent via barrier deposition processes. Referring to Figure 15, due to the presence of the inhibitor film 180, barrier deposition is suppressed on the surface of the conductive material. As a result, the barrier layer 166 is not formed on the exposed top surface of the contact via 152. After the barrier layer 166 conformally forms the sidewalls of the trench 164 and the liner for the exposed top surface of the dielectric layer 120 and the dielectric barrier layer 142, the inhibitor film 180 is removed in a post-deposition process similar to the post-deposition process 150 described above. After the top surface of the contact via 152 is exposed, the liner 168 is conformally deposited on the barrier layer 166 and covers the top surface of the contact via 152. Referring to Figure 16, the metal filler layer 172 and the metal capping layer 176 are sequentially deposited in the trench 164 to complete the formation of the metal line 174. As shown in Figure 16, the top surface of the contact via 152 is covered by the liner 168 instead of the barrier layer 166. Depending on the thickness of the lining 168, the bottom surface of the metal filler layer 172 may be lower than the top surface of the horizontal portion of the barrier layer 166.

[0040] Figures 17-20 illustrate an alternative embodiment. Referring to Figure 17, after deriving the structure in Figure 4, the dielectric barrier layer 142 and the conductive material 152 are sequentially deposited before and after the removal of the inhibitor film 140, respectively. One difference is that the dielectric barrier layer 142 is not deposited conformally, but rather the horizontal portion covering the top surface of the dielectric layer 120 is thicker than the vertical portion covering the sidewall of the via opening 124. This is likely because there can be relatively more open areas at the top surface of the dielectric layer 120 to facilitate the accumulation of dielectric material during the deposition process. Referring to Figure 18, the horizontal portion of the dielectric barrier layer 142 remains on the top surface of the dielectric layer 120 after the planarization process due to its relatively large thickness. Because the horizontal portion of the dielectric barrier layer 142 can act as an etch stop layer, the dielectric layer 160 is deposited directly on the horizontal portion of the dielectric barrier layer 142 and the top surface of the contact via 152. Referring to Figure 19, during the formation of trench 164, a portion of the horizontal portion of the dielectric barrier layer 142 exposed in trench 164 is also removed, so that the top surface of dielectric layer 120 is exposed in trench 164. In other words, the horizontal portion of dielectric barrier layer 142 is disconnected from its vertical portion. Referring to Figure 20, metal line 174 is formed in trench 164. As shown in Figure 20, barrier layer 166 forms the lining of the sidewalls and bottom surface of trench 164, and the horizontal portion of barrier layer 166 covers the top surface of dielectric layer 120, dielectric barrier layer 142, and contact via 152. Depending on the thickness of the horizontal portion of dielectric barrier layer 142, the top surface of the horizontal portion of dielectric barrier layer 142 may be higher than, flush with, or lower than the top surface of the horizontal portion of barrier layer 166.

[0041] Similar to the alternative embodiments illustrated in Figures 14-16, Figure 21 illustrates an alternative embodiment of the structure obtained in Figure 20, wherein the top surface of the contact via 152 is covered by a liner 168 instead of a barrier layer 166. Because an inhibitor film system deposited on the exposed metal surface inhibits barrier deposition, no barrier layer 166 is formed on the exposed top surface of the contact via 152. Depending on the thickness of the liner 168, the bottom surface of the metal filler layer 172 may be lower than the top surface of the horizontal portion of the barrier layer 166, and / or even lower than the top surface of the horizontal portion of the dielectric barrier layer 142.

[0042] Figures 22-23 illustrate an alternative embodiment. Referring to Figure 22, after deriving the structure in Figure 18, the trench 164 is formed by a photolithography process. One difference is that the dielectric barrier layer 142 acts as an etch stop layer, such that a portion of the horizontal portion of the dielectric barrier layer 142 exposed in the trench 164 is retained. In other words, the horizontal portion of the dielectric barrier layer 142 extends continuously from its vertical portion, and the top surface of the dielectric layer 120 remains covered by the dielectric barrier layer 142 and is not exposed in the trench 164. The etching process may optionally recess the top portion of one of the contact vias 152 below one of the top surfaces of the dielectric layer 120, as illustrated in Figure 22. Referring to Figure 23, a metal line 174 is formed in the trench 164. As shown in Figure 23, the barrier layer 166 forms the lining of the sidewalls and bottom surface of the trench 164, and separates the lining 168 from the contact through hole 152 without contacting it.

[0043] Similar to the alternative embodiments illustrated in Figures 14-16, Figure 24 illustrates an alternative embodiment of the structure obtained in Figure 23, wherein the top surface of the contact via 152 is covered by a liner 168 instead of a barrier layer 166. Because an inhibitor film deposited on the exposed metal surface inhibits barrier deposition, no barrier layer 166 is formed on the exposed top surface of the contact via 152. The bottom surface of the metal filler layer 172 protrudes downwards and may be lower than a top surface of the horizontal portion of the barrier layer 166, and / or even lower than a top surface of the horizontal portion of the dielectric barrier layer 142.

[0044] Referring back to Figure 1, as discussed above, the conductive morphology 108 can represent a contact plug in the contact layer or a metal line formed in the Mx layer, the contact via 152 can represent a contact via formed in the via_x layer, and the metal line 174 can represent a metal line formed in the Mx+1 layer. The embodiments of this disclosure have some advantageous features. By forming a barrier layer after the inhibitor film is formed, since the growth of the inhibitor film on different materials is selective, the resulting barrier layer is selectively formed on the sidewalls of the low-k dielectric layer to perform a diffusion blocking function, and is not formed on the underlying contact interface to avoid increasing the via contact resistance.

[0045] In one exemplary embodiment, this disclosure relates to a method of manufacturing a semiconductor device. The method includes: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer over the conductive topology; forming a first opening in the second dielectric layer to expose a top surface of the conductive topology; selectively depositing an inhibitor film on the top surface of the conductive topology; depositing a dielectric barrier layer on the sidewalls of the first opening; removing the inhibitor film to expose the top surface of the conductive topology; depositing a conductive material on the dielectric barrier layer and filling the first opening; and performing a planarization process to expose the dielectric barrier layer. In some embodiments, the inhibitor film comprises silane. In some embodiments, selectively depositing the inhibitor film includes a self-assembled monolayer (SAM) process. In some embodiments, the conductive material is in contact with the dielectric barrier layer. In some embodiments, after performing the planarization process, a top surface of the second dielectric layer is exposed. In some embodiments, after the planarization process is performed, the top surface of one of the second dielectric layers remains covered by a horizontal portion of the dielectric barrier layer. In some embodiments, the method further includes: after the planarization process, depositing a third dielectric layer over the planarized conductive material; forming a second opening in the third dielectric layer to expose the top surface of one of the planarized conductive materials; depositing a barrier layer on the sidewalls of the second opening; and depositing a metal filler layer over the barrier layer and filling the second opening. In some embodiments, the barrier layer is formed of a conductive material. In some embodiments, the planarized conductive material is in contact with the dielectric barrier layer, and the method further includes depositing a liner over the barrier layer, the liner separating the metal filler layer from the barrier layer without contact. In some embodiments, the liner is in contact with the top surface of the planarized conductive material.

[0046] In another exemplary embodiment, this disclosure relates to a method of forming a semiconductor structure. The method includes: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; forming a contact via through the second dielectric layer and onto a top surface of the conductive topology, the contact via being separated from the second dielectric layer by a dielectric barrier layer; forming a third dielectric layer over the second dielectric layer; and forming a metal line in the third dielectric layer and electrically coupled to the contact via. The metal line includes a metal fill layer separated from the third dielectric layer by a conductive barrier layer. In some embodiments, forming the contact via includes: forming a first opening in the second dielectric layer to expose the top surface of the conductive topography; selectively depositing an inhibitor film on the top surface of the conductive topography; depositing a dielectric barrier layer on the sidewall of the first opening; depositing a conductive material on the dielectric barrier layer and filling the first opening; and planarizing the conductive material to form the contact via. In some embodiments, forming the contact via further includes removing the inhibitor film after depositing the dielectric barrier layer. In some embodiments, forming the metal line includes: forming a second opening in the third dielectric layer to expose one of the top surfaces of the contact via; depositing a conductive barrier layer on the sidewall of the second opening; depositing a metal filler layer over the conductive barrier layer and filling the second opening; and planarizing the metal filler layer. In some embodiments, forming the metal line further includes forming a metal capping layer over the metal filler layer. In some embodiments, forming the metal circuit further includes: selectively depositing an inhibitor film on the top surface of the contact via; removing the inhibitor film after depositing the conductive barrier layer to expose the top surface of the contact via; and depositing a liner above the conductive barrier layer and in contact with the top surface of the contact via.

[0047] In yet another exemplary embodiment, this disclosure pertains to an interconnect structure. The interconnect structure includes: a conductive body disposed in a first dielectric layer; a second dielectric layer above the first dielectric layer; a contact via extending through the second dielectric layer and resting on a top surface of the conductive body; a dielectric barrier layer separating the contact via from the second dielectric layer; a third dielectric layer above the second dielectric layer; and a metal line disposed in the third dielectric layer and resting on a top surface of the contact via, the metal line including a barrier layer that separates a metal fill layer from the third dielectric layer without contacting it. In some embodiments, the barrier layer is a conductive barrier layer. In some embodiments, the metal line further includes a liner disposed between the barrier layer and the metal fill layer, wherein the liner contacts the top surface of the contact via. In some embodiments, a horizontal portion of the dielectric barrier layer covers a top surface of the second dielectric layer.

[0048] The foregoing has summarized the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] This disclosure is best understood in conjunction with the accompanying drawings and the following detailed description. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0009] FIG1 illustrates a cross-sectional view of a layer involved in an interconnect structure of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 and 24 illustrate cross-sectional views of an interconnect structure at an intermediate stage in the formation of one or more contact vias and metal wires according to various embodiments of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer over the conductive topology; forming a first opening in the second dielectric layer to expose a top surface of the conductive topology; selectively depositing an inhibitor film on the top surface of the conductive topology; depositing a dielectric barrier layer on the sidewall of the first opening, wherein the dielectric barrier layer has a tip formed on the bottom portion of the sidewall of the first opening; removing the inhibitor film to expose the top surface of the conductive topology; depositing a conductive material on the dielectric barrier layer and filling the first opening; and performing a planarization process to expose the dielectric barrier layer.

2. The method of claim 1, wherein after the planarization procedure is performed, one of the top surfaces of the second dielectric layer is exposed.

3. The method of claim 1, wherein after the planarization process is performed, one of the top surfaces of the second dielectric layer remains covered by a horizontal portion of the dielectric barrier layer.

4. The method of claim 1, further comprising: after performing the planarization process, depositing a third dielectric layer over the planarized conductive material; forming a second opening in the third dielectric layer to expose a top surface of the planarized conductive material; depositing a barrier layer on the sidewall of the second opening; and depositing a metal filler layer over the barrier layer and filling the second opening.

5. A method of forming a semiconductor structure, comprising: forming a conductive topology in a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; forming a contact via through the second dielectric layer and onto a top surface of the conductive topology, wherein the contact via is separated from the second dielectric layer by a dielectric barrier layer, wherein the dielectric barrier layer has a tip formed on the bottom portion of the sidewall of the contact via; forming a third dielectric layer over the second dielectric layer; and forming a metal line in the third dielectric layer and electrically coupled to the contact via, wherein the metal line includes a metal fill layer separated from the third dielectric layer by a conductive barrier layer.

6. The method of claim 5, wherein forming the contact via includes: A first opening is formed in the second dielectric layer to expose the top surface of the conductive topography; an inhibitor film is selectively deposited on the top surface of the conductive topography; a dielectric barrier layer is deposited on the sidewall of the first opening; a conductive material is deposited on the dielectric barrier layer and fills the first opening; and the conductive material is planarized as the contact via.

7. The method of claim 5, wherein forming the metal circuit includes: A second opening is formed in the third dielectric layer to expose one of the top surfaces of the contact via; the conductive barrier layer is deposited on the sidewall of the second opening; The metal filler layer is deposited over the conductive barrier layer and fills the second opening; and the metal filler layer is planarized.

8. An interconnect structure comprising: a conductive topology disposed in a first dielectric layer; a second dielectric layer above the first dielectric layer; a contact via extending through the second dielectric layer and abutting a top surface of the conductive topology; a dielectric barrier layer separating the contact via from the second dielectric layer, wherein the dielectric barrier layer has a tip formed on a bottom portion of a sidewall of the contact via; a third dielectric layer above the second dielectric layer; and a metal line disposed in the third dielectric layer and abutting a top surface of the contact via, the metal line including a barrier layer that separates a metal fill layer from the third dielectric layer without contact.

9. The interconnect structure of claim 8, wherein the metal line further includes a liner disposed between the barrier layer and the metal filler layer, and wherein the liner is in contact with the top surface of the contact via.

10. The interconnect structure of claim 8, wherein a horizontal portion of the dielectric barrier layer covers a top surface of the second dielectric layer.

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