Semiconductor devices and methods of manufacture

Abstract

In one embodiment, a method may include forming a multilayer stack on a substrate, the multilayer stack having alternating layers of a first semiconductor layer and a second semiconductor layer. The method may also include: forming a first source / drain region adjacent to the first and second semiconductor layers in a first region, the first source / drain region having a capping layer; forming a protective layer on the first source / drain region; forming a second source / drain region adjacent to the first and second semiconductor layers in a second region; removing the protective layer from the first source / drain region; replacing the first semiconductor layer in the first region with a first metal gate structure; and replacing the first semiconductor layer in the second region with a second metal gate structure.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor devices are widely used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate; and using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby enabling more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The best understanding of the various features disclosed herein can be achieved by referring to the accompanying drawings and the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, for ease of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) according to some embodiments in a three-dimensional view. Figures 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 16C Figures 17A, 17B, 17C, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, and 24C are cross-sectional views of intermediate stages in the fabrication of a nano-FET according to some embodiments. Figures 25 and 26 are cross-sectional views of a nano-FET according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and not limiting. For instance, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, this document uses spatial relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms to describe the relationship between an element or feature and other elements or features illustrated in the figures. In addition to the positioning described in the figures, spatial relative terms also include different positioning encompassed in use or operation. The device may also be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0008] This disclosure relates to semiconductor devices and methods for enhancing performance and reducing defects, particularly in the context of nanostructured field-effect transistors (nano-FETs). This disclosure addresses the challenges associated with protecting the source / drain regions during the manufacturing process. As semiconductor technology advances to increasingly smaller nodes, the need for more precise and reliable fabrication techniques becomes increasingly important. This disclosure introduces a silicon-based capping layer designed to enhance the protection of the p-type source / drain regions in nano-FETs.

[0009] In some nano-FET fabrication configurations, the source / drain epitaxial process sequence involves forming an n-type epitaxial region after the p-type epitaxial region. During the n-type epitaxial process, the p-type epitaxial region is protected by a protective layer (which may be an alumina layer). However, the protective layer may not provide uniform or sufficient coverage. Therefore, the underlying epitaxial layer of the p-type epitaxial structure is easily damaged by etching chemicals, especially chlorine-containing etchants used in subsequent n-type source / drain formation steps.

[0010] This invention addresses this issue by introducing a silicon capping layer as part of a p-type source / drain epitaxial structure. The capping layer can be a highly boron-doped silicon layer. Its thickness is controlled between 2 and 6 nanometers, completely covering the underlying layer and acting as a protective barrier. The capping layer is particularly effective against HCl and Cl2 etchants, providing a protective layer when the protective layer is insufficient.

[0011] This method offers several advantages. First, it significantly enhances the protection of the p-type source / drain regions, ensuring their integrity throughout the fabrication process. Improvements to the capping layer enhance the reliability of the nano-FET and potentially improve its performance. The capping layer can be composed of various materials such as Si, SiB, SiGe, or SiGeB, offering versatility that allows for manufacturing process flexibility and optimization of transistor characteristics.

[0012] Furthermore, by precisely controlling the thickness and shape of the capping layer, its protective properties can be fine-tuned, allowing manufacturers to customize the manufacturing process to specific requirements. This method, combined with existing nano-FET fabrication workflows, minimizes the need for significant modifications to existing manufacturing processes. By providing enhanced etch resistance and maintaining the integrity of the P-type source / drain regions, this method enables the production of more reliable and higher-performance nano-FETs, components in a wide range of electronic devices, from smartphones and computers to advanced AI systems and IoT devices.

[0013] The embodiments described below will be within the specific context of nano-FET transistors. However, various embodiments can also be applied to combinations of nano-FETs with other types of transistors (e.g., fin field effect transistors, planar transistors, or the like).

[0014] Figure 1 illustrates, in a three-dimensional view, an example of a nano-FET (e.g., a nanowire FET, a nanosheet FET, or the like) according to some embodiments. The nano-FET includes nanostructures 55 (e.g., nanosheets, nanowires, or the like) on fins 66 of a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions of the nano-FET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent isolation regions 68. Although the isolation regions 68 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer solely to a semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of the fins 66 is illustrated as a single, continuous material with the substrate 50, the bottom portion of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation areas 68.

[0015] Gate dielectric layer 100 is located on the top surface of fin 66 and on the top, sidewalls, and bottom surface of nanostructure 55. Gate electrode 102 is located on gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric layer 100 and gate electrode 102. Source / drain regions 92 may refer to a source or a drain, individually or jointly, depending on the context.

[0016] Figure 1 further illustrates the reference cross sections used in the following figures. Cross section A-A' is along the longitudinal axis of the gate electrode 102, oriented, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nano-FET fin 66, and is aligned with, for example, the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nano-FET. For clarity, these reference cross sections will be referenced in subsequent figures.

[0017] Some of the embodiments discussed herein are described in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider patterns used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0018] Figures 2 through 24C are cross-sectional views of intermediate stages in the manufacture of the nano-FET used in the SRAM device of Figure 1B according to some embodiments. Figures 2 through 5, 6A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, and 24A illustrate the reference cross-section A-A' illustrated in Figure 1. Figures 6B, 7B, 8B, 9B, 10B, 11B, 11C, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B illustrate the reference cross-section B-B' illustrated in Figure 1. Figures 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 16C, 17C, 22C, 23C and 24C illustrate the reference cross section C-C' shown in Figure 1.

[0019] In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano-FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown in the divider 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are described, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further, in Figure 2, a multilayer stack 64 is also formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). The multilayer stack 64 is illustrated as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano-FET (such as silicon germanium or the like), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano-FET (such as silicon, silicon carbon or the like). For illustrative purposes, the multilayer stack 64 is described as having its bottom semiconductor layer suitable for a p-type nano-FET. In some embodiments, the multilayer stack 64 may be formed with the bottom layer being a semiconductor layer suitable for an n-type nano-FET.

[0022] Referring now to Figure 3, according to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar, or combinations thereof. Etching can be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0023] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have, for example, smaller pitches compared to those obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned on a substrate using a photolithography process. Spacers are formed on the patterned sacrificial layer side using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins 66.

[0024] Figure 3 illustrates that the fins 66 in the n-type region 50N and the p-type region 50P have substantially equal widths, for illustrative purposes only. In some embodiments, the width of the fins 66 in the n-type region 50N may be larger or thinner than that in the p-type region 50P. Furthermore, although each fin 66 and nanostructure 55 is illustrated to have a uniform width, in other embodiments, the fins 66 and / or nanostructure 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0025] In Figure 4, shallow trench isolation (STI) region 68 is formed adjacent to fins 66. The STI region 68 is formed by depositing insulating material on the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, or similar materials, or combinations thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or similar materials, or combinations thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrative embodiment, the insulating material is silicon oxide formed by an FCVD process. Annealing can be performed after the insulating material is formed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is described as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not described separately) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. A filler material (such as those discussed above) may then be formed on the liner.

[0026] Next, a removal process is performed on the insulating material to remove excess insulating material from the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etching back, a combination thereof, or the like can be used. The planarization process exposes the nanostructure 55 so that, after the planarization process is completed, the top surfaces of the nanostructure 55 and the insulating material are flattened.

[0027] Next, the insulating material is recessed to form the STI region 68. After the insulating material is recessed, the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a planar, convex, concave (such as a dish shape), or combination thereof, as shown. The top surface of the STI region 68 may be formed into a planar, convex, and / or concave surface by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, such as an etching process selective for the insulating material (e.g., etching the insulating material faster than etching the fins 66 and nanostructures 55). For example, hydrogen fluoride, diluted hydrogen fluoride, another fluorine-based etchant, or the like can be used to remove oxides.

[0028] The process described above with respect to Figures 2 through 4 is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, photomasks and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may comprise alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used simultaneously.

[0029] Furthermore, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) described and discussed herein contain the same material in the p-type region 50P and the n-type region 50N, for illustrative purposes only. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials, or may be formed in different orders in the p-type region 50P and the n-type region 50N.

[0030] Furthermore, in Figure 4, suitable traps (not shown separately) can be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different trap types, different implantation steps for n-type region 50N and p-type region 50P can be implemented using photoresist or other photomasks (not shown separately). For example, photoresist can be formed on fin 66 and STI region 68 of n-type region 50N and p-type region 50P. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using spin coating technology and can be patterned using acceptable lithography techniques. After the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, with the photoresist acting as a photomask to substantially prevent n-type impurity implantation into n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, or the like, with a concentration in the implanted region ranging from 10¹³ atoms / cm³ to 10¹⁴ atoms / cm³. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0031] Before or after implantation into the p-type region 50P, a photoresist or other photomask (not separately described) is formed on the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and can be patterned using acceptable lithography techniques. After the photoresist is patterned, p-type impurities are implanted into the n-type region 50N. The photoresist acts as a photomask, essentially preventing the implantation of p-type impurities into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or similar substances, and the concentration of the impurity implanted in the region ranges from 10¹³ atoms / cm³ to 10¹⁴ atoms / cm³. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0032] After implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used simultaneously.

[0033] In Figure 5, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. For example, the dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a photomask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and then planarized, such as by CMP. The photomask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 72 can be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 can be made of other materials that have high etch selectivity when etching the isolation region. For example, the photomask layer 74 may include silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single photomask layer 74 are formed between the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown only covering the fin 66 and nanostructure 55, for reference only. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, extending between the dummy gate layer 72 and the STI region 68.

[0034] Figures 6A through 24C illustrate various additional steps in manufacturing the apparatus of the embodiment. Figures 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, and 24B illustrate features in region 50N or region 50P. In Figures 6A and 6B, the photomask layer 74 (see Figure 5) can be patterned using acceptable photolithography and etching techniques to form a photomask 78. The pattern of the photomask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the respective channel regions of the fin 66. The pattern of the photomask 78 can be used to separate each dummy gate 76 from adjacent dummy gate 76 entities. The longitudinal direction of the dummy gate 76 can also be substantially perpendicular to the longitudinal direction of the individual fins 66.

[0035] In Figures 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed on the structures shown in Figures 6A and 6B, respectively. The first spacer layer 80 and the second spacer layer 82 will then be patterned as spacers for forming self-aligned source / drain regions. In Figures 7A and 7B, the first spacer layer 80 is formed on the top surface of the STI region 68, the fin 66, the nanostructure 55, the top surface and sidewalls of the photomask 78, and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. The second spacer layer 82 is deposited on the first spacer layer 80. When using techniques such as thermal oxidation or deposition by CVD, ALD, or the like, the first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer 82 may be formed of a material with an etch rate different from that of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride or similar materials, and may be deposited by CVD, ALD or similar methods.

[0036] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation can be performed on the lightly doped source / drain (LDD) region (not described separately). In embodiments with different device types, similar to the implantation discussed above in Figure 4, a photomask (such as a photoresist) can be formed on the n-type region 50N, exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P. The photomask is then removed. Subsequently, a photomask (such as a photoresist) can be formed on the p-type region 50P, exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The photomask is then removed. The n-type impurity can be any n-type impurity discussed above, and the p-type impurity can be any p-type impurity discussed above. The impurity concentration in the lightly doped source / drain regions ranges from 10¹⁵ atoms / cm³ to 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0037] In Figures 8A and 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching), anisotropic etching process (e.g., dry etching), or the like. In some embodiments, the material of the second spacer layer 82 is etched at a different rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and the second spacer layer 82 can act as a photomask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 acts as an etching stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in Figure 8A. Subsequently, the second spacer 83 acts as a photomask, while the exposed portion of the first spacer layer 80 is etched, thereby forming the first spacer 81, as shown in Figure 8A.

[0038] As shown in Figure 8A, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. As shown in Figure 8B, in some embodiments, the second spacer 82 can be removed from the first spacer layer 80 adjacent to the photomask 78, the dummy gate 76, and the dummy gate dielectric 71, with the first spacer 81 disposed on the sidewalls of the photomask 78, the dummy gate 76, and the dummy dielectric layer 60. In other embodiments, a portion of the second spacer 82 may remain on the first spacer layer 80 adjacent to the photomask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0039] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or similar methods may be used. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0040] In Figures 9A and 9B, a first recess 84 is formed in the fin 66, nanostructure 55, and substrate 50 in both the p-type region 50P and the n-type region 50N. An epitaxial source / drain region is subsequently formed in the first recess 84. The first recess 84 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in Figure 9A, the top surface of the STI region 58 may be flush with the bottom surface of the first recess 84. In various embodiments, the fin 66 may be etched such that the bottom surface of the first recess 84 is positioned below the top surface of the STI region 68; or similarly. The first recess 84 can be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (such as RIE, NBE, or similar). During the etching process used to form the first recess 84, a second spacer 83 and a photomask 78 shield portions of the fin 66, nanostructure 55, and substrate 50. Each layer of the nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first recess 84 after it has reached the desired depth.

[0041] In Figures 10A and 10B, portions of the sidewalls of the multilayer stack 64 formed by the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 84 are etched to form sidewall recesses 88 in both the p-type region 50P and the n-type region 50N. Although the sidewalls of the first nanostructure 52 in the sidewall recess 88 are shown as straight in Figure 10B, the sidewalls may be concave or convex (e.g., see Figure 11C). The etching may be isotropic or anisotropic.

[0042] As an example of the process, an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 (but some etching may occur). In an embodiment where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a wet or dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52.

[0043] In some embodiments, due to the etching selectivity between the materials of the first nanostructure 52 and the second nanostructure 54, the recess 88 may extend upward and / or downward, making the shape of the recess 88 more trapezoidal. In some embodiments, the recess will have a flat upper surface and a flat lower surface.

[0044] In Figures 11A to 11C, a first internal spacer 90 is formed in the sidewall recesses 88 of both the p-type region 50P and the n-type region 50N. The first internal spacer 90 can be formed by depositing an internal spacer layer (not described separately) on the structure shown in Figures 10A and 10B. The first internal spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure (discussed further below).

[0045] The internal spacer can be deposited using a conformal deposition process (such as CVD, ALD, or similar) to form the shape of the recess 88. The internal spacer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than 3.5. The internal spacer can then be anisotropically etched to form a first internal spacer 90. Although the outer sidewall of the first internal spacer 90 is depicted as flush with the sidewall of the second nanostructure 54, the outer sidewall of the first internal spacer 90 can extend beyond or be recessed from the sidewall of the second nanostructure 54. Once formed, the first internal spacer 90 forms the shape of the sidewall of the recess 88, such that the first internal spacer 90 can have a flat upper / bottom surface or an extended surface with a trapezoidal shape.

[0046] Furthermore, although the outer wall of the first internal spacer 90 is shown as straight in Figure 11B, the outer wall of the first internal spacer 90 may be concave or convex. For example, Figure 11C illustrates the following embodiment in which the sidewall of the first nanostructure 52 is concave, the outer wall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54.

[0047] In Figures 12A to 16C, epitaxial source / drain regions 92 are formed in the first recesses 84 of both the p-type region 50P and the n-type region 50N. The source / drain regions 92 can apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. In some embodiments, the epitaxial source / drain regions 92 may comprise one or more semiconductor material layers, and in some embodiments, the epitaxial source / drain regions 92 may be formed in the p-type region 50P before being formed in the n-type region 50N.

[0048] By shielding the n-type region 50N, such as an NMOS region, an epitaxial source / drain region 92, such as a PMOS region, can be formed in the p-type region 50P. Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 84 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nano-FET. For example, if the second nanostructure 54 is silicon-based, the epitaxial source / drain region 92 can include a material that applies compressive strain to the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 92 can also have surfaces protruding from individual surfaces of the multilayer stack 64 and can have facets.

[0049] By shielding the p-type region 50P, such as a PMOS region, an epitaxial source / drain region 92, such as an NMOS region, can be formed in the n-type region 50N. Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 84 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have surfaces protruding from individual upper surfaces of the nanostructure 55 and may have facets.

[0050] Figures 12A through 16C illustrate an exemplary process for forming an epitaxial source / drain region 92 in a p-type region 50P prior to its formation in the n-type region 50N. In Figures 12A through 12B, a first semiconductor material layer 92A and a second semiconductor material layer 92B are formed in a first recess 84 in both the p-type region 50P and the n-type region 50N. As described in subsequent figures, the epitaxial source / drain region may further include a third semiconductor material layer 92C and a fourth semiconductor material layer 92D. Although four layers are illustrated and described in the figures, any number of semiconductor material layers may be used for the epitaxial source / drain region 92. In some embodiments, the second semiconductor material layer 92B is omitted.

[0051] The first semiconductor material layer 92A (also referred to as L0) may be an undoped or lightly doped layer, which can prevent or reduce the diffusion of dopants from the overlying epitaxial layers (e.g., particularly the third and fourth semiconductor material layers 92C and 92D) into the underlying substrate 50. In a specific example, the first semiconductor material layer 92A may be a silicon layer that is substantially free of germanium. In some embodiments, the first semiconductor material layer 92A may be formed by a bottom-up epitaxial growth process.

[0052] In embodiments including a second semiconductor material layer 92B (also referred to as L1), the second semiconductor material layer 92B may also be a silicon layer that is substantially free of germanium. In some embodiments, when the first nanostructures 52A-C are removed, the second semiconductor material layer 92B may delay the leakage of etchant from the first nanostructures 52A-C (e.g., see Figures 20A-20B). In some embodiments, the second semiconductor material layer 92B may comprise silicon, boron-doped silicon (SiB), similar materials, or combinations thereof. The second semiconductor material layer 92B may be formed by an epitaxial process, with silicon precursors including silane (SiH4)dichlorosilane (DCS) and boron precursors including B2H6 or BCl3. The second semiconductor material layer 92B may include a lateral portion 92B' formed by applying a doping process to an undoped or lightly doped first semiconductor material layer 92A. In subsequent figures along the cross-section of Figure 12B, the multilayers 92A~92D of the epitaxial source / drain regions 92 are only described in the central recess 84, but the outer recesses 84 of each region have a similar configuration to the epitaxial source / drain regions 92.

[0053] In Figures 13A and 13B, the remaining layer of the epitaxial source / drain region 92 is formed in the p-type region 50P. This process may first form a photomask layer 93 (also referred to as a protective layer 93) on the n-type region 50N and the p-type region 50P. In some embodiments, the photomask layer 93 comprises an oxide layer, such as aluminum oxide, but other suitable materials are within the scope of this disclosure. The photomask layer 93 may be a conformal layer with a substantially uniform thickness on both vertical and horizontal surfaces (within the range of process variations). The photomask layer 93 may be removed from the p-type region 50P. In some embodiments, the p-type region 50P is exposed by forming a photoresist and / or a photomask (not described separately) and patterning the photoresist and / or photomask, followed by an etching process to remove the exposed photomask layer 93 in the p-type region 50P, thereby removing the photomask layer 93. Once the photomask layer 93 is patterned, a third semiconductor material layer 92C (which may be referred to as L2) can be formed on the second semiconductor material layer 92B, and a fourth semiconductor material layer 92D (which may be referred to as L3) can be formed on the third semiconductor material layer 92C.

[0054] The epitaxial growth process of the source / drain region 92 in the p-type region 50P involves sequentially forming a third semiconductor material layer 92C and a fourth semiconductor material layer 92D. The third semiconductor material layer 92C is epitaxially grown from a lower layer (a first or second semiconductor material layer 92A or 92B and / or a second semiconductor nanostructure 54, depending on the presence of the second semiconductor material layer 92B). The third semiconductor material layer 92C may be a boron-doped silicon-germanium layer. In some embodiments, the boron concentration of the third semiconductor material layer 92C ranges from 7 x 10²⁰ atoms / cm³ to 1 x 10²¹ atoms / cm³, and the germanium concentration ranges from 50% to 60%.

[0055] After the formation of the third semiconductor material layer 92C, a fourth semiconductor material layer 92D (also referred to as the capping layer 92D) is epitaxially grown from the third semiconductor material layer 92C. The fourth semiconductor material layer 92D can be used as a protective layer and can have various compositions. In one configuration, the fourth semiconductor material layer 92D is a boron-doped silicon-germanium layer. In some embodiments, the boron concentration of the fourth semiconductor material layer 92D can range from 0 to 1 x 10²² atoms / cm³, and the germanium concentration is less than 20%. In some embodiments, the fourth semiconductor material layer 92D can be composed of germanium-free silicon, or it can be a boron-free pure silicon layer. In some embodiments, the fourth semiconductor material layer 92D can be made of Si, SiB, SiGe, or SiGeB. Regardless of its specific composition, the germanium concentration in the third semiconductor material layer 92C is higher than that in the fourth semiconductor material layer 92D.

[0056] When the fourth semiconductor layer 92D is a highly boron-doped silicon layer, it provides protection against HCl etching during wet cleaning processes after p-type epitaxy or during n-type epitaxy processes. This protection is particularly useful when the subsequently formed protective layer 95 (e.g., see Figures 14A-14B) does not completely cover the source / drain regions 92 in the p-type region 50P. The fourth semiconductor layer 92D acts as a protective layer during the formation of the n-type epitaxial source / drain regions 92, preventing etching damage. Specifically, in some embodiments, the fourth semiconductor layer 92D can protect against HCl and Cl2 etchants, as well as other chlorine-containing etchants.

[0057] The fourth semiconductor material layer 92D is designed to completely cover the third semiconductor material layer 92C. In some embodiments, the thickness of the fourth semiconductor material layer 92D ranges from 2 nm to 6 nm, and the fourth semiconductor material layer 92D maintains this thickness along the (001), (110), and (111) crystallographic directions. This uniform coverage ensures complete protection of the underlying layer during subsequent processing steps.

[0058] In some embodiments, each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, the third semiconductor material layer 92C, and the fourth semiconductor material layer 92D may be formed of different semiconductor materials and may be doped with different concentrations of dopants.

[0059] In Figures 14A and 14B, the photomask layer 93 is removed from the n-type region 50N, and a protective layer 95 is formed in both regions 50P and 50N. In some embodiments, the protective layer 95 comprises an oxide layer, such as aluminum oxide, but other suitable materials are within the scope of this disclosure. The protective layer 95 may be a conformal layer with a substantially uniform thickness on both vertical and horizontal surfaces (within the range of process variations).

[0060] In Figures 15A and 15B, the protective layer 95 is removed from the n-type region 50N, and the remaining portion of the epitaxial source / drain 92 is formed in the n-type region 50N. In some embodiments, the n-type region 50N is exposed by forming a photomask (not shown separately) and a patterned photomask, followed by an etching process to remove the exposed protective layer 95 in the n-type region 50N, thus removing the protective layer 95.

[0061] Forming the epitaxial source / drain region 92 in the n-type region 50N can include any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon-based, the epitaxial source / drain region 92 can include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. In some embodiments, a third semiconductor material layer 92C is grown in the n-type region 50N having a suitable material composition. The capping layer 92D may be omitted from the n-type region 50N. Forming the third semiconductor material layer 92C in the n-type region 50N can include an etching step using a chlorine-containing etchant, such as in deposition and etching cycles. As described above, the fourth semiconductor material layer 92D in the p-type region 50P acts as a protective layer during the formation of the n-type epitaxial source / drain region 92, preventing etching damage. Specifically, in some embodiments, the fourth semiconductor material layer 92D can protect against HCl and Cl2 etchants and other chlorine-containing etchants.

[0062] As shown in Figure 15B, the epitaxial source / drain regions 92 in both regions 50P and 50N are formed in the first recess 84, such that each dummy gate 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 at an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate subsequently formed in the resulting nano-FET.

[0063] During the respective formation processes of each region 50N and 50P, dopants may be implanted into the epitaxial source / drain regions 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 to form source / drain regions, similar to the process for forming lightly doped source / drain regions described above, followed by annealing. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0064] Several advantages are achieved by using a fourth semiconductor material layer 92D (which may be referred to as a capping layer or L3 layer) in the source / drain region 92 of the p-type region 50P. First, this method significantly enhances the protection of the p-type source / drain region, ensuring its integrity throughout the fabrication process. The improved protective layer increases the reliability and performance of the resulting nano-FET. The fourth semiconductor material layer 92D can be composed of various materials such as Si, SiB, SiGe, or SiGeB, and its versatility allows for manufacturing process flexibility and optimization of transistor characteristics. Furthermore, its protective characteristics can be fine-tuned by precisely controlling the thickness and shape of the fourth semiconductor material layer 92D. The disclosed process also integrates with existing nano-FET fabrication workflows, minimizing the need for extensive modifications to existing manufacturing processes.

[0065] In Figures 16A to 16C, the protective layer 95 is removed after the epitaxial source / drain region 92 is formed. Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain region 92 has facets extending outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nano-FET to merge, as shown in Figure 16C. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in Figure 16A. In the embodiments illustrated in Figures 16A and 16C, a first spacer 81 may be formed on the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, thereby extending the epitaxial growth region to the surface of the STI region 58.

[0066] In Figures 17A to 17C, a first interlayer dielectric (ILD) 96 is deposited on the structures illustrated in Figures 6A, 16B, and 16A, respectively (the process in Figures 7A to 16C does not change the cross-section illustrated in Figure 6A). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the photomask 78, and the first spacer 81. The CESL 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with an etch rate different from that of the material covering the first ILD 96.

[0067] In Figures 18A and 18B, a planarization process, such as CMP, can be performed to planarize the top surface of the first ILD 96 with the top surface of the dummy gate 76 or the photomask 78. The planarization process can also remove the photomask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewall of the photomask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 remain planar within the range of process variations. Therefore, the top surface of the dummy gate 76 is exposed by the first ILD 96. In some embodiments, the photomask 78 can be retained, in which case the planarization process plans the top surface of the first ILD 96 with the top surfaces of the photomask 78 and the first spacer 81.

[0068] In Figures 19A and 19B, the dummy gate 76 and photomask 78 (if present) are removed in one or more etching steps to form a second recess 98. A portion of the dummy dielectric layer 60 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy dielectric layer 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, which may selectively etch the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers a portion of a nanostructure 55, which serves as a channel region in the subsequently completed nano-FET. The portion of the nanostructure 55 serving as the channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may be used as an etch stop layer while the dummy gate 76 is etched. After removing the dummy gate 76, the dummy dielectric layer 60 can be removed.

[0069] In Figures 20A and 20B, the first nanostructure 52 in the n-type region 50N and the p-type region 50P is removed. The first nanostructure 52 can be removed by performing an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 58 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructure 52.

[0070] In Figures 21A and 21B, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N and the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 58.

[0071] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include an interfacial silicon oxide layer and a metal oxide layer situated on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, wherein the k value of the gate dielectric layer 100 may be greater than 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0072] Gate electrodes 102 are deposited on gate dielectric layer 100 and fill the remaining portion of second recess 98. Gate electrode 102 includes a protective layer (such as silicon), a barrier layer (such as titanium nitride), a work function material (such as titanium nitride, titanium oxide, tantalum nitride, titanium carbide, cobalt, ruthenium, aluminum, titanium aluminum, tungsten, or other metallic materials), combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 102 is illustrated in Figures 19A and 19B, gate electrode 102 may include any number of pad layers, any number of work function tuning layers, and filler material. Any combination of layers constituting gate electrode 102 may be deposited between adjacent second nanostructures 54 in n-type region 50N and p-type region 50P, and between second nanostructure 54A and substrate 50.

[0073] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can be performed simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can be performed simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0074] After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, which lies on the top surface of the first ILD 96. Thus, the remaining material of the gate electrode 102 and the gate dielectric layer 100 forms the replacement gate structure of the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0075] In Figures 22A to 22C, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed, forming a recess between the gate structure and the opposing portion of the first spacer 81. A gate mask 104 containing one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled into the recess, followed by a planarization process to remove excess dielectric material extending onto the first ILD 96. The gate mask 104 is optional and may be omitted in some embodiments. The subsequently formed gate contacts (such as contact 114 discussed below with respect to Figures 24A to 24C) penetrate the gate mask 104 and contact the top surface of the recessed gate electrode 102.

[0076] As further illustrated in Figures 22A to 22C, the second ILD 106 is deposited on the first ILD 96 and the gate photomask 104. In some embodiments, the second ILD 106 is a flowable thin film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0077] In Figures 23A to 23C, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, or the like). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and then it can be etched through the CESL 94 using a third etching process. A photomask, such as a photoresist, can be formed and patterned on the second ILD 106 to mask portions of the second ILD 106 during the first and second etching processes. In some embodiments, the etching process may over-etch; therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level, or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 23B illustrates that the third recess 108 exposes the epitaxial source / drain region 92 and gate structure in the same cross-section, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross-sections, thereby reducing the risk of subsequent short circuits at the contacts. After forming the third recess 108, a silicon region 110 is formed on the epitaxial source / drain region 92. In some embodiments, a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, is formed by first depositing a metal (not shown) that reacts with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 on the exposed portion of the epitaxial source / drain region 92. A thermal annealing process is then performed to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanium region (e.g., a region containing both silicide and germanide). In one embodiment, the silicide region 110 comprises TiSi with a thickness ranging from 2 nm to 10 nm.

[0078] Next, in Figures 24A to 24C, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, contacts 112 and 114 each comprise a barrier layer and a conductive material, and are electrically coupled to an underlying conductive feature (e.g., the gate electrode 102 and / or the silicate region 110 in the illustrated embodiments). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, while contact 112 is electrically coupled to the silicate region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Planarization processes, such as CMP, can be performed to remove excess material from the surface of the second ILD 106.

[0079] In some embodiments, the contact 112 in the p-type region 50P extends through the fourth semiconductor layer 92D to the third semiconductor layer 92C. In some embodiments, the contact 112 in the p-type region 50P does not extend through the fourth semiconductor layer 92D to the third semiconductor layer 92C. In some other embodiments, only the silicon region 110 in the p-type region 50P extends through the fourth semiconductor layer 92D to the third semiconductor layer 92C.

[0080] Figures 25 and 26 illustrate cross-sectional views of an apparatus according to some embodiments. Figures 25 and 26 illustrate the reference cross-section C-C' illustrated in Figure 1. In Figures 25 and 26, the same reference numerals denote the same elements formed by the same process as in the embodiments of Figures 2 through 24C. Figures 25 and 26 each illustrate a p-type region 50P at a processing point similar to that in Figure 15A.

[0081] Figures 25 and 26 illustrate different cross-sectional shapes of the fourth semiconductor layer 92D. These shape differences can be controlled by the shape of the underlying layer (e.g., 92C), the parameters of the fabrication process of layer 92D, and / or the crystallographic orientation of the layer. For example, in Figure 25, the fourth semiconductor layer 92D is more rounded or circular in cross-section. In Figure 26, the fourth semiconductor layer 92D has a more square shape in cross-section, or can be described as having a flat top. In the embodiment of Figure 25, the shape of the fourth semiconductor layer 92D is limited by facets at the 111 plane, which may be due to the epitaxial growth temperature range between 600°C and 700°C. In the embodiment of Figure 26, the shape of the fourth semiconductor layer 92D is more conformal, which may be due to the lower epitaxial growth temperature range between 500°C and 580°C.

[0082] The embodiments disclosed herein offer several advantages. By utilizing a highly boron-doped silicon layer to protect the p-type source / drain regions in the nano-FET, the nano-FET fabricated using the disclosed process exhibits higher reliability and performance. In some configurations of nano-FET fabrication, the source / drain epitaxial process sequence involves forming an n-type epitaxial region after the p-type epitaxial region. During the n-type epitaxial process, the p-type epitaxial region is protected by a protective layer (e.g., an alumina layer). However, the protective layer may not provide uniform or sufficient coverage. Therefore, the underlying epitaxial layer of the p-type epitaxial structure may be damaged by etching chemicals, particularly chlorine-containing etchants used in subsequent n-type source / drain formation steps.

[0083] This disclosure addresses this issue by introducing a highly boron-doped silicon layer as part of the p-type source / drain epitaxial structure. This layer completely covers the underlying layer, acting as a protective barrier. The highly boron-doped silicon layer is particularly effective against HCl and Cl2 etchants, providing a layer of protection when the protective layer is insufficient. This significantly enhances the protection of the p-type source / drain region, ensuring its integrity throughout the fabrication process. The improved protective layer increases the reliability and performance of the resulting nano-FET.

[0084] In one embodiment, a method may include forming a multilayer stack on a substrate, the multilayer stack having alternating layers of first semiconductor layers and second semiconductor layers. The method may also include: forming first source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a first region, the first source / drain regions having a capping layer; forming a protective layer on the first source / drain regions; forming second source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a second region; removing the protective layer from the first source / drain regions; replacing the first semiconductor layers in the first region with a first metal gate structure; and replacing the first semiconductor layers in the second region with a second metal gate structure.

[0085] The embodiments may also include one or more of the following features: The protective layer may include a method of using aluminum oxide. The first source / drain regions are portions of a PMOS transistor. The second source / drain regions are portions of an NMOS transistor. Forming the protective layer on the first source / drain regions and the second source / drain regions may include forming the protective layer on the first source / drain regions and the second source / drain regions; and removing the protective layer from the second source / drain regions. Forming the second source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in the second region may include etching the second source / drain regions with a chlorine-containing etchant, exposing the protective layer to the chlorine-containing etchant. The capping layer of the first source / drain regions is exposed to the chlorine-containing etchant. Each of the first source / drain regions may include a first layer, a second layer on the first layer, and a capping layer on the second layer, wherein the first layer is a silicon layer, the second layer is a boron-doped silicon-germanium layer, and the capping layer is a boron-doped silicon layer. The capping layer may have a higher boron doping concentration than the second layer. The capping layer may include germanium with a lower germanium concentration than the second layer. The method may include forming an interlayer dielectric on the first and second source / drain regions; and forming a conductive contact in the interlayer dielectric and electrically coupling it to the first source / drain regions, the conductive contact extending through the capping layer of the first source / drain regions.

[0086] In one embodiment, a method may include forming a multilayer stack on a substrate, the multilayer stack having alternating layers of first semiconductor layers and second semiconductor layers. The method may also include: forming first source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a first region, the first source / drain regions having a capping layer; forming a protective layer on the first source / drain regions; forming second source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a second region; etching the second source / drain regions with a chlorine-containing etchant, wherein the protective layer and the capping layer of the first source / drain regions are exposed to the chlorine-containing etchant; removing the protective layer from the first source / drain regions; replacing the first semiconductor layers in the first region with a first metal gate structure; and replacing the first semiconductor layers in the second region with a second metal gate structure.

[0087] The embodiments may also include one or more of the following features. The protective layer may include a method of using aluminum oxide. Forming the first source / drain regions may include growing a first layer having silicon; growing a second layer on the first layer having boron-doped silicon-germanium; and growing the capping layer on the second layer having boron-doped silicon. The capping layer has a higher boron doping concentration than the second layer; the capping layer may include germanium and its germanium concentration is lower than that of the second layer; and the capping layer has a thickness ranging from 2 nm to 6 nm. The capping layer may include Si, SiB, SiGe, or SiGeB.

[0088] In one embodiment, a semiconductor device may include a channel region stack located on a substrate. The semiconductor device may also include: first source / drain regions adjacent to the channel region stack in a first region of the substrate, each of the first source / drain regions having: a first layer comprising silicon; a second layer on the first layer, the second layer comprising boron-doped silicon-germanium; and a capping layer on the second layer, the capping layer having boron-doped silicon; a first metal gate structure surrounding the channel regions in the first region; and conductive contacts on and electrically coupled to the first source / drain regions, the conductive contacts extending through the capping layer of the first source / drain regions.

[0089] The embodiments may also include one or more of the following features: The boron doping concentration of the capping layer is higher than that of the second layer; and the capping layer may include a semiconductor device with a germanium concentration lower than that of the second layer. The capping layer may include a semiconductor device of Si, SiB, SiGe, or SiGeB. The semiconductor device may include: a second source / drain region adjacent to the channel regions in a second region of the substrate; and a second metal gate structure surrounding the channel regions in the second region, wherein the first source / drain regions are portions of a PMOS transistor, and the second source / drain regions are portions of an NMOS transistor.

[0090] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0091] 50: Substrate / Lower Substrate 50N: n-type region 50P:p-type area 51: First semiconductor layer 51A, 51B, 51C: First semiconductor layer 52: First nanostructure 52A, 52B, 52C: First nanostructure 53: Second semiconductor layer 53A, 53B, 53C: Second semiconductor layer 54: Second nanostructure 54A, 54B, 54C: Second nanostructure 55: Nanostructure 58: Shallow Trench Isolation (STI) Area 60: Dummy dielectric layer 64: Multi-layer stacking 66: Fins 68: Isolation Zone / Shallow Trench Isolation (STI) Zone 70: Dummy Dielectric Layer 71: Dummy gate dielectric 72: Dummy gate layer 74: Photomask layer 76: Dummy gate 78: Light Mask 80: First Spacing Layer 81: First spacer 82: Second spacer layer 83: Second spacer 84: First concave part 88: Side wall recess 90: First internal spacer 92: Epitaxial Source / Drain Region 92A: First semiconductor material layer 92B: Second semiconductor material layer 92B': Lateral portion 92C: Third semiconductor material layer 92D: Fourth semiconductor material layer / capping layer 93: Photomask / Protective Layer 94: Contact Etching Stop Layer (CESL) 95: Protective layer 96: Interlayer Dielectric (ILD) 98:Second recess 100: Gate dielectric layer 102: Gate electrode 104: Gate Electrode 106: Interlayer Dielectric (ILD) 108: The third concave part 110: Silicon region 112:Contact 114:Contact

[0092] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a multilayer stack on a substrate, the multilayer stack including alternating layers of first semiconductor layers and second semiconductor layers; forming first source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a first region, the first source / drain regions including a capping layer; and forming a protective layer on the first source / drain regions; forming second source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a second region; removing the protective layer from the first source / drain regions; replacing the first semiconductor layers in the first region with a first metal gate structure; and replacing the first semiconductor layers in the second region with a second metal gate structure.

2. The method as described in claim 1, wherein the protective layer comprises aluminum oxide.

3. The method as described in claim 1, wherein forming the protective layer on the first source / drain regions comprises: forming the protective layer on the first source / drain regions and the second source / drain regions; and removing the protective layer from the second source / drain regions.

4. The method as claimed in claim 1, wherein forming the second source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in the second region comprises: etching the second source / drain regions with a chlorine-containing etchant, wherein the protective layer is exposed to the chlorine-containing etchant.

5. A method of manufacturing a semiconductor device, comprising: forming a multilayer stack on a substrate, the multilayer stack including alternating layers of first semiconductor layers and second semiconductor layers; forming first source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a first region, the first source / drain regions including a capping layer; forming a protective layer on the first source / drain regions; forming second source / drain regions adjacent to the first semiconductor layers and the second semiconductor layers in a second region; etching the second source / drain regions with a chlorine-containing etchant, wherein the capping layer of the first source / drain regions is exposed to the chlorine-containing etchant; removing the protective layer from the first source / drain regions; replacing the first semiconductor layers in the first region with a first metal gate structure; and replacing the first semiconductor layers in the second region with a second metal gate structure.

6. The method as described in claim 5, wherein the protective layer comprises aluminum oxide.

7. The method as described in claim 5, wherein forming the first source / drain regions comprises: growing a first layer comprising silicon; growing a second layer on the first layer, the second layer comprising boron-doped silicon germanium; and growing the capping layer on the second layer, the capping layer comprising boron-doped silicon.

8. A semiconductor device comprising: a channel region stack on a substrate; first source / drain regions adjacent to the channel region stack in a first region of the substrate, each of the first source / drain regions comprising: a first layer comprising silicon; a second layer on the first layer comprising boron-doped silicon germanium; and a capping layer on the second layer comprising boron-doped silicon and free of germanium; a first metal gate structure surrounding the channel regions in the first region; and conductive contacts on and electrically coupled to the first source / drain regions, the conductive contacts extending through the capping layer of the first source / drain regions.

9. The semiconductor device as claimed in claim 8, wherein: The boron doping concentration of the capping layer is higher than that of the second layer.

10. The semiconductor device of claim 8, further comprising: a second source / drain region adjacent to the channel regions in a second region of the substrate; and a second metal gate structure surrounding the channel regions in the second region, wherein the first source / drain regions are portions of a PMOS transistor, and the second source / drain regions are portions of an NMOS transistor.

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