Method of forming semiconductor device

Abstract

A method of forming a semiconductor device includes: forming a conductive feature over a substrate; forming a dielectric layer over the conductive feature and the substrate; forming a layer of polycrystalline material over the dielectric layer, wherein a first facet and a second facet of the polycrystalline material have different lattice densities; selectively adsorbing material molecules on the first facet of the polycrystalline material; and performing a planarization process on the polycrystalline material layer after selectively adsorbing the material molecules, wherein the planarization process removes the polycrystalline material at the first facet at a first removal rate and at the second facet at a second removal rate, wherein the material molecules on the first facet cause a reduction in the difference between the first removal rate and the second removal rate.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed.

[0004] Recently, vertically stacked transistor devices, such as complementary field-effect transistors (CFETs), have offered a promising new structure, achieving higher bulk density by vertically stacking nanostructured CFETs above a substrate. Further research and improvement of various aspects of this new structure are needed to achieve better device performance. Summary of the Invention

[0005] none Simple Explanation of the Diagram

[0006] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates an example of a nanostructure field-effect transistor (NSFET) device in a three-dimensional view according to some embodiments. Figures 2, 3A, 3B, 4A, 4B, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, and 12B illustrate cross-sectional views of a complementary field-effect transistor (CFET) device according to an embodiment at different manufacturing stages. Figures 13A and 13B illustrate cross-sectional views of a CFET device according to another embodiment. Figure 14 illustrates an enlarged view of a portion of the polycrystalline material in one embodiment. Figures 15, 16, and 17 illustrate various embodiments of methods for planarizing polycrystalline materials using facet-dependent adsorption in some examples. Figure 18 illustrates a flowchart of a method for forming a semiconductor device according to some embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or instances of various features for implementing at least one implementation of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly. Throughout this discussion, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed using the same or similar materials(s) by the same or similar forming processes. Furthermore, figures with the same numerals but different letters (e.g., Figures 5A to 5C) illustrate different views of the same device at the same stage of processing.

[0009] Various embodiments of this disclosure are discussed in the context of forming complementary field-effect transistor (CFET) devices, and it is understood that the disclosed planarization method using facet-dependent adsorption can be applied to other types of semiconductor devices, such as fin field-effect transistor (FinFET) devices, nanostructure field-effect transistor (NSFET) devices (e.g., nanowire devices, nanosheet devices), planar devices, or the like. Furthermore, as a non-limiting example, the disclosed planarization method is used to planarize polycrystalline material at bonding interfaces, but it should be understood that the disclosed planarization method can be used to planarize polycrystalline material at other locations within a semiconductor device.

[0010] In some embodiments, a polycrystalline material with high thermal conductivity is used as the bonding material at the interface between two semiconductor devices to improve heat dissipation efficiency. To overcome the difficulties encountered in planarizing polycrystalline materials during chemical mechanical planarization (CMP) processes, removal rate modification layers are selectively formed on certain facets of the polycrystalline material using facet-dependent adsorption. During the CMP process of planarizing the surface of the polycrystalline material, the removal rate modification layers increase the removal rate of the polycrystalline material at hard facets or decrease the removal rate of the polycrystalline material at soft facets. By reducing the difference in removal rates between soft and hard facets, the removal rate modification layers allow the CMP process to successfully achieve improved planarity at the surface of the polycrystalline material.

[0011] Figure 1 illustrates an example of a nanostructure field-effect transistor (NSFET) device 30 in a three-dimensional view according to some embodiments. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed above the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed above the semiconductor fin 90 and between the source / drain regions 112. Shallow trench isolation regions 96 are formed on opposite sides of the semiconductor fin 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrode 122 is above and around the gate dielectric layer 120.

[0012] Figure 1 further illustrates the reference cross sections used in subsequent figures. Cross section AA is along the longitudinal axis of the semiconductor fin 90 and, for example, in the direction of current flow between the source / drain regions 112 of the NSFET device. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the gate electrode 122. Cross section CC is parallel to cross section BB and extends through the source / drain regions 112 of the NSFET device. For clarity, these reference cross sections may be referenced in subsequent figures.

[0013] Figures 2, 3A, 3B, 4A, 4B, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, and 12B illustrate cross-sectional views of the complementary field-effect transistor (CFET) device 300 according to the embodiment at different manufacturing stages. Specifically, in one embodiment, Figures 2, 3A, 3B, 4A, 4B, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 11A, and 11B illustrate cross-sectional views of the NSFET device 100 at various processing stages. The NSFET device 100 is then coupled to another NSFET device 200 to form a CFET device 300, as shown in the cross-sectional views of Figures 13A and 13B.

[0014] In Figure 2, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 includes silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0015] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. In Figure 2, the layers formed by the first semiconductor material 52 are labeled as first semiconductor material layer 52A, first semiconductor material layer 52B, and first semiconductor material layer 52C, and the layers formed by the second semiconductor material 54 are labeled as second semiconductor material layer 54A, second semiconductor material layer 54B, and second semiconductor material layer 54C. The number of layers formed by the first and second semiconductor materials shown in Figure 2 is merely a non-limiting example. Other numbers of layers are also possible and are fully intended to be included within the scope of this disclosure.

[0016] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming the channel region of a p-type FET, such as silicon germanium (SixGe1-x, where x can be in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming the channel region of an n-type FET, such as silicon. In some embodiments, the second semiconductor material 54 (e.g., silicon) can be used to form an n-type or p-type FET, and the first semiconductor material 52 is used as a sacrificial material to be removed later. The multilayer stack 64 (also referred to as an epitaxial material stack) will be patterned to form the channel region of the NSFET in subsequent processing. For example, the multilayer stack 64 may be patterned and etched to form nanostructures (e.g., nanosheets or nanowires), wherein the channel region of the resulting NSFET comprises nanostructures vertically stacked above the fins, and each nanostructure extends parallel to the main upper surface of the substrate.

[0017] The multilayer stack 64 can be formed by an epitaxial growth process performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is periodically exposed to a first set of precursors for selectively growing a first semiconductor material 52, and then to a second set of precursors for selectively growing a second semiconductor material 54. The first set of precursors includes precursors for the first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes precursors for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes silicon precursors (e.g., silane) and germanium precursors (e.g., germanane), and the second set of precursors includes silicon precursors but omits the germanium precursor. Thus, the epitaxial growth process may include continuously enabling silicon precursor flow to the growth chamber, and then cyclically: (1) enabling germanium precursor flow to the growth chamber during the growth of the first semiconductor material 52; and (2) inhibiting germanium precursor flow to the growth chamber during the growth of the second semiconductor material 54. This cycle of exposure can be repeated until the target number of layers are formed.

[0018] Figures 3A, 3B, 4A, 4B, 5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 11A, and 11B illustrate cross-sectional views of the NSFET device 100 according to an embodiment at a subsequent manufacturing stage. Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A are cross-sectional views along cross-section AA in Figure 1. Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, and 11B are cross-sectional views along cross-section BB in Figure 1. Figures 5C, 6C, and 7C are cross-sectional views along cross section CC in Figure 1. The number of fins and gate structures shown in these figures are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures may also be formed.

[0019] In Figures 3A and 3B, the fin structure 91 is formed to protrude above the substrate 50. Each component of the fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a layer stack 92 covering the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0020] The fin structure 91 can be patterned using any suitable method. For example, the fin structure 91 can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. In an embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers are used to pattern, for example, the fin structure 91.

[0021] In some embodiments, the remaining spacers are used to pattern mask 94, which is then used to pattern fin structure 91. Mask 94 may be a single-layer mask or a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to suitable techniques. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A may be silicon oxide, and the second mask layer 94B may be silicon nitride. Mask 94 may be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. Mask 94 may then be used as an etching mask to etch substrate 50 and multilayer stack 64. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. In some embodiments, etching is an anisotropic etching process. After the etching process, a layer stack 92 is formed by patterning a multilayer stack 64, and the patterned portion of the substrate 50 forms semiconductor fins 90, as shown in Figures 3A and 3B. The unetched lower portion of the substrate 50 is referred to as substrate 50 in Figures 3A and 3B (and subsequent figures). Thus, in the illustrated embodiment, the layer stack 92 also includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54, and the semiconductor fins 90 are formed of the same material as the substrate 50 (e.g., silicon).

[0022] The semiconductor fin 90 and layer stack 92 in Figure 3B are illustrated as having substantially vertical sidewalls (e.g., perpendicular to the main upper surface of substrate 50). The shape of the semiconductor fin 90 and layer stack 92 shown in Figure 3B is merely a non-limiting example. The semiconductor fin 90 and layer stack 92 may have sloping sidewalls (e.g., having a trapezoidal cross-section). Sloping sidewalls can be formed due to the nature of the anisotropic etching process used to form the semiconductor fin 90 and layer stack 92. For example, the etching capability of the anisotropic etching process may decrease along the downward vertical direction in Figure 3B, which may result in sloping sidewalls for the semiconductor fin 90 and layer stack 92.

[0023] Next, in Figures 4A and 4B, shallow trench isolation (STI) regions 96 are formed above the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material may be formed above the substrate 50. The insulating material may be an oxide, nitride, or similar compound of silicon oxide, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material, such as an oxide), the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process may be performed after the formation of the insulating material.

[0024] In some embodiments, an insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surface of the substrate 50 and the fin structure 91, and a filler material, such as those described above, is formed over the liner. In some embodiments, the liner is omitted.

[0025] Next, a removal process is performed on the insulating material to remove excess insulating material above the fin structure 91. In the illustrated embodiment, the removal process also removes the mask 94. In some embodiments, a planarization process such as chemical mechanical planarization (CMP), etch-back, a combination thereof, or similar can be used. The planarization process exposes the layer stack 92 such that the top surface of the layer stack 92 is flush with the insulating material after the planarization process is completed. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed such that the layer stack 92 protrudes between adjacent STI regions 96. The top portion of the semiconductor fin 90 may also protrude between adjacent STI regions 96. Further, the top surface of the STI region 96 may have a flat surface, a convex surface, a concave surface (such as a dish), or a combination thereof, as shown. The top surface of the STI region 96 may be formed as flat, convex, and / or concave by appropriate etching. An acceptable etching process can be used to recess the STI region 96, such as an etching process that is selective for the insulating material (e.g., etching the insulating material at a faster rate than etching other materials, such as the semiconductor fins 90 and the stacked layers 92). For example, a chemical oxide can be used with a suitable etchant, such as dilute hydrofluoric acid (dHF), for removal.

[0026] Next, in Figures 5A to 5C, a dummy dielectric layer 97 is formed over the layer stack 92 and the STI region 96. The dummy dielectric layer 97 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques.

[0027] Next, a dummy gate 102 is formed above the fin structure 91. To form the dummy gate 102, a dummy gate layer can be formed above the dummy dielectric layer 97. The dummy gate layer can be deposited above the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be a conductive material and can be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), or the like. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials having high etch selectivity with the STI region 96.

[0028] Next, a mask 104 is formed over the dummy gate layer. The mask 104 may be formed of silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be patterned using acceptable optical lithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using an acceptable etching technique to form a dummy gate 102, and then transferred to a dummy dielectric layer using an acceptable etching technique to form a dummy dielectric layer 97. The dummy gate 102 covers the individual channel regions of the stack 92. The pattern of the mask 104 can be used to separate each of the dummy gates 102 from adjacent dummy gate entities. The dummy gate 102 may also have a length direction substantially perpendicular to the length direction of the fin structure 91. The dummy gate 102 and the dummy dielectric layer 97 are collectively referred to as the dummy gate structure 101. In some embodiments, the dummy dielectric layer 97 may also be referred to as the dummy gate dielectric.

[0029] Next, an insulating material is conformally deposited over the layer stack 92, the STI region 96, and the dummy gate 102 to form a gate spacer layer 108. The insulating material may be silicon nitride, silicon carbonitride, combinations thereof, or the like. In some embodiments, the gate spacer layer 108 includes a plurality of sublayers. For example, a first sublayer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.

[0030] Figures 5B and 5C illustrate cross-sectional views of the NSFET device 100 in Figure 5A along cross sections EE and FF, respectively. Cross sections EE and FF correspond to cross sections BB and CC in Figure 1, respectively. Unless otherwise stated, subsequent figures with the letters A, B, and C (e.g., Figures 6A, 6B, and 6C) illustrate cross-sectional views along the same cross sections as Figures 5A, 5B, and 5C, respectively.

[0031] Next, in Figures 6A to 6C, the gate spacer layer 108 is etched using an anisotropic etching process to form a gate spacer. The anisotropic etching process can remove the horizontal portion of the gate spacer layer 108 (e.g., the STI region 96 and the portion above the dummy gate structure 101), wherein the remaining vertical portion of the gate spacer layer 108 (e.g., the portion along the sidewall of the dummy gate structure 101) forms the gate spacer. In some embodiments, the gate spacer layer 108 may also be interchangeably referred to as the gate spacer.

[0032] After forming the gate spacer layer 108, the implantation of lightly doped source / drain (LDD) regions (not shown) can be performed. An appropriate type of impurity (e.g., p-type or n-type) can be implanted into the exposed layer stack 92 and / or the semiconductor fins 90. The n-type impurity can be any suitable n-type impurity, such as phosphorus, arsenic, antimony, or the like, and the p-type impurity can be any suitable p-type impurity, such as boron, BF2, indium, or the like. The lightly doped source / drain region can have an impurity concentration between approximately 1E15 / cm³ and approximately 1E16 / cm³. An annealing process can be used to activate the implanted impurities.

[0033] Next, an opening 110 (which may also be referred to as a groove or source / drain opening) is formed in the layer stack 92. The opening 110 may extend through the layer stack 92 and into the semiconductor fin 90. The opening 110 may be formed by an anisotropic etching process using, for example, a dummy gate structure 101 and a gate spacer layer 108 as an etching mask.

[0034] After forming the opening 110, a selective etching process is performed to recess the end portion of the first semiconductor material 52 exposed by the opening 110, without substantially attacking the second semiconductor material 54. After the selective etching process, a groove (also called a sidewall groove) is formed in the first semiconductor material 52 at the location where the removed end portion was previously located.

[0035] Next, an internal spacer layer is formed in the opening 110 (e.g., conformally) to line the sidewalls and bottom of the opening 110. The internal spacer layer also fills the sidewall recesses of the first semiconductor material 52 formed by the previous selective etching process. The internal spacer layer may be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, and may be formed by a suitable deposition method, such as PVD, CVD, atomic layer deposition (ALD), or the like. Next, an etching process, such as anisotropic etching, is performed to remove the portion of the internal spacer layer disposed outside the sidewall recesses of the first semiconductor material 52. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the sidewall recesses of the first semiconductor material 52) forms the internal spacer 55. As shown in Figure 6A, the opening 110 exposes the sidewalls of the second semiconductor material 54 and exposes the upper surface 90U of the semiconductor fin 90 at the bottom of the opening 110.

[0036] In the example of Figure 6C, the portion of the gate spacer 108 disposed on the upper surface of the STI region 96 between adjacent semiconductor fins 90 is completely removed by an anisotropic etching process used to form the gate spacer layer 108. The remaining portion of the gate spacer layer 108 forms fin spacers 108F along the sidewalls of the semiconductor fins 90. In Figure 6C, as a non-limiting example, the upper surface of the STI region 96 between adjacent semiconductor fins 90 is illustrated as a flat surface. For example, due to the anisotropic etching process that removes the upper portion of the STI region 96, the upper surface of the STI region 96 between adjacent semiconductor fins 90 may be curved (e.g., concave).

[0037] Next, in Figures 7A through 7C, a source / drain region 112 is formed in the opening 110. In the discussion herein, the term "source / drain region" may refer individually or collectively to a source or drain, depending on the context. In the illustrated embodiment, the source / drain region 112 is formed of epitaxial material(s), and therefore may also be referred to as an epitaxial source / drain region 112. In some embodiments, the epitaxial source / drain region 112 is formed in the opening 110 to apply stress to individual channel regions of the formed NSFET device, thereby improving performance. In some embodiments, the epitaxial source / drain region 112 is formed such that a dummy gate 102 is disposed between individual adjacent pairs of epitaxial source / drain regions 112. In some embodiments, a gate spacer layer 108 is used to separate the epitaxial source / drain region 112 from the dummy gate 102 by an appropriate lateral distance, such that the epitaxial source / drain region 112 does not short-circuit the subsequently formed replacement gate structure of the resulting NSFET device.

[0038] In some embodiments, the epitaxial source / drain region 112 is epitaxially grown in the opening 110. The epitaxial source / drain region 112 may comprise any acceptable material, such as a material suitable for an n-type or p-type device. For example, when forming an n-type device, the epitaxial source / drain region 112 may comprise a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, or the like. Similarly, when forming a p-type device, the epitaxial source / drain region 112 may comprise a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source / drain region 112 may have a surface protruding from an individual surface of the semiconductor fin 90 and may have a facet.

[0039] The epitaxial source / drain regions 112 and / or semiconductor fins 90 may be implanted with dopants (e.g., n-type or p-type impurities), similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have an impurity concentration (also referred to as dopant concentration) between approximately 1E19 / cm3 and approximately 1E21 / cm3. The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 112 may be in-situ doped during growth.

[0040] As a result of the epitaxial process used to form the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 112 has small facets that extend laterally outward beyond the sidewalls of the semiconductor fins 90. In the illustrated embodiment, adjacent epitaxial source / drain regions 112 remain separate after the epitaxial process is completed (see Figure 7C). In other embodiments, these small facets cause adjacent epitaxial source / drain regions 112 to merge together.

[0041] Next, a contact etch stop layer (CESL) 116 is formed over the source / drain region 112 and the dummy gate structure 101 (e.g., conformally). Then, a first inter-layer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114 and can be formed from silicon nitride using PECVD, although other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, or the like can also be used, as well as alternative techniques for forming the CESL 116 such as low-pressure CVD (LPCVD), PVD, or the like.

[0042] The first ILD 114 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. The dielectric material used for the first ILD 114 may include silicon oxide, silicon phosphate glass (PSG), borosilicate glass (BSG), borosilicate silica glass (BPSG), silica-free glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0043] Next, in Figures 8A and 8B, the dummy gate 102 and the dummy dielectric layer 97 are removed. Note that, for simplicity, the cross-sectional view along the cross section FF shown in Figure 5A is not illustrated in the following processing steps, because such a cross-sectional view is the same as or similar to Figure 7C, or can be easily modified from Figure 7C (e.g., by adding an additional layer formed above the first ILD 114).

[0044] To remove the dummy gate 102, a planarization process such as CMP is performed to make the top surfaces of the first ILD 114 and CESL 116 flush with the top surfaces of the dummy gate 102 and the gate spacer layer 108. The planarization process also removes the mask 104 (see Figure 7A) on the dummy gate 102 and a portion of the gate spacer layer 108 along the sidewalls of the mask 104. After the planarization process, the top surfaces of the dummy gate 102, the gate spacer layer 108, the CESL 116, and the first ILD 114 are flush. Therefore, the top surface of the dummy gate 102 is exposed via the first ILD 114.

[0045] Next, the dummy gate 102 is removed in (multiple) etching steps, thereby forming a recess 103 (also referred to as a gate trench). In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (multiple) reactive gases that selectively etch the dummy gate 102 without etching the first ILD 114 or the gate spacer layer 108. During the removal of the dummy gate 102, the dummy dielectric layer 97 may be used as an etch stop layer while the dummy gate 102 is being etched. The dummy dielectric layer 97 may then be removed after the removal of the dummy gate 102. An etching process, such as an isotropic etching process, may be performed to remove the dummy dielectric layer 97. As shown in Figures 8A and 8B, the recess 103 exposes a channel region of the NSFET device 100. The channel region is located between adjacent epitaxial source / drain regions 112.

[0046] Next, the first semiconductor material 52 (e.g., the portion exposed by the recess 103) is removed to release the second semiconductor material 54. After the removal of the first semiconductor material 52, the second semiconductor material 54 (e.g., the portion of the dummy gate 102 that lies beneath it before removal) forms a plurality of nanostructures 54. The nanostructures 54 may be collectively referred to as the channel region 93 (or channel layer) of the formed NSFET device 100. As shown in Figures 8A and 8B, gaps 53 (e.g., voids) are formed between the nanostructures 54 by removing the first semiconductor material 52. In some embodiments, the nanostructures 54 are nanosheets or nanowires, depending on, for example, the dimensions (e.g., size and / or aspect ratio) of the nanostructures 54.

[0047] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to the first semiconductor material 52 (e.g., has a higher etching rate), such that the first semiconductor material 52 is removed without substantially damaging the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process is performed using an etching gas and optionally a carrier gas. In some embodiments, the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, or the like. In some embodiments, the first semiconductor material 52 may also be referred to as a first nanostructure, and the second semiconductor material 54 may also be referred to as a second nanostructure.

[0048] Next, in Figures 9A and 9B, a gate dielectric layer 120 and a gate electrode 122 are formed in the recess 103 to form an alternative gate structure 123. The gate dielectric layer 120 is conformally deposited in the recess 103, such as on the top surface and sidewalls of the semiconductor fin 90, and on the sidewalls of the gate spacer layer 108. The gate dielectric layer 120 may also be formed on the top surface of the first ILD 114. It should be noted that the gate dielectric layer 120 is formed to cover the nanostructure 54. According to some embodiments, the gate dielectric layer 120 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 120 is formed of a high-k dielectric material, in which the gate dielectric layer 120 may have a dielectric constant (also referred to as a K value) greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. The gate dielectric layer 120 may be formed by methods such as molecular-beam deposition (MBD), ALD, PECVD, and similar methods.

[0049] Next, a gate electrode 122 is deposited above and around the gate dielectric layer 120, and the remaining portion of the recess 103 is filled. The gate electrode 122 may include a metallic material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 122 is illustrated, the gate electrode 122 may include any number of liner layers (e.g., barrier layers), any number of work function tuning layers, and filler material (e.g., filler metal, conductive material). After the gate electrode 122 is formed, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 120 and the gate electrode 122 above the top surface of the first ILD 114. The gate electrode 122 and the remaining portion of the gate dielectric layer 120 thus form the gate electrode 122 and the gate dielectric layer 120 of the replacement gate structure 123 of the resulting NSFET device 100, respectively. Each gate electrode 122 and its corresponding gate dielectric layer 120 can be collectively referred to as a gate stack, a replacement gate structure, a metal gate structure, or a gate structure. Each replacement gate structure 123 extends around an individual nanostructure 54.

[0050] Next, in Figures 10A and 10B, a gate mask 138 is formed over the replacement gate structure 123. The formation process of the gate mask 138 may include recessing the replacement gate structure 123, filling the resulting groove with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and performing a planarization process to remove excess dielectric material over the first ILD 114. The remaining portion of the dielectric material forms the gate mask 138.

[0051] Next, source / drain contact socket 119 and gate contact socket 118 are formed to electrically couple to source / drain region 112 and replacement gate structure 123, respectively. In the illustrated embodiment, source / drain contact socket 119 and gate contact socket 118 are formed in a self-aligned manner and fill the space between opposite sidewalls of CESL 116 and the space between opposite sidewalls of gate spacer layer 108, respectively.

[0052] In some embodiments, one or more anisotropic etching processes are performed to remove portions of the first ILD 114 and the portion of the CESL 116 disposed above the source / drain region 112 to form a source / drain contact opening and expose the source / drain region 112. Similarly, one or more anisotropic etching processes may be performed to remove the gate mask 138 to form a gate contact opening that exposes the replacement gate structure 123.

[0053] Source / drain contact sockets 119 and gate contact sockets 118 can be formed by filling the source / drain contact openings and gate contact openings with (multiple) conductive materials (such as tungsten), although other suitable materials such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys of these materials, combinations thereof, or the like can also be used. A planarization process such as CMP can be performed to remove excess portions of the conductive material disposed outside the source / drain contact openings and gate contact openings. As will be readily understood by those skilled in the art, the number and location of the source / drain contact sockets 119 and gate contact sockets 118 shown in the figures are illustrative and not limiting.

[0054] In the illustrated embodiment, a silicate region 99 is formed on the source / drain region 112 before filling the source / drain contact opening to form the source / drain contact socket 119. In some embodiments, the silicate region 99 is formed by depositing a metal (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with a semiconductor material (e.g., silicon, germanium) to form a silicate or germanide region over the source / drain region 112, followed by performing a thermal annealing process to form the silicate region 99. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicate region 99 is referred to as a silicate region, it can also be a germanide region or a germanide-siliconized region (e.g., a region containing both silicate and germanide).

[0055] Next, an etch stop layer (ESL) 134 and a second ILD 135 are sequentially formed over, for example, the first ILD 114, the replacement gate structure 123, and the gate spacer layer 108. The ESL 134 may comprise a dielectric material with high etch selectivity for etching the second ILD 135, such as aluminum oxide, aluminum nitride, silicon carbide, or the like, and may be formed using CVD, ALD, or the like. The second ILD 135 may be formed from PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, flowable CVD, PECVD, or the like.

[0056] Next, a via 131 is formed to extend through the second ILD 135 and ESL 134 and electrically coupled to the source / drain contact socket 119 and the gate contact socket 118. The via 131 can be formed by forming a via opening extending through the second ILD 135 and ESL 134, followed by filling the via opening with a plurality of conductive materials. The plurality of conductive materials can be the same as or similar to the conductive materials used for the source / drain contact socket 119 or the gate contact socket 118, and therefore details will not be repeated. In some embodiments, a liner layer (e.g., a diffusion barrier layer) can be formed along the sidewalls of the via opening before the plurality of conductive materials fill the via opening. The liner layer can be titanium, tantalum, titanium nitride, tantalum nitride, or the like, and can be formed using any suitable formation method, such as CVD, ALD, or the like.

[0057] In Figures 10A and 10B, the layer of the NSFET device 100 disposed between the upper portion of the semiconductor fin 90 and the second ILD 135 is collectively referred to as the device layer 142 of the NSFET device 100.

[0058] Referring again to Figures 10A and 10B, a front interconnect structure 130 is next formed on device layer 142. The front interconnect structure 130 includes a dielectric layer 136 and a layer of conductive features 132 within the dielectric layer 136. The dielectric layer 136 may include suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectric materials, combinations thereof, or the like, and may be formed by any suitable formation method, such as CVD, PECVD, ALD, combinations thereof, or the like. The conductive features 132 (e.g., conductive characteristics) may include metal wires and vias, which may be formed using, for example, a damascene process. The conductive features 132 may include a diffusion barrier layer and a metallic material (e.g., copper) above the diffusion barrier layer. The diffusion barrier layer (also referred to as a liner layer) may be, for example, Ta, Ti, TaN, TiN, or the like. The metallic material may be, for example, Cu, Co, Ru, Mo, or the like. In some embodiments, the topmost conductive feature 132 (e.g., the conductive feature 132 in the topmost dielectric layer 136T away from the device layer 142) may include a conductive feature 132P for bonding with another semiconductor device (e.g., a bonding pad or metal pattern for bonding). Therefore, the conductive feature 132P may also be referred to as a bonding feature or bonding structure.

[0059] In the illustrated embodiment, the topmost dielectric layer 136T (also referred to as the outermost dielectric layer) of the front interconnect structure 130 is made of a material with high thermal conductivity (e.g., having a thermal conductivity higher than approximately...). The top dielectric layer 136T is formed of a polycrystalline material (with good thermal conductivity). Examples of polycrystalline materials used for the top dielectric layer 136T include carbon, ceramics, and composite materials with polycrystalline structures, such as aluminum nitride, silicon carbide, beryllium oxide, metal nitrides, and metal oxides. Examples of metallic materials in metal nitrides or metal oxides include aluminum, titanium, and tantalum. In some embodiments, other dielectric layers 136 of the front interconnect structure 130 are formed of a dielectric material different from the top dielectric layer 136T (e.g., a non-polycrystalline dielectric material, such as silicon oxide).

[0060] Polycrystalline materials with high thermal conductivity can be advantageously used as bonding materials at the bonding interfaces of semiconductor devices to improve heat dissipation efficiency. Furthermore, polycrystalline materials can also be used as heat dissipation devices or heat sinks in semiconductor devices. The surface of deposited polycrystalline materials is typically not flat; in some embodiments, planarization processes such as CMP are typically performed to planarize the surface of the deposited polycrystalline material. Figure 14 illustrates the surface of a polycrystalline material, and Figures 15 through 17 illustrate various example methods used for planarizing polycrystalline materials.

[0061] Referring to Figure 14, which illustrates an enlarged view of a portion 160 of the top dielectric layer 136T in Figure 10A. The upper surface of the top dielectric layer 136T (which is a polycrystalline material) in Figure 14 corresponds to the upper surface of the top dielectric layer 136T in Figure 10A that is away from the device layer 142. For ease of discussion, the top dielectric layer 136T may also be interchangeably referred to herein as a polycrystalline material.

[0062] As shown in Figure 14, the surface above the top dielectric layer 136T has different facets extending along different crystal planes, such as facets along the (111) direction and along the (100) direction. For ease of discussion, the facet along the (111) direction can also be called facet (111), and the facet along the (100) direction can also be called facet (100). In the example in Figure 14, the top horizontal facet of the top dielectric layer 136T is facet (111), and the tilted facet is facet (100). The facets along different crystal planes have different lattice densities, which results in different hardnesses of the facets. The different hardnesses, in turn, result in different removal rates of the top dielectric layer 136T at different facets during subsequent planarization processes (e.g., CMP). Generally, the removal rate of hard facets (e.g., those with higher lattice densities) is lower than that of soft facets (e.g., those with lower lattice densities). In the example of Figure 14, facet (111) is harder than facet (100), so facet (111) can also be called a hard facet, and facet (100) can also be called a soft facet. Therefore, if a CMP process is performed to planarize the top dielectric layer 136T in Figure 14, the polycrystalline material at the hard facet (e.g., facet (111)) is removed at a first removal rate, and the polycrystalline material at the soft facet (e.g., facet (100)) is removed at a second removal rate higher than the first removal rate. In the discussion herein, the removal rate of polycrystalline material at the facet (e.g., facet (111)) (e.g., the first removal rate) refers to the rate at which the facet is recessed along a direction perpendicular to the facet (e.g., the vertical direction in Figure 14) during the CMP process.

[0063] In the example of Figure 14, the slower removal rate of the polycrystalline material at the facet (111) (or equivalently, the faster removal rate of the polycrystalline material at the facet (100)) poses a challenge to the CMP process. For example, if the facet (100) is removed at a faster removal rate than the facet (111) during the CMP process, the peaks and valleys on the surface of the top dielectric layer 136T may become more prominent after the CMP process, thus failing to meet the purpose of the CMP process. Therefore, if the facets (111) and (100) are left untreated, the CMP process may not be able to successfully improve the planarity of the surface of the top dielectric layer 136T. This paper describes various methods for treating different facets of the top dielectric layer 136T with reference to Figures 15 through 17 to achieve improved planarity of the surface of the top dielectric layer 136T after the CMP process.

[0064] Figure 15 illustrates a method in which a removal rate modification layer 161 (also referred to as a surface modification layer or etch rate modification layer) is selectively formed on a soft facet (e.g., facet (100)) to reduce the removal rate of the polycrystalline material at the soft facet. The upper left of Figure 15 illustrates a portion of the topmost dielectric layer 136T before the formation of the removal rate modification layer. Next, as shown in the middle portion of Figure 15, molecules of a suitable chemical for the removal rate modification layer 161 are selectively adsorbed onto the facet (100) to form the removal rate modification layer 161 (e.g., one or more layers of the removal rate modification layer 161).

[0065] In some embodiments, different facets of the polycrystalline material possess different physical and / or chemical properties, such as varying surface reactivity, hydroxyl density, hydrophilicity, and coulombic interactions. These different physical or chemical properties may interact differently with the molecules of certain chemicals, thereby allowing molecules to selectively adsorb onto certain facets of the polycrystalline material. Examples of chemicals whose molecules can selectively adsorb onto the facets of the polycrystalline material include silanes, carbonic acid, phosphates, carbonates, sulfonates, amines, and amides. In some embodiments, chemicals are added to the CMP slurry used in the CMP process to facilitate the selective adsorption of molecules 161 of the removal rate modification layer onto the facets of the polycrystalline material. In other embodiments, chemicals are applied to the surface of the polycrystalline material prior to performing the CMP process to facilitate the selective adsorption of molecules 161 of the removal rate modification layer.

[0066] As shown on the right side of Figure 15, during the CMP process, the removal rate modification layer 161 covers the facet (100) and acts as a barrier layer for the CMP process, thereby reducing the removal rate of the top dielectric layer 136T at the facet (100). The CMP process can eventually remove a portion of the removal rate modification layer. After the CMP process is completed, the remaining portion of the removal rate modification layer 161 is removed by a suitable method (such as wet etching or dry etching). The dashed lines in Figure 15 illustrate the recessed facet of the polycrystalline material after the CMP process is completed. In the example of Figure 15, because the removal rate modification layer 161 protects the soft facet (e.g., facet (100)), after the CMP process is completed, the facet (100) is less recessed than the hard facet (e.g., facet (111)), thereby reducing the vertical offset between peaks and valleys on the surface of the top dielectric layer 136T and improving the planarity of the surface of the top dielectric layer 136T.

[0067] Figure 16 illustrates a method in which a removal rate modification layer 163 is selectively formed on a hard facet (e.g., facet (111)) to improve the removal rate of the polycrystalline material at the hard facet. The upper left of Figure 16 illustrates a portion of the top dielectric layer 136T before the formation of the removal rate modification layer. Next, as shown in the middle portion of Figure 16, molecules 163 of the removal rate modification layer, suitable for chemicals, are selectively adsorbed onto the facet (111) to form the removal rate modification layer 163 (e.g., one or more layers of molecules 163 of the removal rate modification layer). The chemicals may be added to a CMP slurry to selectively adsorb the molecules 163 of the removal rate modification layer, or they may be applied to the surface of the top dielectric layer 136T prior to performing the CMP process to selectively adsorb the molecules 163 of the removal rate modification layer.

[0068] In some embodiments, the CMP slurry (also referred to as the slurry) and the abrasive particles 165 contained in the top dielectric layer 136T carry the same type of charge (e.g., the same positive charge or the same negative charge), while the molecules 163 of the removal rate modification layer carry a different (e.g., opposite) type of charge. The charged molecules 163 of the removal rate modification layer can also be referred to as ions. Due to the attraction between opposite types of charges, the selectively adsorbed molecules 163 of the removal rate modification layer on the facet (111) enhance the interaction between the abrasive particles 165 in the CMP slurry and the facet (111), thereby increasing the removal rate of the polycrystalline material at the facet (111), as shown on the right side of Figure 16. In this embodiment, the abrasive particles 165 in the CMP slurry are negatively charged diamond abrasive particles, the top dielectric layer 136T is a negatively charged diamond film, and the molecules 163 of the removal rate modification layer are positively charged cations, such as bis-cations of arginine. As another example, both the abrasive particles 165 and the top dielectric layer 136T carry positive charges, while the molecules 163 of the removal rate modification layer are negatively charged anions.

[0069] In some embodiments, molecule 163 of the removal rate modification layer is a bis-ion having two negative charges (e.g., a net charge of -2). In some embodiments, molecule 163 of the removal rate modification layer is a bis-positive ion having two positive charges (e.g., a net charge of +2). Besides arginine, bivalent chemicals that can be used to form the removal rate modification layer in Figure 16 include polyacrylic acid, polyethyleneimine, hexadecyltrimethylammonium bromide, lauryl betaine, cocamidopropyl betaine, polyamide-amine dendrimers, chitosan, and sodium dodecyl sulfate.

[0070] In some embodiments, the molecule 163 of the removal rate modification layer has three negative charges (e.g., a net charge of -3) and may be provided by a chemical having a tricarboxylic acid group, such as citric acid, aconitic acid, tricarboxylic acid, or 1,2,3-propanetricarboxylic acid. In some embodiments, the molecule 163 of the removal rate modification layer has three positive charges (e.g., a net charge of +3) and may be provided by a chemical having a triamine group, such as diethylenetriamine, triethylenetetramine, or bis(hexamethylene)triamine.

[0071] Arrow 167 in Figure 16 illustrates the electro-attraction between molecules 163 of the removal rate modification layer and abrasive particles 165, and between molecules 163 of the removal rate modification layer and the facet (111) of the top dielectric layer 136T. The dashed line in Figure 16 illustrates the recessed facet of the top dielectric layer 136T after the CMP process is completed. After the CMP process is completed, the remaining portion of the removal rate modification layer 163 is removed by a suitable method (such as wet etching or dry etching). In the example of Figure 16, because the removal rate modification layer 163 increases (e.g., increases) the removal rate of the polycrystalline material at the facet (111), the facet (111) is more recessed than the facet (100) after the CMP process is completed, thereby reducing the vertical offset between peaks and valleys on the surface of the top dielectric layer 136T and improving the planarity of the surface of the top dielectric layer 136T.

[0072] Note that in the example of Figure 15, the removal rate modification layer 161 (e.g., one or more molecules of the removal rate modification layer 161) reduces the removal rate of the polycrystalline material at soft facets (e.g., facets (100)), which have a faster removal rate than hard facets (e.g., facets (111)). In the example of Figure 16, the removal rate modification layer 163 (e.g., one or more molecules of the removal rate modification layer 163) increases the removal rate of the polycrystalline material at hard facets (e.g., facets (111)), which have a slower removal rate than soft facets (e.g., facets (100)). Therefore, in some embodiments, the removal rate modification layers 161 and 163 in Figures 15 and 16 can be described as reducing the difference (e.g., the absolute value of the difference) between the removal rate of the polycrystalline material at the soft facet and the removal rate of the polycrystalline material at the hard facet, or compensating for the difference between the removal rate of the polycrystalline material at the soft facet and the removal rate of the polycrystalline material at the hard facet.

[0073] Figure 17 illustrates a method in which a first removal rate modification layer 161 (e.g., one or more molecules 161 of the removal rate modification layer) is formed on a soft facet (e.g., facet (100)) to reduce the removal rate of the polycrystalline material at the soft facet, and a second removal rate modification layer 163 (e.g., one or more molecules 163 of the removal rate modification layer) is formed on a hard facet (e.g., facet (111)) to increase the removal rate of the polycrystalline material at the hard facet. Those skilled in the art will readily understand that the method in Figure 17 is a combination of the methods disclosed in Figures 15 and 16. The details of the molecules 161 and 163 of the removal rate modification layer in Figure 17 and their formation methods are the same as or similar to those described above, and therefore will not be repeated.

[0074] Modifications and variations of the disclosed method are possible and are entirely intended to be included within the scope of this disclosure. For example, in the embodiment of Figure 15, selective adsorption of the removal rate modification layer molecules 161 results in the formation of the removal rate modification layer on the facet (100) and no removal rate modification layer on the facet (111). Of course, this is only a non-limiting example. An embodiment is also contemplated in which the selective adsorption of the removal rate modification layer molecules 161 results in a thicker removal rate modification layer on the facet (100) and a thinner removal rate modification layer on the facet (111), and this embodiment is within the scope of this disclosure. The thicker removal rate modification layer on the facet (100) may include, for example, a layer of more removal rate modification layer molecules 161 than the thinner removal rate modification layer on the facet (111). Similarly, selective adsorption of molecules 163 of the removal rate modification layer can result in a thicker removal rate modification layer on the facet (111) (e.g., more layers of molecules 163 of the removal rate modification layer) and a thinner removal rate modification layer on the facet (100).

[0075] Referring back to Figures 10A and 10B, after planarizing the top dielectric layer 136T, a conductive feature 132P is formed in the top dielectric layer 136T using a suitable formation method (such as damascene). In the illustrated embodiment, the conductive feature 132P is exposed at the outermost surface of the front interconnect structure 130, away from the device layer 142. For example, the top surface 132PU of the conductive feature 132P is flush with (e.g., flush with) the upper surface of the top dielectric layer 136T of the front interconnect structure 130.

[0076] Next, in Figures 11A and 11B, a back-side thinning process is performed, and a back-side interconnect structure 151 is formed on the side of device layer 142 opposite to the front-side interconnect structure 130. Details will be discussed below.

[0077] In some embodiments, a thinning process is performed from the rear side of substrate 50 to thin substrate 50. The thinning process may be a polishing process, a CMP process, an etching process, a combination thereof, or similar. The thinning process may remove substrate 50, STI region 96, and the lower portion of semiconductor fin 90. In some embodiments, the thinning process stops when the source / drain regions 112 are exposed. Next, the remaining portion of semiconductor fin 90 (e.g., the top portion that contacts the conductive features) is removed (e.g., by a selective etching process) to form a recess between, for example, adjacent pairs of source / drain regions 112. ESL 145 is formed as the sidewalls and bottom of the recess. ESL 145 may be formed using the same or similar materials and formation methods as CESL 116, so details are not repeated. Next, dielectric material 143 is formed on ESL 145 and fills the recess. Dielectric material 143 may be, for example, SiO, SiN, or a low-k dielectric material formed using any suitable formation method. Next, a planarization process such as CMP can be performed to achieve a coplanar lower surface between the source / drain region 112, ESL 145, and dielectric material 143. After the formation of ESL 145 and dielectric material 143, the layer of the NSFET device 100 disposed between the second ILD 135 and the lower surface of the source / drain region 112 is collectively referred to as the device layer 142 of the NSFET device.

[0078] Next, a rear-side interconnect structure 151, including a dielectric layer 136 and conductive features 132, is formed on the rear side of device layer 142. The rear-side interconnect structure 151 may include source / drain contact sockets 119 formed in the innermost dielectric layer 136 of the contact dielectric material 143. In the illustrated embodiment, a siliconized region 99 is formed on the lower surface of the source / drain region 112 prior to the formation of the source / drain contact sockets 119. Figures 11A and 11B further illustrate a liner layer 147 (e.g., a diffusion barrier layer) surrounding the source / drain contact sockets 119. The liner layer 147 may be made of suitable materials such as titanium, tantalum, titanium nitride, tantalum nitride, or the like, and may be formed using any suitable formation method such as CVD, ALD, or the like.

[0079] The rear interconnect structure 151 also includes conductive features 132P (e.g., bonding pads) embedded in the topmost dielectric layer 136T remote from the device layer 142. In some embodiments, the topmost dielectric layer 136T of the rear interconnect structure 151 is formed of the same or similar polycrystalline material as the topmost dielectric layer 136 of the front interconnect structure 130. Subsequently, in some embodiments, the topmost dielectric layer 136T of the rear interconnect structure 151 is planarized using a CMP process, and a substantially flat surface is achieved after the CMP process using the same or similar removal rate modification layer as described in Figures 15 through 17 above.

[0080] Next, in Figures 12A and 12B, NSFET device 100 is bonded to NSFET device 200 to form CFET device 300. NSFET device 200 is similar to NSFET device 100 and can be formed using the same or similar formation methods. In some embodiments, the source / drain region 124 of NSFET device 200 has a different conductivity type (e.g., n-type or p-type) than the source / drain region 112 of NSFET device 100. For example, the source / drain region 112 of NSFET device 100 may have a first doping type (e.g., doped with a first conductivity type, such as an n-type dopant), while the source / drain region 124 of NSFET device 200 may have a second doping type (e.g., doped with a second conductivity type, such as a p-type dopant) different from the first doping type. In other words, an n-type NSFET can be used to form one of NSFET devices 100 and 200, and a p-type NSFET can be used to form the other of NSFET devices 100 and 200. In other embodiments, the source / drain region 112 of NSFET device 100 and the source / drain region 124 of NSFET device 200 have the same doping type (e.g., both are doped with n-type or p-type dopants).

[0081] In the examples of Figures 12A and 12B, the front interconnect structure 130 of the NSFET device 200 is bonded to the front interconnect structure 130 of the NSFET device 100 to form the CFET device 300. This bonding scheme is also referred to as front-to-front bonding.

[0082] In Figures 12A and 12B, the top dielectric layer 136T of the front interconnect structure 130 of the NSFET device 100 is bonded to the top dielectric layer 136T of the front interconnect structure 130 of the NSFET device 200 via a dielectric-to-dielectric bonding (also known as a direct dielectric-to-dielectric bonding). The conductive feature 132P of the front interconnect structure 130 of the NSFET device 100 is bonded to the individual conductive feature 132P of the front interconnect structure 130 of the NSFET device 200 via a metal-to-metal bonding (also known as a direct metal-to-metal bonding).

[0083] Dielectric-to-dielectric and metal-to-metal bonding are bonding techniques that can be used in direct bonding processes to join two semiconductor devices together without the use of intermediate layers (e.g., solder or adhesive layers). Direct bonding processes use dielectric-to-dielectric and / or metal-to-metal bonding to achieve a robust and reliable connection at the interface of two devices. Metal-to-metal bonding involves aligning and applying sufficient pressure on metal surfaces (such as copper or aluminum surfaces), often accompanied by heat treatment to promote atomic diffusion and interface adhesion, without the need for an intermediate layer (e.g., solder). Dielectric-to-dielectric bonding uses surfaces such as silicon dioxide or other insulating materials, which, when aligned under appropriate conditions (e.g., at high temperatures and / or under pressure at the surface), form a bond via forces such as van der Waals forces or covalent interactions. Direct bonding processes help produce high-density, low-resistance connections while reducing or minimizing the thermal budget.

[0084] Referring again to Figures 12A and 12B, an optional heat dissipation device 149 (also referred to as a heat sink) is formed on the top dielectric layer 136T of the rear interconnect structure 151 of the NSFET device 200. In some embodiments, the heat dissipation device 149 is a layer of polycrystalline material with high thermal conductivity and can be formed from the same or similar material using the same or similar formation method as the top dielectric layer 136T. In some embodiments, the heat dissipation device 149 is omitted. Similarly, the optional heat dissipation device 149 may be formed on the top dielectric layer 136T of the rear interconnect structure 151 of the NSFET device 100. In some embodiments where the heat dissipation device 149 (e.g., polycrystalline material) is formed, the top dielectric layer 136T of the rear interconnect structure 151 that contacts the heat dissipation device 149 may be formed from the same dielectric material as the other dielectric layers 136 of the rear interconnect structure 151 (e.g., a non-polycrystalline dielectric material, such as silicon oxide). In some embodiments, both the heat dissipation device 149 and the dielectric layer 136T of the contact heat dissipation device 149 are formed of a polycrystalline material with high thermal conductivity.

[0085] In some embodiments, a plurality of NSFET devices 100 are formed on a first wafer (e.g., substrate 50), and a plurality of NSFET devices 200 are formed on a second wafer (e.g., another substrate 50). After the front-side interconnect structures 130 on the two wafers are bonded together, a wafer-to-wafer structure comprising a plurality of CFET devices 300 is formed. Next, a dicing process is performed along the dicing region shown by dashed line 150 in Figures 12A and 12B to separate the wafer-on-wafer structure into individual (e.g., separate) CFET devices 300, each of which includes vertically stacked (e.g., bonded together) NSFET devices 100 and NSFET devices 200. In some embodiments, the NSFET devices 100 and 200 in the CFET devices 300 have different conductivity types. In other embodiments, the NSFET devices 100 and 200 in the CFET devices 300 have the same conductivity type.

[0086] Figures 13A and 13B illustrate cross-sectional views of a CFET device 300A according to another embodiment. The CFET device 300A is similar to the CFET device 300, but the front interconnect structure 130 of the NSFET device 100 is bonded to the rear interconnect structure 151 of the NSFET device 200. This bonding scheme is also referred to as front-to-back bonding. Similar to the CFET device 300, dielectric-to-dielectric bonding and metal-to-metal bonding are used to bond the NSFET device 100 and the NSFET device 200 without using an intermediate layer.

[0087] In the examples of Figures 13A and 13B, an optional heat dissipation device 149 is formed on the top dielectric layer 136T of the front interconnect structure 130 of the NSFET device 200. Similarly, an optional heat dissipation device 149 may be formed on the top dielectric layer 136T of the rear interconnect structure 151 of the NSFET device 100. In some embodiments of forming the optional heat dissipation device 149, the dielectric layer 136T of the contact heat dissipation device 149 may be formed of the same dielectric material (e.g., a non-polycrystalline dielectric material, such as silicon oxide) as the other dielectric layers 136 of the front (or rear) interconnect structure. In some embodiments, both the heat dissipation device 149 and the dielectric layer 136T of the contact heat dissipation device 149 are formed of a polycrystalline material with high thermal conductivity.

[0088] In some embodiments, a granulation process may then be performed along the granulation region indicated by the dashed line 150 in Figures 13A and 13B to separate a plurality of CFET devices 300A formed in a wafer-to-wafer structure into a plurality of individual (e.g., separate) CFET devices 300.

[0089] The disclosed embodiments achieve advantages. For example, by using a polycrystalline material with high thermal conductivity at the interface between two devices, heat dissipation efficiency is improved, achieving enhanced thermal management of advanced devices. The disclosed removal rate modification layer, formed by facet-dependent adsorption, can selectively increase (e.g., enhance) or decrease the polishing efficiency of the CMP process at different facets of the polycrystalline material to achieve improved planarity of the polycrystalline material surface. The disclosed method for facet-dependent adsorption is universal across different types of materials and can be easily integrated into existing process flows for cost-effective implementation.

[0090] Figure 18 illustrates a flowchart of a method 1000 for forming a semiconductor device according to some embodiments. It should be understood that the methods shown in Figure 18 are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, various steps shown in Figure 18 may be added, deleted, replaced, reconfigured, or repeated.

[0091] Referring to Figure 18, at block 1010, a conductive feature is formed above the substrate. At block 1020, a dielectric layer is formed above the conductive feature and the substrate. At block 1030, a layer of polycrystalline material is formed above the dielectric layer, wherein the first facet and the second facet of the polycrystalline material have different lattice densities. At block 1040, molecules of a first material are selectively adsorbed on the first facet of the polycrystalline material. At block 1050, after the selective adsorption of molecules of the first material, a planarization process is performed on the polycrystalline material layer, wherein the planarization process removes the polycrystalline material at the first facet at a first removal rate and at the second facet at a second removal rate, wherein the molecules of the first material on the first facet cause a reduction in the difference between the first removal rate and the second removal rate.

[0092] In an embodiment, a method of forming a semiconductor device includes: forming a device layer over a first substrate, wherein the device layer includes a transistor, wherein the transistor includes fins protruding over the first substrate, a channel region over the fins, a gate structure surrounding the channel region, and source / drain regions over the fins and on opposite sides of the gate structure; and forming an interconnect structure at a first side of the device layer and electrically coupling it to the transistor, wherein the interconnect structure includes a first dielectric layer and conductive features embedded in the first dielectric layer, wherein forming the interconnect structure includes: forming an outermost dielectric layer of the interconnect structure away from the device layer using a polycrystalline material, wherein a first facet and a second facet of the polycrystalline material have different lattice densities; selectively adsorbing molecules of a first material on the first facet of the polycrystalline material; and performing a planarization process on the polycrystalline material after selectively adsorbing molecules of the first material, wherein during the planarization process, molecules of the first material reduce the difference between a first removal rate of the polycrystalline material at the first facet and a second removal rate of the polycrystalline material at the second facet. The method further includes bonding the outermost dielectric layer of the interconnect structure to a second dielectric layer formed over a second substrate after forming the interconnect structure. In an embodiment, the first facet has a higher lattice density than the second facet, wherein during the planarization process, molecules of the first material cause an increase in the first removal rate of the polycrystalline material at the first facet. In an embodiment, the planarization process includes a chemical mechanical planarization (CMP) process performed using a slurry containing abrasive particles, wherein the abrasive particles and the polycrystalline material carry a first type of charge, and wherein the molecules of the first material carry a second type of charge different from the first type of charge. In an embodiment, the abrasive particles and the polycrystalline material carry a positive charge, and the molecules of the first material are anions. In an embodiment, the first facet has a lower lattice density than the second facet, wherein during the planarization process, molecules of the first material cause a decrease in the first removal rate of the polycrystalline material at the first facet. In an embodiment, the molecules of the first material are silane molecules, carbonate molecules, phosphate molecules, carbonate molecules, sulfonate molecules, amine molecules, or amide molecules. In an embodiment, the polycrystalline material has higher thermal conductivity than silicon. In an embodiment, forming the interconnect structure further includes selectively adsorbing molecules of a second material on a second facet of the polycrystalline material. In an embodiment, the first facet has a higher lattice density than the second facet, wherein during the planarization process, molecules of the first material cause a first removal rate increase of the polycrystalline material at the first facet, and wherein during the planarization process, molecules of the second material cause a second removal rate decrease of the polycrystalline material at the second facet. In an embodiment, bonding the outermost dielectric layer includes bonding the outermost dielectric layer of the interconnect structure to the second dielectric layer via dielectric-to-dielectric bonding.

[0093] In an embodiment, a method of forming a semiconductor device includes: forming a device layer over a first substrate, wherein the device layer includes a transistor; forming a first dielectric layer over the first substrate and the transistor; forming a conductive feature in the first dielectric layer, wherein the conductive feature is electrically coupled to the transistor; forming a layer of polycrystalline material over the first dielectric layer, wherein a first facet and a second facet of the polycrystalline material have different lattice densities; selectively forming a removal rate modification layer on the first facet of the polycrystalline material by selectively adsorbing molecules of the first material on the first facet; and performing a planarization process on the polycrystalline material after selectively forming the removal rate modification layer, wherein the planarization process removes the polycrystalline material at a first removal rate at the first facet and at a second removal rate at the second facet, wherein the removal rate modification layer causes a reduction in the difference between the first removal rate and the second removal rate. In an embodiment, the method further includes, after performing the planarization process, bonding the layer of polycrystalline material to the second dielectric layer formed over the second substrate via dielectric-to-dielectric bonding. In one embodiment, the method further includes forming a first bonding feature in the polycrystalline material layer after performing a planarization process and before bonding the polycrystalline material layer, wherein the method further includes bonding the first bonding feature to a second bonding feature embedded in the second dielectric layer via metal-to-metal bonding. In one embodiment, the first facet has a lower lattice density than the second facet, wherein the removal rate modification layer causes a decrease in the first removal rate. In another embodiment, the first facet has a higher lattice density than the second facet, wherein the removal rate modification layer causes an increase in the first removal rate.

[0094] In an embodiment, a method of forming a semiconductor device includes: forming a conductive feature over a substrate; forming a dielectric layer over the conductive feature and the substrate; forming a layer of polycrystalline material over the dielectric layer, wherein a first facet and a second facet of the polycrystalline material have different lattice densities; selectively adsorbing molecules of a first material onto the first facet of the polycrystalline material; and, after selectively adsorbing the molecules of the first material, performing a planarization process on the polycrystalline material layer, wherein the planarization process removes the polycrystalline material at the first facet at a first removal rate and at the second facet at a second removal rate, wherein the molecules of the first material on the first facet cause a reduction in the difference between the first removal rate and the second removal rate. In an embodiment, the first facet has a lower lattice density than the second facet, wherein the molecules of the first material on the first facet cause a decrease in the first removal rate. In an embodiment, the first facet has a higher lattice density than the second facet, wherein the molecules of the first material on the first facet cause an increase in the first removal rate. In one embodiment, the first facet has a lower lattice density than the second facet, and the method further includes selectively adsorbing molecules of a second material onto the second facet of the polycrystalline material, wherein molecules of the first material on the first facet cause a decrease in a first removal rate, and wherein molecules of the second material on the second facet cause an increase in a second removal rate.

[0095] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0096] 30: NSFET device 50:Substrate 52: First Semiconductor Material 52A~52C: First semiconductor material layer 53: Gap 54: Second Semiconductor Material 54A~54C: Second semiconductor material layer 55: Internal spacers 64: Multi-layer stacking 90: Semiconductor fins 90U: Top surface 91: Fin Structure 92: Layer stacking 93: Passage Area / Passage Level 94: Mask 94A: First mask layer 94B: Second masking layer 96: STI Zone 97: Dummy Dielectric Layer 99: Silicone region 100: NSFET device 101: Virtual gate structure 102: Dummy gate 103: Groove 104: Mask 104A: First masking layer 104B: Second masking layer 108: Gate spacer layer 108F: Fin spacers 112: Source / Drain Region 114: First ILD 116:CESL 118: Gate Contact Socket 119: Source / Drain Contact Socket 120: Gate dielectric layer 122: Gate electrode 123: Replace the gate structure 124: Source / Drain Region 130: Front-side interconnect structure 131: Through hole 132: Electrical conductivity characteristics 132P: Conductivity characteristics 132PU: Top Surface 134:ESL 135: Second ILD 136: Dielectric layer 136T: Top dielectric layer 138: Gate shield 142: Device Layer 143: Dielectric Materials 145:ESL 147: Lining layer 149: Heat dissipation device 150: Dashed line 151: Rear Interconnect Structure Part of 160:136T 161: Remove the rate modification layer 163: Remove the rate modification layer 165: Abrasive particles 167: Arrow 200: NSFET device 300:CFET device 300A: CFET device 1000: Method 1010~1050: Square

[0097] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor device, the method comprising the steps of: forming a device layer over a first substrate, wherein the device layer includes a transistor, wherein the transistor includes a fin protruding over the first substrate, a plurality of channel regions over the fin, a gate structure around the channel regions, and source / drain regions over the fin and on a plurality of opposite sides of the gate structure; forming an interconnect structure at a first side of the device layer and electrically coupling it to the transistor, wherein the interconnect structure includes a plurality of first dielectric layers and a plurality of conductive features embedded in the first dielectric layers, wherein the step of forming the interconnect structure includes the step of: forming an outermost dielectric layer of the interconnect structure away from the device layer using a polycrystalline material, wherein a first facet of the polycrystalline material and a second facet of the polycrystalline material have different lattice densities; A plurality of molecules of a first material are selectively adsorbed on the first small plane of the polycrystalline material; and after selectively adsorbing the plurality of molecules of the first material, a planarization process is performed on the polycrystalline material, wherein during the planarization process, the molecules of the first material reduce the difference between a first removal rate of the polycrystalline material at the first small plane and a second removal rate of the polycrystalline material at the second small plane; and after forming the interconnect structure, the outermost dielectric layer of the interconnect structure is bonded to a second dielectric layer formed on a second substrate.

2. The method as claimed in claim 1, wherein the first facet has a higher lattice density than the second facet, wherein during the planarization process, the molecules of the first material cause the first removal rate of the polycrystalline material at the first facet to increase.

3. The method as claimed in claim 2, wherein the planarization process includes a chemical mechanical planarization (CMP) process performed using a slurry containing a plurality of abrasive particles, wherein the abrasive particles and the polycrystalline material carry a first type of charge, wherein the molecules of the first material carry a second type of charge different from the first type of charge.

4. The method as described in claim 3, wherein the abrasive particles and the polycrystalline material carry a plurality of negative charges, and the molecules of the first material are cations.

5. The method as described in claim 3, wherein the abrasive particles and the polycrystalline material carry a plurality of positive charges, and the molecules of the first material are anions.

6. A method for forming a semiconductor device, the method comprising the steps of: forming a device layer over a first substrate, wherein the device layer includes a transistor; forming a first dielectric layer over the first substrate and the transistor; forming a conductive feature in the first dielectric layer, wherein the conductive feature is electrically coupled to the transistor; forming a layer of a polycrystalline material over the first dielectric layer, wherein a first facet and a second facet of the polycrystalline material have different lattice densities; selectively forming a removal rate modification layer on the first facet of the polycrystalline material by selectively adsorbing a plurality of molecules of a first material on the first facet; and after selectively forming the removal rate modification layer, performing a planarization process on the polycrystalline material, wherein the planarization process removes the polycrystalline material at a first removal rate at the first facet and at a second removal rate at the second facet, wherein the removal rate modification layer causes a reduction in the difference between the first removal rate and the second removal rate.

7. The method as described in claim 6, further comprising the step of: after performing the planarization process, bonding the layer of the polycrystalline material to a second dielectric layer formed over a second substrate via dielectric-to-dielectric bonding.

8. The method as claimed in claim 7, further comprising the step of forming a first bonding feature in the layer of the polycrystalline material after performing the planarization process and before bonding the layer of the polycrystalline material, wherein the method further comprises the step of bonding the first bonding feature to a second bonding feature embedded in the second dielectric layer via metal-to-metal bonding.

9. A method of forming a semiconductor device, the method comprising the steps of: forming a conductive feature over a substrate; forming a dielectric layer over the conductive feature and the substrate; forming a layer of a polycrystalline material over the dielectric layer, wherein a first facet and a second facet of the polycrystalline material have different lattice densities; selectively adsorbing a plurality of molecules of a first material on the first facet of the polycrystalline material; and after selectively adsorbing the molecules of the first material, performing a planarization process on the layer of the polycrystalline material, wherein the planarization process removes the polycrystalline material at the first facet at a first removal rate and at the second facet at a second removal rate, wherein the molecules of the first material on the first facet cause a reduction in the difference between the first removal rate and the second removal rate.

10. The method of claim 9, wherein the first facet has a lower lattice density than the second facet, wherein the method further comprises the steps of: selectively adsorbing a plurality of molecules of a second material on the second facet of the polycrystalline material, wherein the molecules of the first material on the first facet cause a decrease in the first removal rate, and wherein the molecules of the second material on the second facet cause an increase in the second removal rate.

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