Semiconductor device and methods of forming the same

Abstract

Embodiments of this disclosure provide a semiconductor device comprising: a substrate having a front side and a back side opposite to the front side of the substrate; a channel region disposed between a first source / drain region and a second source / drain region and above the front side of the substrate; a gate structure disposed above the channel region; and a first contact disposed in the substrate, wherein the first contact includes a first sidewall extending from the back side of the substrate and a second sidewall extending to the first source / drain region, wherein the first sidewall and the second sidewall are on the same side of the first contact, wherein the second sidewall is horizontally further away from the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region.

Description

Technical Field

[0001] none Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the development of ICs, functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometric dimensions (i.e., the smallest component (or line) that can be produced using manufacturing processes) have decreased. This shrinkage typically benefits production efficiency and reduces associated costs. However, such shrinkage also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, it is necessary to improve the manufacturing process and production of integrated circuits. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] Several aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Figures 1 through 6 are perspective views of intermediate stages in the manufacture of a semiconductor device according to some embodiments. Figures 7A to 25B are cross-sectional views of an intermediate stage in the manufacture of a semiconductor device according to some embodiments. Figures 26A to 30B are cross-sectional views of an intermediate stage in the manufacture of a semiconductor device according to some embodiments. Figures 31A to 34B are cross-sectional views of an intermediate stage in the manufacture of a semiconductor device according to some embodiments. Figures 35A and 35B are cross-sectional views of an intermediate stage in the manufacture of a semiconductor device according to some embodiments. Figures 36A and 36B are cross-sectional views of an intermediate stage in the manufacture of a semiconductor device according to some embodiments. Figures 37 to 40B are perspective and cross-sectional views of intermediate stages in the manufacture of a semiconductor device according to some embodiments. Implementation

[0006] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and not limiting. For example, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplification and clarity, and the repetition itself does not imply a relationship between the various implementations and / or configurations discussed.

[0007] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the figures, spatially relative terms may be used herein, such as "below," "lower than," "slightly below," "higher than," "above," "above," "top," "above," and similar terms. In addition to the directions illustrated in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0008] Various embodiments of this disclosure provide a semiconductor device including a plurality of self-aligned back-side contacts formed in a substrate and electrically coupled to a source / drain region. The self-aligned back-side contacts formed in this self-aligned manner can effectively reduce the risk of damage to the gate structure or the formation of a short circuit between the back-side contacts and the gate structure.

[0009] While various embodiments of this disclosure are discussed in relation to nanostructured channel field-effect transistors, such as gate-all-around (GAA) field-effect transistors, like horizontal gate-all-around (HGAA) or vertical gate-all-around (VGAA) field-effect transistors, some aspects of this disclosure can be applied to other processes and / or other devices, such as planar field-effect transistors, fin field-effect transistors, and other suitable devices. Other modifications that may be made within the scope of this disclosure will be readily understood by those skilled in the art. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing the pattern to be created to have, for example, a smaller pitch than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A plurality of spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the gate full-ring structure.

[0010] Figures 1 through 25B illustrate exemplary processes for manufacturing a semiconductor device 100 according to various embodiments of this disclosure. It should be understood that, for additional embodiments of this method, additional operations may be provided before, during, and after the processes shown in Figures 1 through 25B, and some of the operations described below may be replaced or eliminated. The order of operations / processes is not limiting and is interchangeable.

[0011] Figures 1 through 6 are perspective views of intermediate stages in the manufacture of a semiconductor device 100 according to some embodiments. As shown in Figure 1, the semiconductor device 100 includes a substrate 101 having a front side 101F and a back side 101B opposite to the front side 101F. The semiconductor device 100 also includes a multilayer stack 102 formed over the front side 101F of the substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0012] The substrate 101 may include various regions in the front side 101F of the substrate 101 that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the substrate 101 may include p-type doped wells for n-type field-effect transistors (NFETs) and n-type doped wells for p-type field-effect transistors (PFETs).

[0013] The multilayer stack 102 includes alternating semiconductor layers made of different materials to facilitate the formation of multiple nanostructure channels, such as nanostructure channel field-effect transistors, in a multi-gate device. In some embodiments, the multilayer stack 102 includes a first semiconductor layer 104 and a second semiconductor layer 106 alternately stacked over the front side 101F of the substrate 101. For example, for illustrative purposes, the multilayer stack 102 is shown as including three layers of first semiconductor layer 104 and three layers of second semiconductor layer 106. It should be understood that any number of first semiconductor layers 104 and second semiconductor layers 106 may be included in the multilayer stack 102. In some embodiments, the first semiconductor layer 104 is formed of a first semiconductor material, and the second semiconductor layer 106 is formed of a second semiconductor material different from the first semiconductor material. The second semiconductor material may have a different etch selectivity and / or oxidation rate than the first semiconductor material. In some embodiments, the first or second semiconductor material is or includes, for example, SiGe, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, combinations thereof, or similar materials. In some embodiments, the first semiconductor material is formed of Si, and the second semiconductor material is formed of SiGe, or vice versa.

[0014] The thickness of each first semiconductor layer 104 may be in the range of about 5 nanometers (nm) to about 30 nanometers. The thickness of each second semiconductor layer 106 may be equal to, less than, or greater than the thickness of the first semiconductor layer 104. In some embodiments, the thickness of each second semiconductor layer 106 is in the range of about 2 nanometers to about 50 nanometers. The first semiconductor layer 104 and the second semiconductor layer 106 are formed via any suitable deposition process, such as epitaxial deposition. For example, the epitaxial deposition of the multilayer stack 102 may be performed via vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), similar, and / or other suitable epitaxial growth processes.

[0015] In Figure 2, according to some embodiments, the patterned multilayer stack 102 and substrate 101 are processed via one or more etching processes. Each semiconductor strip 108 may include a first nanostructure 110 patterned from a first semiconductor layer 104 and a second nanostructure 112 patterned from a second semiconductor layer 106. After the etching process, the substrate 101 may include a plurality of fins 114. The plurality of semiconductor strips 108 are respectively disposed above the plurality of fins 114. The term nanostructure is used herein to refer to any portion of material having a nanometer or even micrometer-scale size and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, this term refers to elongated portions of material with circular and substantially circular cross-sections, as well as elongated or strip-shaped portions of material including, for example, cylindrical or substantially rectangular cross-sections.

[0016] Forming the semiconductor strip 108 can be achieved by patterning a hard mask layer (not shown) formed on a multilayer stack 102 using multiple patterning operations, including lithography and etching processes. The etching process can include dry etching, such as reactive ion etching (RIE) or neutral beam etching (NBE), wet etching, and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, the photoresist layer can be patterned to form a patterned mask element using an electron beam lithography process. The etching process forms trenches 116 in unprotected areas that penetrate the hard mask layer, through the multilayer stack 102, and into the substrate 101, thereby leaving the semiconductor strip 108 and fins 114. The trenches 116 extend along the X direction. In some embodiments, the semiconductor strip 108 and fin 114 have a longitudinal axis along the X direction.

[0017] Semiconductor device 100 may include a plurality of transistor structures. A first nanostructure 110 or portions thereof may form nanostructure channels of the transistor structure in a subsequent manufacturing stage, while a second nanostructure 112 may act as a sacrificial layer in a subsequent manufacturing stage to allow the nanostructure channels to be surrounded by gate structures. The transistor structure having nanostructure channels may be referred to as a nanostructure transistor, nanosheet transistor, nanowire transistor, gate-all-around (GAA) transistor, multi-bridge channel (MBC) transistor, or any transistor having gate electrodes surrounding the channels.

[0018] In Figure 3, after forming the semiconductor strips 108, an insulating material 118 is formed over the substrate 101. The insulating material 118 fills trenches 116 between adjacent semiconductor strips 108 until the semiconductor strips 108 are embedded in the insulating material 118. A planarization operation, such as chemical mechanical polishing (CMP) and / or etch-back, is then performed to expose the top of the semiconductor strips 108. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), fluorine-doped silicate glass (FSG), a low-k dielectric material (k value less than about 3.5), or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as flowable chemical vapor deposition (FCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0019] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes multiple portions of semiconductor strips 108 and substrate 101. The recess in insulating material 118 reveals trenches 116 between adjacent semiconductor strips 108. Forming isolation region 120 can be achieved using suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of isolation region 120 may be flush with or below the top surface of fin 114 and in contact with fin 114.

[0020] In Figure 5, one or more dummy gate structures 130 (only one shown) are formed over semiconductor device 100. The dummy gate structure 130 is formed over a portion of semiconductor strip 108. Each dummy gate structure 130 may include a dummy gate dielectric 132, a dummy gate electrode 134, and a hard mask 136. Forming the dummy gate dielectric 132, dummy gate electrode 134, and hard mask 136 may be achieved by sequentially depositing multiple blanket layers of the dummy gate dielectric 132, dummy gate electrode 134, and hard mask 136, and then patterning those layers into the dummy gate structure 130. The dummy gate structure 130 may have a longitudinal direction (e.g., the Y direction in Figure 5) substantially perpendicular to the longitudinal direction of semiconductor strip 108 (e.g., the X direction in Figure 5). The dummy gate structure 130 can be located on the isolation region 120 and span one or more semiconductor strips 108.

[0021] The dummy gate dielectric 132 may include one or more layers of dielectric material, such as a deposited oxide-based material (e.g., silicon oxide) or a material oxidized from the substrate 101. The dummy gate electrode 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The hard mask 136 may include one or more dielectric layers. For example, the hard mask 136 may be a combination of oxide layers and nitride layers.

[0022] Then, a gate spacer 138 is formed on the sidewall of the dummy gate structure 130. The gate spacer 138 can be formed by conformally depositing one or more layers for the gate spacer 138 and anisotropically etching (e.g., reactive ion etching) the one or more layers. For example, dielectric materials such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), combinations thereof, or similar dielectric materials can be used for the gate spacer 138.

[0023] In Figure 6, according to some embodiments, a first opening 140 is formed in the semiconductor strip 108, fin 114, and substrate 101. Forming the first opening 140 may be achieved by removing at least portions of the semiconductor strip 108 and substrate 101 that are not protected by the gate spacer 138 and dummy gate structure 130. Thus, the first opening 140 may be formed in the X direction between adjacent dummy gate structures 130, as shown in Figure 6 (or in the cross-sectional view shown in Figure 7A). The first opening 140 may be recessed below the top surface of the isolation region 120, although it may also be recessed to be flush with or above the top surface of the isolation region 120. The first opening 140 may be formed via an etching process of isotropic or anisotropic etching, and this etching process may be selective relative to one or more crystal planes of the substrate 101. The etching process can be dry etching, such as reactive ion etching, neutral beam etching, or the like, or wet etching. The etchant from the etching process can include C2H4F2, C2F6, CF4, mixtures with or without HBr, Cl2, O2, or the like, or any suitable etchant.

[0024] Figures 7A and 7B are cross-sectional views of the semiconductor device 100 taken along sections AA and BB of Figure 6, respectively. According to some embodiments, the cross-sectional views show a plurality of dummy gate structures 130, a plurality of semiconductor strips 108, and other detailed elements. Throughout this description, figures including "A" are obtained from reference section AA of Figure 6, and figures including "B" are obtained from reference section BB of Figure 6.

[0025] In Figures 7A and 7B, the first opening 140 extends through the stack of the first nanostructure 110 and the second nanostructure 112 and into the substrate 101. In some embodiments, the first opening 140 has an extending depth, for example, at least about twice the height of the stack of the first nanostructure 110 and the second nanostructure 112. The extending depth of the first opening 140 provides sufficient space for forming the insulating filler 154 (Figure 12A).

[0026] According to some embodiments, in Figures 8A and 8B, the second nanostructure 112 exposed by the first opening 140 is etched to form a plurality of second openings 142. That is, the second openings 142 can be spaces occupied by the second nanostructures 112, including spaces between adjacent first nanostructures 110 and spaces between the bottommost first nanostructure 110 and the substrate 101. When a selective etchant is used to etch the second semiconductor material of the second nanostructure 112, the first nanostructures 110 and the substrate 101 remain relatively unetched. In embodiments where the second semiconductor material includes, for example, SiGe, an etching process using a hydroxide etchant, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like, is used.

[0027] According to some embodiments, in Figures 9A and 9B, an insulating layer 144 is deposited in a first opening 140 and a second opening 142. In some embodiments, given the dimensional difference between the first opening 140 and the second opening 142, the insulating layer 144 may substantially or completely fill the second opening 142 and form a conformal layer in the first opening 140. The insulating layer 144 may comprise an oxide-containing material, such as silicon oxide, silicon oxynitride, SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. In some embodiments, the insulating layer 144 comprises a material similar to that of the isolation region 120. The insulating layer 144 may be formed via any suitable deposition method, such as FCVD, ALD, PECVD, LPCVD, combinations thereof, or similar methods.

[0028] According to some embodiments, in Figures 10A and 10B, an etching process is performed to remove the insulating layer 144 in the first opening 140 and to partially recess the insulating layer 144 in the second opening 142 (Figure 8A). The etching process may use an etchant that selectively etches the insulating layer 144, and the first nanostructure 110 and the substrate 101 may remain relatively unetched. The etching process may be an isotropic etching process. In some embodiments, the isotropic etching process is performed for a sufficiently long time to remove the insulating layer 144 in the first opening 140 and to laterally recess the insulating layer 144 in the second opening 142. Accordingly, the insulating layer 144 in the first opening 140 is substantially or completely removed. In embodiments where the insulating layer 144 remains in the first opening 140 after the isotropic etching process, a further anisotropic process may be performed to substantially or completely remove the insulating layer 144 in the first opening 140.

[0029] According to some embodiments, in Figures 11A and 11B, internal spacers 150 are formed in the lateral recesses and on the sidewalls of the insulating layer 144. The internal spacers 150 can serve as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first opening 140, and the insulating layer 144 will be replaced with the gate structure.

[0030] In some embodiments, the internal spacer layer is deposited via conformal deposition processes such as CVD, ALD, or the like. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material, such as a low-k dielectric material, may be used. The internal spacer layer may then be anisotropically etched to form internal spacer 150, using gate spacer 138 as a mask via, for example, reactive ion etching, neutral beam etching, or the like. Although the outer wall of internal spacer 150 is shown flush with the sidewall of first nanostructure 110 in Figure 11A, the outer wall of internal spacer 150 may extend beyond or be recessed from the sidewall of first nanostructure 110. Furthermore, although the outer wall of internal spacer 150 is shown straight in Figure 11A, the outer wall of internal spacer 150 may be concave or convex.

[0031] In Figures 12A and 12B, according to some embodiments, an isolation filler 154 is formed in the first opening 140. Forming the isolation filler 154 may be achieved, for example, by depositing a dielectric layer of relatively thick thickness on the bottom of the first opening 140 and a dielectric layer of relatively thin thickness on the sidewalls of the first opening 140, followed by a trimming etch process to remove the dielectric layer on the sidewalls of the first opening 140. The deposition of the dielectric layer may include FCVD, PECVD, LPCVD, combinations thereof, or similar methods. The trimming etch process may be wet etching, dry etching with a suitable tilt angle, or a combination thereof. In some embodiments, the dielectric layer deposition process and the trimming etch process may be repeated to allow the isolation filler 154 to have sufficient thickness at the bottom of the first opening 140. The isolation filler 154 may at least cover the exposed surface of the first opening 140 below the bottommost insulating layer 144 to isolate the subsequently formed source / drain region 158 (Figure 13A) from the substrate 101. Because the first opening 140 has an extended depth within the substrate 101, the isolation filler 154 also effectively reduces or prevents leakage or crosstalk between adjacent epitaxial source / drain regions (Figure 13A). In some embodiments, the isolation filler includes a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbide, combinations thereof, or the like. In some embodiments, the isolation filler includes SiGe when the epitaxial source / drain regions (Figure 13A) are not formed of SiGe or include an underlayer not formed of SiGe.

[0032] The upper surface of the spacer filler 154 can be a flat surface, a convex surface, or a concave surface. In some embodiments, as shown in Figure 12C, the upper surface of the spacer filler 154 can be a concave surface to allow for the formation of a larger volume source / drain region 158 in the first opening 140, which can provide improved electrical performance. In some embodiments, the upper surface of the spacer filler 154 can vertically overlap the bottommost internal spacer 150 (e.g., between the bottom of the bottommost first nanostructure 110 and the top of the fin 114 / substrate 101). The spacer filler 154 may not be in physical contact with the first nanostructure 110.

[0033] According to some embodiments, in Figures 13A and 13B, a source / drain region 158 is formed in the first opening 140 and over the insulating filler 154. In this disclosure, the source and drain regions are used interchangeably and their structures are substantially the same. Furthermore, the source / drain region may refer to either the source or the drain, individually or collectively depending on the context. The source / drain region may apply stress to the first nanostructure 110, thereby improving device performance. For n-type channel field-effect transistors, the source / drain region 158 may be made of one or more layers of Si, SiP, SiC, and SiCP, or for p-type channel field-effect transistors, the source / drain region 158 may be made of one or more layers of Si, SiGe, and Ge. For p-type field-effect transistors (PFETs), p-type impurities, such as boron, boron fluoride, indium, or the like, may be included in the source / drain region 158. For n-type field-effect transistors (NFETs), n-type impurities, such as phosphorus, arsenic, antimony, or the like, may be included in the source / drain regions 158. The source / drain regions 158 can be formed via epitaxial growth methods such as CVD, ALD, MBE, combinations thereof, or the like, and may also be referred to as epitaxial source / drain regions 158. In some embodiments, impurities may be in-situ doped when the source / drain regions 158 are epitaxially deposited. The source / drain regions 158 may have impurity concentrations between about 1 × 10¹⁹ atoms / cm³ and about 1 × 10²¹ atoms / cm³. In some embodiments, the source / drain regions 158 are grown to form a plurality of facets, which may correspond to crystal planes of the material used for the substrate 101.

[0034] In Figures 14A and 14B, according to some embodiments, a contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device 100. The CESL 160 covers the sidewalls of the isolation region 120, the source / drain region 158, and the gate spacer 138. The CESL 160 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or similar materials, or combinations thereof, and may be formed via CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 162 is formed on the CESL 160 above the semiconductor device 100. The material used for the first interlayer dielectric layer 162 may include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, SiOC, phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), combinations thereof, or the like. Organic materials, such as polymers, may also be used for the first interlayer dielectric layer 162. The first interlayer dielectric layer 162 may be deposited via FCVD, PECVD, or other suitable deposition techniques. In some embodiments, after the first interlayer dielectric layer 162 is deposited, a heat treatment is performed to cure the first interlayer dielectric layer 162. After the first interlayer dielectric layer 162 is formed, a planarization operation, such as chemical mechanical polishing (CMP), is performed to make the top surface of the first interlayer dielectric layer 162 flush with the top surface of the dummy gate electrode 134 or the hard mask 136. In some embodiments where the hard mask 136 is retained, the planarization process flushes the top surface of the first interlayer dielectric layer 162 with the top surfaces of the hard mask 136 and the gate spacer 138. In some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 134, the gate spacer 138, and the first interlayer dielectric layer 162 are flush within process variations. In such embodiments, the top surface of the dummy gate electrode 134 is exposed through the first interlayer dielectric layer 162.

[0035] In some embodiments, an optional first capping layer (not shown) is formed over the first interlayer dielectric layer 162. Forming the first capping layer may include recessing the first interlayer dielectric layer 162 between the plurality of dummy gate electrodes 134 and filling the recess with the first capping layer produced via the recessing process. Filling the recess with the first capping layer can be achieved via any suitable deposition process, such as CVD, PECVD, ALD, or other suitable methods. In some embodiments, a planarization process is then performed to remove excess portions of the first capping layer over the dummy gate electrodes 134, such that the upper surface of the first capping layer is flush with the upper surface of the dummy gate electrodes 134 or the hard mask 136 (if present). In some embodiments, the first capping layer includes silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, combinations thereof, or the like. The first capping layer protects the first interlayer dielectric layer 162 from damage during the removal of the insulating layer 144, as shown in Figures 16A and 16B.

[0036] In Figures 15A and 15B, the dummy gate electrode 134 and the hard mask 136 (if present) are removed. In some embodiments, the dummy gate dielectric 132 is also removed after the dummy gate electrode 134 is removed. The removal of the hard mask 136, the dummy gate electrode 134, and the dummy gate dielectric 132 can be performed via one or more etching processes. For example, the etching process can be performed by etching the hard mask 136, using the dummy gate electrode 134 as an etch barrier; etching the dummy gate electrode 134, using the dummy gate dielectric 132 as an etch barrier; and then removing the dummy gate dielectric 132 via another etching process. In some embodiments, the etching process for etching the dummy gate electrode 134 and the dummy gate dielectric 132 may include using a reactive gas that selectively etches the dummy gate electrode 134 and the dummy gate dielectric 132 at a faster rate than etching the first interlayer dielectric layer 162 or the gate spacer 138. As shown in Figure 15B, after removing the dummy gate dielectric 132 and the dummy gate electrode 134, the insulating layer 144 is exposed.

[0037] According to some embodiments, in Figures 16A and 16B, the insulating layer 144 is removed. Removal of the insulating layer 144 can be achieved via an isotropic etching process, such as via wet etching containing an etchant comprising diluted HF or other suitable etchant. The removal of the hard mask 136, the dummy gate electrode 134, the dummy gate dielectric 132, and the insulating layer 144 forms a third opening 164 between the plurality of gate spacers 138 and between the plurality of first nanostructures 110. In some embodiments, the process associated with the insulating layer 144 can be omitted, such as the process shown in Figures 8A through 11B, so the second nanostructure 112 remains and is not replaced by the insulating layer 144. In such an embodiment, the third opening 164 is formed by removing the second nanostructure 112, and the features of the internal spacers 150 and the isolation filler 154 shown, for example, in Figures 12A through 15B, are still formed and located at the position shown in Figure 16A.

[0038] In some embodiments, an optional second capping layer (not shown) is formed over the isolation region 120 before the insulating layer 144 is removed. Formation of the second capping layer may include depositing a dielectric material over the upper surface of the isolation region 120 and over the exposed surfaces of the first nanostructure 110 and the insulating layer 144. In some embodiments, the thickness of the dielectric material over the upper surface of the isolation region 120 may be greater than the thickness of the dielectric material over the first nanostructure 110 and over the exposed surfaces of the insulating layer 144, by adjusting suitable deposition parameters or depending on the deposition method (e.g., FCVD). An etching process may then be performed to remove the dielectric material over the exposed surfaces of the first nanostructure 110 and the insulating layer 144, while some of the dielectric material on the upper surface of the isolation region 120 may be retained to form the second capping layer. The etching process may include a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the second capping layer includes silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, combinations thereof, or the like. The second capping layer protects the isolation area 120 from damage during the removal of the insulation layer 144.

[0039] In Figures 17A and 17B, a gate dielectric layer 168 and a gate electrode 170 are formed to replace the gate. The gate dielectric layer 168 is conformally deposited in the third opening 164. The gate dielectric layer 168 may be formed on the top surface and sidewalls of the substrate 101 and on the exposed surface of the first nanostructure 110. In some embodiments, the gate dielectric layer 168 is also deposited on multiple top surfaces of the first interlayer dielectric layer 162, the contact etch stop layer 160, the gate spacer 138, and the isolation region 120. In some embodiments, the gate dielectric layer 168 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high dielectric constant dielectric materials include HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium oxide-alumina (HfO-AlO) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 168 can be formed via CVD, ALD, or any suitable deposition technique.

[0040] Gate electrodes 170 are deposited over gate dielectric layer 168 and fill the remaining portion of third opening 164. Gate electrode 170 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. Although a single-layer gate electrode 170 is shown in Figures 17A and 17B, gate electrode 170 may comprise any number of pad layers, any number of work function calibration layers, and filler material. Gate electrode 170 may be formed via CVD, ALD, electroplating, or other suitable deposition techniques. After filling third opening 164, excess material of gate dielectric layer 168 and gate electrode 170 above the top surface of first interlayer dielectric layer 162 is then removed via a planarization process (e.g., CMP) until the top surface of first interlayer dielectric layer 162 is exposed. The remaining portions of the gate electrode 170 and the gate dielectric layer 168 thus form an alternative gate structure for the semiconductor device 100. The gate electrode 170 and the gate dielectric layer 168 may be collectively referred to as gate structure 172. Gate structure 172 may surround the channel of the semiconductor device 100 (i.e., the first nanostructure 110).

[0041] As further shown in Figures 18A and 18B, a second interlayer dielectric layer 174 is deposited over a first interlayer dielectric layer 162. In some embodiments, the second interlayer dielectric layer 174 is formed of a dielectric material similar to the first interlayer dielectric layer 162 and is formed via a method similar to that used for the first interlayer dielectric layer 162. In some embodiments, a contact etch stop layer 176 is also formed prior to the formation of the second interlayer dielectric layer 174. The contact etch stop layer 176 may comprise a material similar to that used for the contact etch stop layer 160 and may be formed using a method similar to that used for the contact etch stop layer 160.

[0042] In Figures 19A and 19B, according to some embodiments, contacts 178 and 180 are formed in the first interlayer dielectric layer 162 and the second interlayer dielectric layer 174. Contact 178 is electrically coupled to the source / drain region 158 and may be referred to as a source / drain contact. Because contact 178 is formed above the front side 101F of the substrate 101, contact 178 may also be referred to as a front contact or a front source / drain contact. Contact 180 is electrically coupled to the gate structure 172 and may be referred to as a gate contact.

[0043] In some embodiments, contact 178 is electrically coupled to source / drain regions 158. For example, contact 178 may extend to physically connect to the front side of source / drain regions 158. Contact 178 is formed above and electrically coupled to some source / drain regions 158, the top surfaces of other source / drain regions 158 being completely covered by contact etch stop layer 160 and / or first interlayer dielectric layer 162. Depending on design requirements, not all source / drain regions 158 are electrically coupled to contact 178. For example, depending on design requirements, only some source / drain regions 158 are electrically coupled to contact 178, and as will be discussed in detail below, some source / drain regions 158 may be electrically coupled to back contact 192 (Figure 23A).

[0044] According to some embodiments, the formation of contacts 178 and 180 includes etching a second interlayer dielectric layer 174, a first interlayer dielectric layer 162, a contact etch stop layer 176, and / or a contact etch stop layer 160 to form recesses exposing multiple surfaces of the source / drain region 158 and / or the gate structure 172, and then depositing material for contacts 178 and 180 in the recesses. The recesses can be formed using one or more anisotropic etching processes, such as reactive ion etching, neutral beam etching, or similar methods.

[0045] Contacts 178 and 180 may each comprise one or more layers, such as a barrier layer (not shown), an adhesive layer (not shown), and a filler material above the barrier layer and / or adhesive layer. In some embodiments, the barrier layer of contacts 178 and 180 includes titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material of contacts 178 and 180 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, contact 178 also includes a silicon region 182 in contact with the source / drain region 158 to reduce resistance. The silicon region 182 may be formed between the barrier layer (or filler material) and the source / drain region 158, via the material of the barrier layer (or filler material) of contact 178 reacting with the semiconductor material of the source / drain region 158. Although the silicate region 182 is referred to as a silicate region, it can also be a germanide region or a germanium silicate region. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the contacts 178 and 180 above the top surface of the second interlayer dielectric layer 174.

[0046] Figures 20A to 25B illustrate intermediate steps, according to some embodiments, of forming a front-side interconnect structure 183 over the front side 101F of substrate 101 (as shown in Figures 20A and 20B), forming a back-side contact 192 in substrate 101 (as shown in Figures 22A to 24B), and forming a back-side interconnect structure 195 over the back side 101B of substrate 101 (as shown in Figures 25A and 25B). In Figures 20A and 20B, according to some embodiments, the front-side interconnect structure 183 is formed over the front side 101F of substrate 101, for example, over a second interlayer dielectric layer 174. The front-side interconnect structure 183 may include one or more conductive features 184 formed in one or more stacked dielectric layers 186. Each of the multiple stacked dielectric layers 186 may contain a dielectric material, such as silica, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), a low-k dielectric material, a combination thereof, or the like. The dielectric layers 186 may be deposited using suitable processes, such as CVD, PECVD, PVD, or the like.

[0047] Conductive feature 184 may include multiple conductive lines and multiple conductive vias interconnecting the multiple conductive lines across multiple layers. The conductive vias may extend through corresponding ones of multiple dielectric layers 186 to provide vertical connections between the conductive lines across the multiple layers. Conductive feature 184 may be formed via any acceptable process, such as a single damascene process, a dual damascene process, a combination thereof, or the like. For example, conductive feature 184 may be formed using a damascene process, in which a combination of photolithography and etching techniques is used to pattern the corresponding dielectric layers 186 to form trenches corresponding to the desired pattern of conductive feature 184. Optional diffusion barrier layers and / or optional adhesion layers may be deposited, and then these trenches may be filled with a conductive material. Suitable materials for the barrier layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like; suitable materials for the conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In one embodiment, the conductive features 184 can be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. Chemical mechanical planarization (CMP) processes or the like can be used to remove excess conductive material from the surfaces of the respective dielectric layers 186 and planarize the multiple surfaces of the dielectric layers 186 and the conductive features 184 for subsequent processing.

[0048] Figures 20A and 20B show five layers of conductive features 184 and dielectric layers 186 in the front interconnect structure 183. However, it should be understood that the front interconnect structure 183 may contain any number of conductive features 184 disposed in any number of dielectric layers 186. The front interconnect structure 183 may be electrically connected to source / drain contacts 178 and gate contacts 180. In some embodiments, the front interconnect structure 183 also includes bump pads located at the top layer of the front interconnect structure 183 for external connections. External connections can be electrically coupled to the source / drain region 158 via the front interconnect structure 183 and contacts 178.

[0049] In Figures 21A and 21B, the carrier substrate 188 is bonded to the top surface of the front interconnect structure 183 via a bonding layer 190. The carrier substrate 188 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. The carrier substrate 188 may provide structural support during subsequent processing steps and in the completed apparatus.

[0050] In some embodiments, the bonding layer 190 may be a heat-release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating; an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light; or the like. The bonding layer 190 may be dispensed and cured as a liquid. After the carrier substrate 188 is bonded to the front interconnect structure 183, the semiconductor device 100 may be flipped so that the back side 101B of the substrate 101 faces upward. According to some embodiments, a thinning process is then applied to the back side 101B of the substrate 101. The thinning process may include planarization processes (e.g., mechanical polishing, chemical mechanical polishing, or the like), etch-back processes, combinations thereof, or the like.

[0051] According to some embodiments, in Figures 22A and 22B, an opening 191A for a back-side contact 192 is formed in the substrate 101. The opening 191A may expose at least a portion of the insulating filler 154. The opening 191A may be formed via a suitable etching process. In some embodiments, the opening 191A may be one or more anisotropic etching processes, such as reactive ion etching, neutral beam etching, or the like. In some embodiments, the etching process for the opening 191A may use the insulating filler 154 as a buffer or etch barrier so that the opening 191A does not extend directly through the substrate 101. In some embodiments, the etching process for the opening 191A may also include timed-mode etching to prevent the opening 191 from extending through the substrate 101. The etching process for the opening 191A may use an etchant that is highly selective for the substrate 101, such as a mixture of Cl2 or HBr with O2 or CO2, or the like. In this way, when the opening 191A is formed in the substrate 101, the isolation filler 154 and other components of the semiconductor device 100 are not significantly affected.

[0052] In some embodiments, due to process variations, such as lithography resolution limitations or overlap misalignment, the opening 191A is partially misaligned with the source / drain region 158. For example, the bottom of the opening 191A may overlap with the gate structure 172 in a plan view, and if the opening 191A extends through the substrate 101, the gate structure 172 will be exposed. Because the opening 191A is controlled to not extend through the substrate 101, the etching process of the opening 191A will not damage the gate structure 172. In some embodiments, a thicker insulating filler 154 provides better buffering or etch blocking for the etching process used to form the opening 191A.

[0053] According to some embodiments, in Figures 23A and 23B, an opening 191B for the back-side contact 192 is formed by removing the isolation filler 154. The opening 191B can be formed via a suitable etching process. In some embodiments, the opening 191B can be one or more isotropic etching processes, such as wet etching. The etching process for the opening 191B can use an etchant that is highly selective for the isolation filler 154. For example, when the isolation filler 154 is or includes an oxide, the etchant can include a mixture of HF, NH3, and HF, combinations thereof, or the like. Alternatively, when the isolation filler 154 is or includes a nitride, the etchant can include phosphoric acid, HF, or a mixture of NF3 with H2 and / or O2, or the like. In some embodiments, when the isolation filler 154 includes SiGe, the etchant includes a halogen-based gas, such as a mixture selected from NF3, F2, HF, and CClF3, with or without the application of a plasma capable of enhancing the dissociation of the etchant. When HF and F2 are used to etch SiGe, a higher etching rate for Si than for Ge can be achieved by increasing the F2 / HF ratio (e.g., the F2 / HF ratio can range from 0.01 to 100). In some embodiments, the dry etching process includes the use of plasma to dissociate the etchant. Thus, the substrate 101 or other components of the semiconductor device 100 are substantially unaffected when opening 191B is formed. Openings 191A and 191B together form opening 191 for the back-side contact 192.

[0054] The high etch selectivity between the isolation filler 154 and the substrate 101 allows the opening 191B to be formed according to the shape of the isolation filler 154. Therefore, the opening 191B can be self-aligned to guide the source / drain region 158, although the opening 191A may be misaligned with the source / drain region 158. Since the opening 191 for the back-side contact 192 can be formed to expose the source / drain region 158 in a self-aligned manner, the risk of damage to the gate structure 172 or the formation of a short circuit between the back-side contact 192 and the gate structure 172 can be effectively reduced or prevented. This can improve manufacturing yield and device reliability.

[0055] According to some embodiments, in Figures 23A and 23B, a back-side contact 192 is formed in the opening 191. In some embodiments, the first nanostructure 110, the source / drain region 158, the front-side contact 178, and the back-side contact 192 form a transistor structure 100A. In an exemplary embodiment, a transistor structure 100A includes a first nanostructure 110 disposed as a channel between the source / drain region 158A and the source / drain region 158B, a front-side contact 178 electrically coupled to the source / drain region 158A, and a back-side contact 192 electrically coupled to the other source / drain region 158B. The configuration of contacts 178 and 192 may also vary according to design requirements.

[0056] In one embodiment, the back-side contact 192 includes a first sidewall 192A, a second sidewall 192B, a third sidewall 192C, and a fourth sidewall 192D. The first sidewall 192A may extend from the back side 101B of the substrate 101. In some embodiments, the first sidewall 192A is a straight sidewall and extends in a first direction. The second sidewall 192B may extend from the first sidewall 192A to the source / drain region 158. The second sidewall 192B may not extend in the first direction. In some embodiments, the second sidewall 192B is a curved sidewall or a straight sidewall. As shown in Figure 24A, in the transistor structure 100A, the second sidewall 192B is horizontally away from another source / drain region 158B along a vertical direction toward the source / drain region 158A. The third sidewall 192C may extend from the back side 101B of the substrate 101. In some embodiments, the third sidewall 192C is a straight sidewall and extends in the second direction. For example, the first sidewall 192A and the third sidewall 192C may be multiple sidewalls of the opening 191A and opposite to each other. The fourth sidewall 192D is located between the third sidewall 192C and the source / drain region 158A. The fourth sidewall 192D may not extend in the second direction. The fourth sidewall 192D may be a curved sidewall or a straight sidewall. The fourth sidewall 192D may be horizontally adjacent to another source / drain region 158B along a vertical direction toward the source / drain region 158A. In some embodiments, the third sidewall 192C is longer than the first sidewall 192A. In some embodiments, the second sidewall 192B is longer than the fourth sidewall 192D.

[0057] The back contact 192 may also include a first bottom 192E, which connects to the second sidewall 192B and the fourth sidewall 192D. In some embodiments, the back contact 192 also includes a second bottom 192F, which connects to the third sidewall 192C and the fourth sidewall 192D. The first bottom 192E and the second bottom 192F may extend in any direction, such as the horizontal or non-horizontal direction shown in Figure 23A. In one embodiment, the back contact 192 extends into the source / drain region 158, and the first bottom 192E has a curved shape. In some embodiments, depending on the etching profile used to form the opening 191A, the second bottom 192F has a straight or curved shape.

[0058] In some embodiments, each of the back-side contacts 192 includes one or more layers, such as a barrier layer 1921 and a filler material 1922 above the barrier layer 1921. In some embodiments, the barrier layer 1921 of the back-side contacts 192 includes titanium, titanium nitride, tantalum, tantalum nitride, or the like. The filler material 1922 of the back-side contacts 192 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, the back-side contacts 192 also include a siliconized region 193 in contact with the source / drain region 158 to reduce resistance. The siliconized region 193 may be formed between the barrier layer and the source / drain region 158 by reacting the material of the back-side contacts 192 with the semiconductor material of the source / drain region 158. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the back contact 192 above the back side 101B of the substrate 101.

[0059] According to some embodiments, in Figures 25A and 25B, a back-side interconnect structure 195 is formed above the exposed surfaces of the back side 101B and back-side contacts 192 of the substrate 101. The back-side interconnect structure 195 may include conductive features and dielectric layers similar to those of the front-side interconnect structure 183. For example, the back-side interconnect structure 195 may include multiple conductive features 196 stacked in multiple dielectric layers 198. The back-side interconnect structure 195 is formed via a method similar to that of the front-side interconnect structure 183. For example, forming the conductive features 196 may include patterning multiple recesses in the dielectric layer 198, for example, using a combination of photolithography and etching processes. The pattern of the multiple recesses in the dielectric layer 198 may correspond to the pattern of the conductive features 196. The multiple conductive features 196 are then formed by depositing conductive material in these recesses. In some embodiments, the conductive features 196 include a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the conductive feature 196 comprises copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like. An optional diffusion barrier layer and / or optional adhesion layer may be deposited before the recess is filled with the conductive material. Suitable materials for the barrier layer / adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or the like. The conductive feature 196 can be formed using, for example, CVD, ALD, PVD, plating, or the like. The conductive feature 196 is electrically coupled to the source / drain region 158 via a back-side contact 192.

[0060] In some embodiments, conductive feature 196 includes power rails, which are wires that electrically connect source / drain regions 158 to a reference voltage, a supply voltage, or the like. Several advantages are gained by placing the power rails on the back side of the semiconductor device rather than the front side of the semiconductor die. For example, the gate density of semiconductor device 100 and / or the interconnect density of the front-side interconnect structure 183 can be increased. Furthermore, the back side of semiconductor device 100 can accommodate wider power rails, thereby reducing resistance and improving power transfer efficiency to semiconductor device 100. For example, the width of conductive feature 196 can be at least twice the width of the wires in the first layer of the front-side interconnect structure 183.

[0061] In some embodiments, the back-side interconnect structure 195 further includes bump pads for external connections in its top layer. These bump pads for external connections may also be referred to as back-side input / output pads, which can provide signal, power supply voltage, and / or ground connections to the nanostructure transistors. The back-side interconnect structure 195 may include one or more embedded passive devices (not shown), such as resistors, capacitors, inductors, or the like. These embedded passive devices may be integrated with conductive features 196 (e.g., power rails) to provide circuitry (e.g., power circuitry) within the back-side interconnect structure 195.

[0062] Figures 26A through 29B show cross-sectional views of intermediate steps in the fabrication of semiconductor device 200 according to some embodiments. Semiconductor device 200 is similar to semiconductor device 100 and may include any suitable features of semiconductor device 100, wherein the same reference numerals denote the same elements. In semiconductor device 200, an insulating filler 254 extending through substrate 101 is formed to reduce the risk of damage to gate structure 172 and short circuits between back-side contacts and gate structure. The fabrication process of semiconductor device 200 shown in Figures 26A and 26B assumes that the process shown in Figure 5 was previously performed. Accordingly, after the processes discussed above with reference to Figures 1 through 5, the process can proceed to Figures 26A and 26B.

[0063] In Figures 26A and 26B, a first opening 240 with an extended depth may be formed, for example, at least about 3 times larger than the stacking height of the first nanostructure 110 and the second nanostructure 112. In some embodiments, the first opening 240 has a depth of about 250 nanometers to about 350 nanometers.

[0064] Then, a manufacturing process for the semiconductor device 200, referring to Figures 8A to 11B, can be performed, up to Figures 27A and 27B. In Figures 27A and 27B, according to some embodiments, an isolation filler 254 is formed in the first opening 240. In one embodiment, the isolation filler 254 has a top surface that vertically overlaps with the bottommost internal spacer 150. In some embodiments, the isolation filler 254 comprises a material similar to that of the isolation filler 154 and can be formed via a process similar to that used to form the isolation filler 154. The top surface of the isolation filler 254 can be planar, concave, or convex.

[0065] Then, a manufacturing process for the semiconductor device 200, referring to Figures 13A to 20B, can be performed, up to Figures 28A and 28B. According to some embodiments, in Figures 28A and 28B, the substrate 101 is thinned from the back side 101B of the substrate 101, exposing the isolation filler 254. In one embodiment, a portion of the isolation filler 254 is also removed during the thinning process. The exposed surface of the isolation filler 254 may be coplanar with the back side 101B of the substrate 101.

[0066] In Figures 29A and 29B, according to some embodiments, a hard mask 222 is formed over the back side 101B of the substrate 101 and the isolation filler 254, and an opening 223 is formed in the hard mask 222 to expose the isolation filler 254. The hard mask 222 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, other suitable masking materials, combinations thereof, or the like. The hard mask 222 can protect the substrate 101 from damage by subsequent etching processes used to form the back side contacts. One or more suitable lithography and etching processes can be used to form the opening 223 in the hard mask 222. Thus, due to lithography resolution limitations or overlap misalignment, the opening 223 may be laterally misaligned with the source / drain region 158.

[0067] According to some embodiments, in Figures 30A and 30B, a back-side contact 292 is formed in the substrate 101. For example, forming the back-side contact 292 may be achieved by removing an isolation filler 254 from the surface exposed to the opening 223 and depositing the material of the back-side contact 292 into the opening formed by removing the isolation filler 254. The removal of the isolation filler 254 may be the same as the etching process used to form the opening 191B, as shown in Figure 23A. Because the isolation filler 254 is connected to the source / drain region 158, the removal of the isolation filler 254 may create an opening that is self-aligned with the source / drain region 158. Excess material of the back-side contact 292 above the back side 101B on the substrate 101 may be removed via a planarization process, such as chemical mechanical polishing or mechanical polishing. In some embodiments, the hard mask 222 is removed prior to the planarization process. In some embodiments, the back-side contact 292 comprises the same material as the back-side contact 192, and the material for depositing the back-side contact 292 may be processed via a similar process to that used to form the back-side contact 192. For example, each of the back-side contacts 292 may comprise a barrier layer 2921, a filler material 292b above the barrier layer 2922, and a silicon region 293 in contact with the source / drain region 158. Although the above process illustrates the use of a hard mask 222, according to some embodiments, the hard mask 222 may be omitted. For example, the back-side contact 292 may be formed by removing the insulating filler 254 from the surface of the back side 101B exposed to the substrate 101 to create an opening pointing to the source / drain region 158, and depositing conductive material into the opening. Because the isolation filler 254 extends through the substrate 101, the etching process used to form the back contact 292 (e.g., the etching process to form the opening 223) can be kept away from the gate structure 172 and will not damage the gate structure 172.

[0068] As shown in Figure 30A, the back-side contact 292 may include a first sidewall 292A and a second sidewall 292B opposite to each other. The first sidewall 292A and the second sidewall 292B may be straight or curved. In some embodiments, the first sidewall 292A is horizontally further away from the first source / drain region 158A along a vertical direction toward the source / drain region 158B, and the second sidewall 292B is horizontally closer to the source / drain region 158A along a vertical direction toward the source / drain region 158B. In one embodiment, the width of the back-side contact 292 relatively adjacent to the back side 101B of the substrate 101 is smaller than the width of the back-side contact relatively far from the back side 101B of the substrate 101. A back-side interconnect structure 195 may be formed above the back side 101B and the back-side contact 292 of the substrate 101. The conductive features 196 (e.g., power rails) of the back-side interconnect structure 195 can be electrically coupled to the source / drain region 158 via the back-side contacts 292.

[0069] Figures 31A to 34B show cross-sectional views of intermediate steps in the fabrication of a semiconductor device 300 according to some embodiments. The semiconductor device 300 is similar to semiconductor device 100 or 200 and may include any suitable features of semiconductor device 100 or 200, wherein the same reference numerals denote the same elements. In some embodiments, the semiconductor device 300 includes a back-side contact 392 (Figure 34B) formed in a substrate 101, having an extended depth and an enlarged bottom width. When the back-side contact 392 is formed, the enlarged bottom width of the back-side contact 392 can increase the tolerance for microlithography misalignment.

[0070] The manufacturing process of semiconductor device 300, as shown in Figures 31A and 31B, assumes that the processes shown in Figures 7A and 7B have been performed prior to this. Accordingly, after the processes discussed above with reference to Figures 1 through 7B, the process can proceed to Figures 31A and 31B. According to some embodiments, in Figures 31A and 31B, a passivation layer 339 is formed in the first opening 140. The passivation layer 339 may be formed on the sidewall of the first opening 140, while exposing the bottom portion of the first opening 140. For example, a conformal dielectric layer may be deposited in the first opening 140 via a suitable method, such as ALD, PECVD, LPCVD, or other suitable methods. An anisotropic etching process (e.g., RIE, NBE, or a combination thereof) may then be performed to remove the bottom of the conformal dielectric layer, thereby forming the passivation layer 339, including the opening 340 exposing the underlying substrate 101. In one embodiment, a portion of the conformal dielectric layer is adjacent to the top surface of the hard mask 136, while the bottom portion of the conformal dielectric layer is removed.

[0071] According to some embodiments, in Figures 32A and 32B, an isotropic process is performed to etch the substrate 101 beneath the passivation layer 339 through the opening 340, thereby forming an opening 341 with an enlarged bottom width. Because the isotropic process may include lateral etching, the opening 341 may be wider than the bottom width of the first opening 140 (or the bottom width of the opening 340). In some embodiments, the passivation layer 339 is removed after the opening 341 is formed. For example, the passivation layer 339 may be removed via an etching process using an etchant with high selectivity for the passivation layer 339. Although Figure 32A shows a circular cross-section, the opening 341 may include other shapes. For example, the opening 341 may have a triangular or conical shape, as shown in Figure 32C.

[0072] Then, a fabrication process for the semiconductor device 300, referring to Figures 9A to 11B, can be performed, up to Figures 33A and 33B. According to some embodiments, in Figures 33A and 33B, an isolation filler 354 is deposited in the first openings 140 and 341. In one embodiment, the isolation filler 354 has an enlarged bottom width and a top surface that vertically overlaps with the bottommost internal spacer 150. The isolation filler 354 may comprise a material similar to that of the isolation filler 354 and may be formed via a process similar to that used to form the isolation filler 154. The top surface of the isolation filler 354 may be planar, concave, or convex.

[0073] Then, a process for manufacturing the semiconductor device 300 with reference to Figures 13A to 25B can be performed, and the process can proceed to Figures 34A and 34B. In Figures 34A and 34B, according to some embodiments, a back-side contact 392 is formed in the substrate 101. For example, the back-side contact 392 can be formed by a process similar to that for forming the opening 191A, exposing the isolation filler 354 from the back side 101B of the substrate 101, removing the isolation filler 354 by a process similar to that for forming the opening 191B, and then forming the conductive material of the back-side contact 392 in the opening and the space created by removing the isolation filler 354 by a process similar to that for forming the back-side contact 192. For example, each of the back-side contacts 392 may include a barrier layer 3921, a filler material 3922 above the barrier layer 3921, and a siliconized region 393 in contact with the source / drain region 158. In some embodiments, although the opening for exposing the isolation filler 354 may be misaligned with the source / drain region 158, the removal of the isolation filler 354 may extend from the guide opening to align with the source / drain region 158. Furthermore, the enlarged bottom width of the isolation filler 354 may further provide greater tolerance for lithography variations and / or other process variations.

[0074] In some embodiments, the back-side contact 392 includes a first sidewall 392A, a second sidewall 392B, a third sidewall 392C, a fourth sidewall 392D, a fifth sidewall 392E, and a sixth sidewall 392F. The first sidewall 392A may extend from the back side 101B of the substrate 101. In some embodiments, the first sidewall 392A is a straight sidewall and extends in a first direction. The second sidewall 392B may extend to the source / drain region 158. The second sidewall 392B may not extend in the first direction. In some embodiments, the second sidewall 392B may be a curved or straight sidewall and does not extend in the first direction. In one embodiment, the second sidewall 392B is horizontally away from another source / drain region 158A along a vertical direction toward the source / drain region 158B. The third sidewall 392C may extend from the back side 101B of the substrate 101. In some embodiments, the third sidewall 392C is a straight sidewall and extends in the second direction. For example, the first sidewall 392A and the third sidewall 392C may be sidewalls opposite to each other. The fourth sidewall 392D is located between the third sidewall 392C and the source / drain region 158A. The fourth sidewall 392D may not extend in the second direction. For example, the fourth sidewall 392D may be horizontally adjacent to another source / drain region 158A along a vertical direction toward the source / drain region 158B. In some embodiments, the third sidewall 392C is longer than the first sidewall 392A. In some embodiments, the second sidewall 392B is longer than the fourth sidewall 392D. The fifth sidewall 392E may connect the first sidewall 392A and the second sidewall 392B. The fifth sidewall 392E may be a curved sidewall. The sixth sidewall 392F may be located between the third sidewall 392C and the fourth sidewall 392D. The sixth sidewall 392F may be a curved sidewall. In some embodiments, the sixth sidewall 392F may be horizontally away from another source / drain region 158B along a vertical direction toward the source / drain region 158B.

[0075] The back contact 392 may also include a first bottom 392G, which connects to the second sidewall 392B and the fourth sidewall 392D. In some embodiments, the back contact 392 also includes a second bottom 392H, which connects to the third sidewall 392C and the sixth sidewall 392F. The first bottom 392G and the second bottom 392H may extend in any direction, such as the horizontal or non-horizontal direction shown in Figure 34A. In one embodiment, the back contact 392 extends into the source / drain region 158, and the first bottom 392G has a curved shape. In some embodiments, depending on the etching profile used to form the opening 191A, the second bottom 392H has a straight or curved shape.

[0076] Figures 35A and 35B show cross-sectional views of a semiconductor device 400 according to some embodiments. Semiconductor device 400 is similar to semiconductor devices 100, 200, or 300 and may include any suitable features of semiconductor devices 100, 200, or 300, wherein like reference numerals denote like elements. Semiconductor device 400 may include a dielectric layer 403 between the bottommost gate structure 172 and the substrate 101. Forming dielectric layer 403 may be achieved by providing a dielectric layer between the bottommost second semiconductor layer 106 and the substrate 101 in a multilayer stack 102 and patterning it with a first semiconductor layer 104 and a second semiconductor layer 106. Dielectric layer 403 may include a dielectric material different from the isolation filler 154, such that dielectric layer 403 is substantially not etched when the isolation filler 154 is removed. Dielectric layer 403 may act as a buffer layer to prevent the etching process used to form openings 191A and / or 191B from damaging the gate structure 172. For example, the semiconductor device 400 can be manufactured using the process shown in Figures 2 through 25B. The etching process used to form the opening 191A may not require timing pattern etching.

[0077] Figures 36A and 36B show cross-sectional views of a semiconductor device 500 according to some embodiments. Semiconductor device 500 is similar to semiconductor device 400 and may include any suitable features of semiconductor device 400, wherein the same reference numerals denote the same elements. In some embodiments, the isolation filler 154 is omitted when the dielectric layer 403 can provide sufficient protection for the gate structure during the formation of the back-side contact 192. The back-side contact 592 may include a material similar to the back-side contact 192, such as including a barrier layer 5921, a filler material 5922 above the barrier layer 5921, and a siliconized region 593. The back-side contact 592 may be formed by etching through the substrate 101 from the back side 101B of the substrate 101 via an anisotropic etching process (e.g., RIE, NBE, or similar). Although the back contact 592 may overlap with the gate structure 172 due to process variations (e.g., lithography errors), the back contact 592 will not damage the gate structure 172 due to the protection of the dielectric layer 403.

[0078] Figures 37 through 40B show perspective and cross-sectional views of a semiconductor device 600 according to some embodiments. Semiconductor device 600 is similar to semiconductor device 100 and may include any suitable features of semiconductor devices 200 through 500, wherein like reference numerals denote like elements. In Figure 37, according to some embodiments, substrate 601 is similar to substrate 101 and also includes a first epitaxial layer 609 and a second epitaxial layer 611 disposed beneath a multilayer stack 102. The first epitaxial layer 609 may comprise a material similar to a second semiconductor material, such as SiGe, similar to a second semiconductor layer 106, and the second epitaxial layer 611 may comprise a material similar to a first semiconductor material, such as Si, similar to a first semiconductor material, similar to a first semiconductor material, similar to a first semiconductor layer 104. In Figure 38, a process similar to that shown in Figures 2 through 4 is then performed, and fins 114 are formed between adjacent plurality of isolation structures 120. In some embodiments, each fin 114 includes a first epitaxial layer 609 and a second epitaxial layer 611.

[0079] According to some embodiments, a process similar to that shown in Figures 5 through 21B is performed, and the resulting structure of the semiconductor device 600 is shown in Figures 39A and 39B. A first epitaxial layer 609 can be used as an etch top layer for a substrate thinning process. Therefore, the remaining thickness of the substrate 101 can be determined by the location of the first epitaxial layer 609. In some embodiments, a portion of the isolation region 120 is also removed. According to some embodiments, a process similar to that shown in Figures 22A through 25B is performed, and the resulting structure of the semiconductor device is shown in Figures 40A and 40B. The first epitaxial layer 609 can further be used as a hard mask to form an opening 191 for the back-side contact 192. In some embodiments, the first epitaxial layer 609 can be consumed during the formation of the opening 191 or removed via an etching process after the opening 191 is formed.

[0080] Embodiments of this disclosure provide a semiconductor device including a self-aligned back-side contact formed in a substrate and electrically coupled to a source / drain region. The self-aligned back-side contact, formed in a self-aligned manner, can effectively reduce the risk of damage to the gate structure or the risk of a short circuit forming between the back-side contact and the gate structure. In some embodiments, the formation of the self-aligned back-side contact includes etching an isolation filler formed between the substrate and the source / drain region, and the aforementioned risks can also be reduced by changing the shape of the isolation filler or by adding a dielectric layer between the substrate and the gate structure.

[0081] One embodiment is a semiconductor device including a substrate having a front side and a back side opposite to the front side of the substrate; a channel region disposed between a first source / drain region and a second source / drain region and above the front side of the substrate; a gate structure disposed above the channel region; and a first contact disposed in the substrate, wherein the first contact includes a first sidewall extending from the back side of the substrate and a second sidewall extending to the first source / drain region, wherein the first sidewall and the second sidewall are on the same side of the first contact, and wherein the second sidewall is horizontally further away from the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region. In one embodiment, the first sidewall is horizontally closer to the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region. In one embodiment, the first sidewall is a straight sidewall, and the second sidewall is a curved sidewall. In one embodiment, the first contact further includes a third sidewall, a fourth sidewall, and a first bottom connecting the third and fourth sidewalls, wherein the third sidewall extends from the back side of the substrate, and the fourth sidewall extends to the first source / drain region. In one embodiment, the fourth sidewall is horizontally closer to the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region. In one embodiment, the semiconductor device further includes an isolation filler disposed between the second source / drain region and the substrate. In one embodiment, the semiconductor device further includes a second contact disposed above the front side of the second source / drain region and electrically coupled to the second source / drain region. In one embodiment, a portion of a gate structure is disposed between the substrate and the channel region, wherein the semiconductor device further includes a dielectric layer disposed between the portion of the gate structure and the substrate.

[0082] Another embodiment is a semiconductor device comprising: a substrate having a front side and a back side opposite to the front side of the substrate; a channel region disposed above the front side of the substrate and between a first epitaxial region and a second epitaxial region; a gate structure disposed above the channel region; a back-side contact disposed in the substrate, wherein the back-side contact includes a first sidewall extending from the back side of the substrate, a second sidewall extending to the first epitaxial region, a third sidewall opposite to the first sidewall, and a fourth sidewall opposite to the second sidewall, wherein the second and third sidewalls are horizontally further away from the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region; a front-side contact disposed above the front side of the substrate and electrically coupled to the second epitaxial region; and a back-side interconnect structure disposed above the back side of the substrate and including a conductive feature electrically coupled to the first epitaxial region through the back-side contact. In one embodiment, the fourth sidewall overlaps with the gate structure in a plan view. In one embodiment, the first and fourth sidewalls are closer to the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region. In one embodiment, the back-side contact further includes a fifth sidewall connecting the first and second sidewalls. In one embodiment, the fifth sidewall is a curved sidewall. In one embodiment, the back-side contact further includes a sixth sidewall connected to the fourth sidewall, and a first bottom connecting the third and sixth sidewalls. In one embodiment, the semiconductor device further includes an isolation filler disposed between the substrate and the second epitaxial region.

[0083] Another embodiment is a method of forming a semiconductor device. The method includes: forming a channel region between a first source / drain region and a second source / drain region and above a front side of a substrate, wherein the substrate includes a back side opposite to the front side of the substrate; forming a gate structure above the channel region; and forming a first contact in the substrate, wherein the first contact includes a first sidewall extending from the back side of the substrate and a second sidewall extending to the first source / drain region, wherein the first sidewall and the second sidewall are on the same side of the first contact, and wherein the second sidewall is horizontally further away from the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region. In one embodiment, forming a first contact includes: forming a first opening extending from the front side of a substrate into the substrate; forming a first insulating filler in the first opening; forming a first source / drain region in the first opening and above the first insulating filler; performing a first etching process from the back side of the substrate to form a second opening exposing the first insulating filler; performing a second etching process to etch the first insulating filler from the second opening and form a third opening exposing the first source / drain region; and depositing a conductive material in the second and third openings. In one embodiment, the method further includes: forming a fourth opening extending from the front side of the substrate into the substrate; forming a second insulating filler in the fourth opening while forming the first insulating filler; and forming a second source / drain region in the fourth opening and above the second insulating filler, wherein the second insulating filler is not etched when forming the first contact. In one embodiment, the method further includes forming a second contact disposed above the front side of the substrate and electrically coupled to the second source / drain region. In one embodiment, a first sidewall is horizontally closer to the second source / drain region along a vertical direction from the back side of the substrate toward the first source / drain region.

[0084] The foregoing outlines several features of various embodiments, enabling those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for the design or modification of other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0085] 100: Semiconductor devices 100A: Transistor Structure 101:Substrate 101B: Dorsal side 101F: Front 102: Multi-layer stacking 104: First semiconductor layer 106: Second semiconductor layer 108: Semiconductor Strip 110: First nanostructure 112: Second nanostructure 114: Fins 116: Trench 118: Insulating materials 120: Isolation area (isolation structure) 130: Virtual gate structure 132: Dummy gate dielectric 134: Dummy gate electrode 136: Hard Mask 138: Gate spacer 140: First Opening 142: Second opening 144: Insulation layer 150: Internal spacers 154: Isolation filler 158: Source / Drain Region 158A: Source / Drain Region 158B: Source / Drain Region 160: Contact Etching Stop Layer 162: First interlayer dielectric layer 164: Third opening 168: Gate Dielectric Layer 170: Gate electrode 172: Gate Structure 174: Second interlayer dielectric layer 176: Contact Etching Stop Layer 178: Contacts 180: Contact 182: Silicone region 183: Front interconnect structure 184: Electrical conductivity characteristics 186: Dielectric layer 188: Carrier substrate 190: Bonding layer 191: Opening 191A: Opening 191B: Opening 192: Back side contact (contact) 192A: First sidewall 192B: Second sidewall 192C: Third lateral wall 192D: Fourth lateral wall 192E: First bottom 192F: Second bottom 1921: Barrier Layer 1922: Filling material 193: Silicone region 195: Backside interconnect structure 196: Electrical conductivity characteristics 198: Dielectric layer 200: Semiconductor devices 222: Hard Mask 223: Opening 240: First Opening 254: Isolation filler 292: Back side contact 292A: First sidewall 292b: Filler material 292B: Second sidewall 2921: Barrier Layer 2922: Barrier Layer 293: Silicone region 300: Semiconductor Devices 339: Passivation layer 340: Opening 341: Opening 354: Isolation filler 392: Back side contact 392A: First sidewall 392B: Second sidewall 392C: Third sidewall 392D: Fourth sidewall 392E: Fifth sidewall 392F: Sixth sidewall 392G: First Bottom 392H: Second bottom 3921: Barrier Layer 3922: Filler material 393: Silicone region 400: Semiconductor Devices 403: Dielectric layer 500: Semiconductor Devices 592: Back side contact 5921: Barrier Layer 5922: Filler material 593: Silicon region 600: Semiconductor Devices 601:Substrate 609: First epitaxial layer 611: Second epitaxial layer AA: Section BB: Section X: Direction Y: direction Z: Direction

[0086] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a substrate having a front side and a back side opposite to the front side of the substrate; a channel region disposed between a first source / drain region and a second source / drain region and above the front side of the substrate; a gate structure disposed above the channel region; a first contact disposed in the substrate, wherein the first contact includes a first sidewall extending from the back side of the substrate and a second sidewall extending to the first source / drain region, wherein the first sidewall and the second sidewall are on the same side of the first contact; and an isolation filler disposed directly below the second source / drain region and between the second source / drain region and the substrate, wherein the isolation filler electrically isolates the second source / drain region and the substrate.

2. The semiconductor device as described in claim 1, wherein, The first sidewall extends horizontally toward the second source / drain region along the vertical direction from the back side of the substrate toward the first source / drain region.

3. The semiconductor device as claimed in claim 1, wherein the first contact further includes a third sidewall, a fourth sidewall, and a first bottom connecting the third sidewall and the fourth sidewall, wherein the third sidewall extends from the back side of the substrate, and the fourth sidewall extends to the first source / drain region.

4. The semiconductor device as claimed in claim 1, wherein the isolation filler comprises a dielectric material.

5. The semiconductor device as claimed in claim 1, wherein a portion of the gate structure is disposed between the substrate and the channel region, wherein the semiconductor device further includes a dielectric layer disposed between the portion of the gate structure and the substrate.

6. A semiconductor device comprising: a substrate having a front side and a back side opposite to the front side of the substrate; a channel region disposed above the front side of the substrate and between a first epitaxial region and a second epitaxial region; a gate structure disposed above the channel region; a back side contact disposed in the substrate, wherein the back side contact includes a first sidewall extending from the back side of the substrate, a second sidewall extending to the first epitaxial region, a third sidewall opposite to the first sidewall, and a fourth sidewall opposite to the second sidewall, wherein the second sidewall and the third sidewall are horizontally further away from the second epitaxial region along a vertical direction from the back side of the substrate toward the first epitaxial region; and a front side contact disposed above the front side of the substrate and electrically coupled to the second epitaxial region. An isolation filler is disposed directly below the front contact and the second epitaxial region and between the second epitaxial region and the substrate, wherein the isolation filler electrically isolates the second epitaxial region and the substrate; and a back-side interconnect structure is disposed above the back side of the substrate and includes a conductive feature that is electrically coupled to the first epitaxial region through the back-side contact.

7. The semiconductor device as described in claim 6, wherein, In a plan view, the third sidewall overlaps with the gate structure.

8. A method of forming a semiconductor device, the method comprising: forming a channel region between a first source / drain region and a second source / drain region and over a front side of a substrate, wherein the substrate includes a back side opposite to the front side of the substrate; forming a gate structure over the channel region; forming an isolation filler in the substrate, wherein the isolation filler is disposed directly below the second source / drain region and between the substrate and the second source / drain region, and the isolation filler electrically isolates the second source / drain region and the substrate; and forming a first contact in the substrate, wherein the first contact includes a first sidewall extending from the back side of the substrate and a second sidewall extending to the first source / drain region, wherein the first sidewall and the second sidewall are on the same side of the first contact.

9. A method of forming a semiconductor device as claimed in claim 8, wherein forming the first contact comprises: forming a first opening extending from the front side of the substrate into the substrate; forming a further insulating filler in the first opening; forming a first source / drain region in the first opening and over the further insulating filler; performing a first etching process from the back side of the substrate to form a second opening exposing the further insulating filler; performing a second etching process to etch the further insulating filler from the second opening and form a third opening exposing the first source / drain region; and depositing a conductive material in the second opening and the third opening.

10. The method of forming a semiconductor device as claimed in claim 9, further comprising: forming a fourth opening extending from the front side of the substrate into the substrate; forming the isolation filler in the fourth opening while forming the other isolation filler; and forming the second source / drain region in the fourth opening and over the isolation filler, wherein the isolation filler is not etched when the first contact is formed.

Images