Method of manufacturing semiconductor devices and apparatus for manufacturing semiconductor device

Abstract

This disclosure describes a method for manufacturing semiconductor devices, the manufactured semiconductor devices, and apparatus for forming the semiconductor devices, wherein byproducts from an etching process are heated separately and independently from a semiconductor wafer. In an embodiment, a dielectric material is deposited into a trench above a semiconductor substrate, and the dielectric material is recessed by an etching process. The etching process includes heating the semiconductor substrate and separately heating a byproduct of the etching process.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit elements and components on them.

[0003] The semiconductor industry has improved the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. As the semiconductor industry further advances towards increased device density, higher efficiency, and lower cost, challenges from both manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). However, as the minimum feature size is reduced, additional features are introduced. [Summary of the Invention]

[0004] None

Implementation Method

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, spatial relative terms, such as “under,” “below,” “lower,” “overlapping,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0008] Examples Specific embodiments relating to the use of etching process byproducts in the fabrication of complementary field-effect transistor (CFET) structures, independent of the heating of the semiconductor wafer, will now be described. However, the embodiments described herein are intended to illustrate the presented concepts and are not intended to limit the embodiments to the precise descriptions presented. Rather, the concepts can be implemented in a wide range of processes and apparatuses, and all processes and apparatuses are fully intended to be included within the scope of the embodiments.

[0009] Figure 1 illustrates an example of a stacked transistor 10 (including FETs (transistors) 10U and 10L) according to some embodiments. Figure 1 is a three-dimensional view, and some features of the stacked transistor 10 are omitted for clarity of illustration.

[0010] The stacked transistor 10 includes a plurality of vertically stacked FETs. For example, the stacked transistor 10 may include a lower nanostructure FET 10L of a first device type (n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor 10 is a CFET, the second device type of the upper nanostructure FET 10U is the opposite of the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 acts as a channel region of the nanostructure FET. The lower semiconductor nanostructure 26L refers to the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U refers to the upper nanostructure FET 10U. In other embodiments, the stacked transistor 10 may be applied to other types of transistors (e.g., finFET or similar).

[0011] A gate dielectric 78 surrounds each semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are positioned above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and each gate electrode 80. Each of the source / drain regions 62 refers individually or collectively to a source or drain depending on the context. Isolation features (not shown) may be formed to separate the desired source / drain regions in the source / drain regions 62 and / or the desired gate electrode of the gate electrode 80.

[0012] In Figure 2, a wafer including a semiconductor substrate 20 is provided. The semiconductor substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, and the substrate may be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or similar, or combinations thereof.

[0013] Semiconductor strips 28 are formed, thereby extending upward from the semiconductor substrate 20. Each of the semiconductor strips 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multilayer stack 22. The stacked elements of the multilayer stack 22 are hereinafter referred to as nanostructures. Specifically, the multilayer stack 22 includes dummy nanostructures 24A, dummy nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Dummy nanostructures 24A and dummy nanostructures 24B can be further collectively referred to as dummy nanostructure 24, and the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0014] The dummy nanostructure 24A is formed of a first semiconductor material, and the dummy nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first semiconductor material and the second semiconductor material can be selected from candidate semiconductor materials of the semiconductor substrate 20. The first semiconductor material and the second semiconductor material have high etch selectivity relative to each other. Therefore, the dummy nanostructure 24B can be removed at a faster rate in subsequent processes compared to the dummy nanostructure 24A.

[0015] The semiconductor nanostructure 26 (including the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material may be selected from candidate semiconductor materials of the semiconductor substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U may be formed of the same semiconductor material or may be formed of different semiconductor materials. In addition, the first and second semiconductor materials of the dummy nanostructure 24 have high etch selectivity for the third semiconductor material of the semiconductor nanostructure 26. Therefore, the dummy nanostructure 24 may be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the dummy nanostructure 24A is formed of or contains silicon germanium, the semiconductor nanostructure 26 is formed of silicon, and the dummy nanostructure 24B may be formed of germanium or silicon germanium with a higher percentage of germanium atoms than the dummy nanostructure 24A.

[0016] The lower semiconductor nanostructure 26L will provide the channel region for the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 26U will provide the channel region for the upper nanostructure FET of the CFET. The semiconductor nanostructure 26 just above / below (e.g., in contact with the dummy nanostructure 24B) can be used for isolation and may or may not act as the channel region of the CFET. The dummy nanostructure 24B will then be replaced by isolation structures that define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0017] To form the semiconductor strip 28, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer (configured as illustrated and described above) may be deposited over the semiconductor substrate 20. The first, second, and third semiconductor material layers may be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) or similar. A patterning process may then be applied to the first, second, and third semiconductor material layers and the semiconductor substrate 20 to define the semiconductor strip 28, the semiconductor substrate 20 including the semiconductor strip 20', the dummy nanostructure 24, and the semiconductor nanostructure 26.

[0018] Semiconductor fins and nanostructures can be patterned by any suitable method. For example, the patterning process may include one or more optical lithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning or multi-patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated having a spacing, for example, smaller than the spacing obtained by otherwise using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer, as well as the semiconductor substrate 20. Etching can be performed by any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. Etching can be anisotropic.

[0019] As illustrated in Figure 2, an STI region 32 is formed over the semiconductor substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric liner and a dielectric material above the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, the like, or a combination thereof. Forming the STI region 32 may include depositing a dielectric layer and performing a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, or the like, to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process followed by an annealing process. The dielectric material is then recessed to define the STI region 32. The dielectric layer can be recessed so that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0020] After the STI region 32 is formed, a dummy gate stack 42 may be formed over the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32) and along the sidewalls of those portions. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or comprise, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, via physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The dummy gate layer 38 is made of a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium (polycrystalline SiGe), or similar materials. A mask layer 40 is formed over the planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, or similar materials. The mask layer 40 may then be patterned via optical lithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38 and may dummy dielectric layer 36. The remaining portions of the mask layer 40, dummy gate layer 38, and dummy dielectric layer 36 form a dummy gate stack 42.

[0021] In Figure 3, a gate spacer 44 and a source / drain recess 46 or trench are formed. First, the gate spacer 44 is formed above the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric materials and subsequently anisotropically etching the dielectric materials. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by deposition processes such as CVD, ALD, or the like.

[0022] Subsequently, a source / drain recess 46 is formed in the semiconductor strip 28. The source / drain recess 46 is formed by etching and can extend through the multilayer stack 22 and into the semiconductor strip 20'. The bottom surface of the source / drain recess 46 can be positioned above, below, or flush with the top surface of the STI region 32. During the etching process, the gate spacer 44 and the dummy gate stack 42 shield portions of the semiconductor strip 28. The etching may include a single etching process or multiple etching processes. A timing etching process can be used to stop the etching of the source / drain recess 46 after it has reached the desired depth.

[0023] In Figure 4, an internal spacer 54 and a dielectric isolation layer 56 are formed. Forming the internal spacer 54 and the dielectric isolation layer 56 may include an etching process that laterally etches the dummy nanostructure 24A and removes the dummy nanostructure 24B. The etching process may be isotropic and selective for the material of the dummy nanostructure 24, allowing the dummy nanostructure 24 to be etched at a faster rate than the semiconductor nanostructure 26. The etching process is also selective for the material of the dummy nanostructure 24B, allowing the dummy nanostructure 24B to be etched at a faster rate than the dummy nanostructure 24A. In this manner, the dummy nanostructure 24B can be completely removed from between the lower semiconductor nanostructure 26L (common) and the upper semiconductor nanostructure 26U (common), without completely removing the dummy nanostructure 24A. In some embodiments where the dummy nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the dummy nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 26 is formed of silicon without germanium. The etching process may include a dry etching process using chlorine gas with or without plasma. Because the dummy gate stack 42 covers the sidewalls of the semiconductor nanostructure 26 (see Figure 2), the dummy gate stack 42 can support the upper semiconductor nanostructure 26U so that the upper semiconductor nanostructure 26U does not collapse after the dummy nanostructure 24B is removed. Furthermore, although the sidewalls of the dummy nanostructure 24A are illustrated as straight after being recessed, the sidewalls may be recessed or convex.

[0024] An internal spacer 54 is formed on the sidewall of the recessed dummy nanostructure 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (common) and the lower semiconductor nanostructure 26L (common). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the dummy nanostructure 24A will be replaced with a corresponding gate structure. The internal spacer 54 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. In addition, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as etching processes used to form the gate structure. On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (common) and the lower semiconductor nanostructure 26L (common). In addition, the intermediate semiconductor nanostructure (one of the semiconductor nanostructures 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0025] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewall of the dummy nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonitride, silicon oxycarbide, silicon oxynitride, or the like. Other low dielectric constant (low k) materials with a k value of less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, or the like. The etched insulating material can be anisotropic or isotropic. The insulating material has a portion remaining in the sidewalls of the dummy nanostructure 24A during etching (thus forming an internal spacer 54), and a portion remaining between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming a dielectric isolation layer 56).

[0026] As shown in Figure 4, a lower epitaxial source / drain region 62L is formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U (not shown in Figure 4, but further illustrated and discussed below in Figure 7). The internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy nanostructure 24A, which will be replaced by a replacement gate in subsequent processes.

[0027] The lower epitaxial source / drain region 62L is epitaxially grown and has a conduction type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the individual materials may include silicon or carbon-doped silicon, with the carbon-doped silicon doped with an n-type dopant such as phosphorus, arsenic, or the like. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the individual materials may include silicon or silicon-germanium, with the silicon-germanium doped with a p-type dopant such as boron, indium, or the like. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not have corresponding p-type or n-type dopant implanted. During epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructure 26U. After the lower epitaxial source / drain region 62L has grown, the mask on the upper semiconductor nanostructure 26U may then be removed.

[0028] As a result of the epitaxial process used to form the lower epitaxial source / drain region 62L, the upper surface of the lower epitaxial source / drain region 62L has facets that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0029] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 may be formed of a dielectric material with high etch selectivity for etching the first ILD 68, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The first ILD 68 may be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The suitable dielectric material for the first ILD 68 may include silicon oxide, SiOC, SiON, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials. The formation process may include depositing a conformal CESL layer, depositing the material for the first ILD 68, followed by a planarization process.

[0030] Figure 5A illustrates a first recessed portion of the first ILD 68. In embodiments, the first ILD 68 may be recessed using one or more etching processes (indicated by the arrow marked 501 in Figure 5A) that use a single etchant or a combination of multiple etchants selective for the material of the first ILD 68. Thus, while the precise etchant used will depend at least in part on the material of the first ILD 68, in certain embodiments where the first ILD 68 comprises silicon oxide, etchants such as hydrofluoric acid (HF) and ammonium (NH3) may be used to recess the material of the first ILD 68. However, any suitable etchant may be used.

[0031] The etching process 501 can be initiated by placing the semiconductor substrate 20 into the etching system 500, as illustrated in Figure 5B. In some embodiments, the etching system 500 may include an etchant delivery system 503, which delivers one or more gaseous etchants to the etching chamber 504. The etchant delivery system 503 supplies various desired etchants to the etching chamber 504 via an etchant controller 513 and a manifold 505. The etchant delivery system 503 can also help control the flow rate of the etchant to the etching chamber 504 by controlling the flow and pressure of the carrier gas passing through the etchant delivery system 503.

[0032] In an embodiment, the etchant delivery system 503 may include a plurality of etchant supply sources 511 together with a carrier gas supply source 507. Although only two etchant supply sources 511 are illustrated in Figure 5B, this is for clarity only, as any suitable number of etchant supply sources 511 may be used, such as one etchant supply source 511 for each etchant required within the etching system 500. For example, in an embodiment where five separate etchants will be used, five etchant supply sources 511 may be present.

[0033] Each of the etchant supply sources 511 may be a container, such as a gas storage tank, located locally or remotely from the etching chamber 504. In other embodiments, the etchant supply source 511 may be a facility that independently prepares and delivers the etchant to be used. Any suitable source of the etchant to be used may be used as the etchant supply source 511, and all such sources are sufficiently intended to be included within the scope of the embodiments.

[0034] In some embodiments, each of the etchant supply sources 511 supplies etchant to the etchant controller 513 via a first line 502 and a first valve 508. The first valve 508 is controlled by a controller 528, which controls and regulates the introduction of various etchants and carrier gases into the etching chamber 504.

[0035] The carrier gas supply source 507 can supply the desired carrier gas or dilution gas to the etching chamber 504, which can be used to help propel or "carry" various desired etchants. The carrier gas can be an inert gas or other gas that does not react with the etchant itself or with byproducts of the reaction from the etchant. For example, the carrier gas can be nitrogen (N2), helium (He), argon (Ar), combinations of these or similar, although other suitable carrier gases can be used.

[0036] The carrier gas supply source 507 or diluent supply source may be a container, such as a gas storage tank, located locally or remotely from the etching chamber 504. In other embodiments, the carrier gas supply source 507 may be a facility that independently prepares and delivers carrier gas to the etchant controller 513. Any suitable source of carrier gas may be used as the carrier gas supply source 507, and all such sources are sufficiently intended to be included within the scope of the embodiments. The carrier gas supply source 507 may supply the desired carrier gas to the etchant controller 513 via a second line 510 and a second valve 506, the second line 510 connecting the carrier gas supply source 507 to the first line 502. The second valve 506 is also controlled by a controller 528, which controls and regulates the introduction of various etchants and carrier gases into the etching chamber 504. Once assembled, wiring can be routed toward the etchant controller 513 for controlled introduction into the etching chamber 504.

[0037] The etching chamber 504 can be any desired shape suitable for applying the etchant and bringing the etchant into contact with the semiconductor substrate 20. In the embodiment illustrated in Figure 5B, the etching chamber 504 has cylindrical sidewalls and a bottom. However, the etching chamber 504 is not limited to a cylindrical shape and can utilize any other suitable shape, such as a hollow square conduit, an octagonal shape, or the like. Furthermore, the etching chamber 504 can be surrounded by an etchant chamber housing 515 made of a material inert to various process materials. Thus, while the etchant chamber housing 515 can be any suitable material that can withstand the chemicals and pressures involved in the etching process, in some embodiments, the etchant chamber housing 515 can be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, and the like.

[0038] Additionally, the etching chamber 504 and the mounting platform 545 may be part of a clustering tooling system (not shown). The clustering tooling system can be used in conjunction with an automated processing system to position and place the semiconductor substrate 20 into the etching chamber 504 before the etching process, position and hold the semiconductor substrate 20 during the etching process, and remove the semiconductor substrate 20 from the etching chamber 504 after the etching process.

[0039] The etching chamber 504 is positioned on the mounting platform 545 to position and control the semiconductor substrate 20 during the etching process. The mounting platform 345 may use electrostatic force, clamps, vacuum pressure, combinations of the above or the like to hold the semiconductor wafer 100, and may also include heating and cooling mechanisms to control the temperature of the semiconductor substrate 20 during the process.

[0040] Additionally, the mounting platform 545 may include one or more first heating elements 530 for raising and controlling the temperature of the semiconductor substrate 20 during the etching process. In embodiments, the one or more first heating elements 530 may be resistance heaters or other types of heaters to help control and maintain the temperature. However, any suitable type of heating element may be used.

[0041] In some embodiments, the etching chamber 504 includes a nozzle 532. In embodiments, the nozzle 532 receives various etchants from the manifold 505 and facilitates the distribution of these etchants into the etching chamber 504. The nozzle 532 may be designed to uniformly distribute the etchant in order to minimize undesirable process conditions that may result from non-uniform distribution. In one embodiment, the nozzle 532 may have a circular design with a plurality of openings uniformly distributed around the nozzle 532 to allow the distribution of the desired etchant into the etching chamber 504. However, any suitable method, such as an inlet port, may be used to introduce the desired etchant into the etching chamber 504.

[0042] The etching chamber 504 can also be connected to a vacuum pump 525. In this embodiment, the vacuum pump 525 is controlled by a controller 528 and can be used to control the pressure inside the etching chamber 504 to the desired compressive stress. In addition, once the etching process is complete, the vacuum pump 525 can be used to prepare to empty the etching chamber 504 to remove the semiconductor substrate 20.

[0043] In addition, while several specific portions of the etching system 500 have been described above, other suitable portions may also be included. For example, end-mounts, liners, and any other portions that may facilitate operation or control of the etching process may also be included. All such portions are fully intended to be included within the scope of the embodiments.

[0044] To begin recessing the first ILD 68, the process can be initiated by placing the semiconductor substrate 20 onto the mounting platform 545. Once the semiconductor substrate 20 is placed on the mounting platform 545, it can be attached to the mounting platform 545 using an attachment process. In an embodiment where the mounting platform 545 is an electrostatic chuck, the semiconductor substrate 20 can be attached to the mounting platform 545 by applying a first current (e.g., alternating current), such that electrostatic forces will apply force to hold the semiconductor substrate 20 to the attachment surface of the mounting platform 545.

[0045] Once the semiconductor substrate 20 has been placed and attached to the mounting platform 545, the controller 528 can initiate the indentation process by setting the temperature of the semiconductor substrate 20 using the first heating component 530. In an embodiment, the first heating component 530 can be used to adjust the temperature between -60°C and approximately 80°C. However, any suitable temperature can be used.

[0046] Once the temperature has been set using the first heating component 530, the controller 528 can connect one or more of the etchant supply sources 511 and one of the carrier gas supply sources 507 to the etching chamber 504 to introduce the first etch combination of etchant (e.g., hydrofluoric acid (HF) and ammonium (NH3)) to the semiconductor substrate 20. In embodiments where hydrofluoric acid and ammonium are used to recess the first ILD 68, when the first ILD 68 contains silicon oxide, the etching process can proceed according to the following chemical reaction: as can be seen, the silicon oxide will react with the etchant to form silicon fluoride (SiF4) and water, thereby removing material from the structure of the first ILD 68.

[0047] However, the above-described reaction is not the only reaction occurring during the removal process, and other side reactions may occur, in which undesired byproducts 531 and / or salts may be generated and remain within the source / drain recess 46 and on the surface of the semiconductor substrate 20. As an example of such a side reaction, silicon fluoride generated in the main reaction may continue to react according to the following chemical formula: such a side reaction will generate undesired byproduct 531, such as ammonium hexafluorosilicate (AFS). Furthermore, this byproduct 531 will be generated as a solid within the source / drain recess 46 being generated. Unless this situation is improved, the solid form of ammonium hexafluorosilicate will interfere with other etching processes and may cause significant variations in the depth formed within the source / drain recess 46.

[0048] Therefore, as illustrated in Figures 6A to 6B, a secondary heating assembly 527 is included within the etching chamber 504 to assist in the removal of unwanted byproducts 531 (e.g., ASF) so that the byproducts 531 do not interfere with the remainder of the removal process 501. In one particular embodiment, the secondary heating assembly 527 includes a laser device that can output a laser beam 529 toward the semiconductor substrate 20, and more precisely, can output the laser beam 529 toward the unwanted byproducts 531 located within the source / drain recess 46. In some embodiments, the secondary heating assembly 527 may have an tunable orientation to tune the angle of incidence of the laser beam 529 striking the semiconductor substrate 20.

[0049] In an embodiment, the laser beam 529 is also tunable, such that the laser beam 529 includes light of one or more wavelengths that assist in the decomposition of the unwanted byproduct 531. For example, in an embodiment where the unwanted byproduct 531 is an AFS, the laser beam 529 includes light following a spectrum, wherein the light following the spectrum is absorbed by bonds present within the AFS (e.g., the AFS absorption spectrum). By using this spectrum, when the laser beam 529 strikes the AFS, the decomposition of the AFS is facilitated by inducing decomposition according to the following chemical formula: By using the laser beam 529, the unwanted byproduct 531 can be more easily removed during the recess of the first ILD 68. Therefore, in the absence of byproduct 531, the byproduct 531 does not interfere with the remainder of the etching process 501, and the variation between the different source / drain recesses 46 can be reduced.

[0050] As shown in Figure 7, once the first ILD 68 has been recessed, an anisotropic etching process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0051] The upper epitaxial source / drain region 62U is then formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. Depending on the desired conduction type of the upper epitaxial source / drain region 62U, the material of the upper epitaxial source / drain region 62U may be selected from the same group of candidate materials as the material used to form the lower epitaxial source / drain region 62L. In embodiments where the stacked transistor is a CFET, the conduction type of the upper epitaxial source / drain region 62U may be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U may be doped in the opposite manner to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L may have the same conduction type. The upper epitaxial source / drain region 62U may be in-situ doped and / or may be implanted with p-type or n-type dopants. Adjacent upper epitaxial source / drain regions 62U may remain separate after the epitaxial process or may be merged.

[0052] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods may be similar to those of the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail herein. The formation process may include depositing layers of CESL 70 and the second ILD 72, and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or dummy gate layer 38 is exposed via the second ILD 124. In the illustrated embodiment, the mask 40 remains after the removal process. In other embodiments, the mask 40 is removed such that the top surface of the dummy gate layer 38 is exposed via the second ILD 72.

[0053] Figure 8 illustrates a gate replacement process to replace the dummy gate stack 42 and dummy nanostructure 24A with a gate stack 90. ​​The gate replacement process includes first removing the remaining portions of the dummy gate stack 42 and dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, such that recesses are defined between gate spacers 44 and the upper portion of the semiconductor strip 28 is exposed. The remaining portions of the dummy nanostructure 24A are then removed by etching, such that recesses extend between the semiconductor nanostructures 26. During the etching process, the dummy nanostructure 24A is etched at a faster rate than the semiconductor nanostructures 26, the dielectric isolation layer 56, and the internal spacers 54. The etching may be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or similar.

[0054] Next, gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructure 26. Gate dielectric 78 is conformally formed on the exposed surface of the recesses (after removing the gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, gate dielectric 78 covers all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, gate dielectric 78 may be formed on the top surface of the semiconductor fin 20'; the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 26; and the sidewalls of the gate spacers 44. Gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers, or the like. The gate dielectric 78 may comprise a high-k material having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, and lead, or combinations thereof. Methods for forming the gate dielectric 78 may include molecular-beam deposition (MBD), ALD, PECVD, and the like, followed by a planarization process (e.g., CMP) to remove a portion of the gate dielectric 78 above the second ILD 72. Although a single-layer gate dielectric 78 is illustrated, the gate dielectric 78 may comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0055] A lower gate electrode 80L is formed on the gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L covers the lower semiconductor nanostructure 26L. The lower gate electrode 80L may be formed of a metallic material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, or the like. Although a single-layer gate electrode is illustrated, the lower gate electrode 80L may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0056] The lower gate electrode 80L is formed of a material suitable for the device type of a lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function tuning layers formed of a material suitable for the device type of a lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like. In some embodiments, the lower gate electrode 80L includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, or the like. Additionally or alternatively, the lower gate electrode 80L may include a dipole-inducing element suitable for the device type of a lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0057] The lower gate electrode 80L can be formed by conformally depositing one or more gate electrode layers to recess the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0058] In some embodiments, an isolation layer (not explicitly illustrated) may be formed on the lower gate electrode 80L as needed. The isolation layer serves as an isolation feature between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like), and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0059] Next, an upper gate electrode 80U is formed on the aforementioned isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U may be disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U covers the upper semiconductor nanostructure 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes as those used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function tuning layers (e.g., n-type work function tuning layers and / or p-type work function tuning layers), the work function tuning layers being formed from a material suitable for the device type of the upper nanostructure FET. Although the illustration shows a single-layer upper gate electrode 80U, the upper gate electrode 80U may include any number of power function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0060] Additionally, a removal process is performed to align with the top surfaces of the upper gate electrode 80U and the second ILD 72. The removal process for forming the gate dielectric 78 may be the same as the removal process for forming the upper gate electrode 80U. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, or the like may be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each pair of gate dielectrics 78 and gate electrodes 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) may be collectively referred to as a "gate structure" 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along at least three sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1). The lower gate structure 90L may also extend along the sidewalls and / or top surface of the semiconductor fin 20'.

[0061] As illustrated in Figure 8, a gate shield 92 is formed over the gate stack 90. ​​The forming process may include: recessing the gate stack 90, filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and performing a planarization process to remove excess portions of the dielectric material over the second ILD 72.

[0062] In Figure 9, the metal-semiconductor alloy region 94 and the source / drain contact 96 are formed through the second ILD 72 to be electrically coupled to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. As an example of forming the source / drain contact 96, the opening is formed through the second ILD 72 and the second CESL 70 using acceptable optical lithography and etching techniques. A liner (not shown separately) such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, or the like. A removal process may be performed to remove excess material from the gate spacer 44 and the top surface of the second ILD 72. The remaining liner and conductive material form the source / drain contact 96 in the opening. In some embodiments, a planarization process, such as CMP, etch-back process, a combination thereof, or the like, is utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within the process variation).

[0063] As needed, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 may be a silicate region formed of metal silicates (e.g., titanium silicate, cobalt silicate, nickel silicate, etc.), a germanide region formed of metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silica-germanide region formed of both metal silicates and metal germanides, or similar. The metal-semiconductor alloy region 94 may be formed before the material of the source / drain contact 96 by depositing metal in the opening of the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by deposition processes such as ALD, CVD, PVD, or similar methods. After a thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the openings of the source / drain contacts 96, such as from the surface of the metal-semiconductor alloy region 94. The material of the source / drain contacts 96 can then be formed on the metal-semiconductor alloy region 94.

[0064] Next, ESL 104 and third ILD 106 are formed. In some embodiments, ESL 104 may include a dielectric material with high etch selectivity for etching the third ILD 106, such as aluminum oxide, aluminum nitride, silicon carbide, or the like. The third ILD 106 may be formed using flow CVD, ALD, or the like, and the material may include PSG, BSG, BPSG, USG, or the like. The third ILD 106 may be deposited by any suitable method, such as CVD, PECVD, or the like.

[0065] Subsequently, gate contact 108 and source / drain via 110 are formed to contact the upper gate electrode 80U and source / drain contact 96, respectively. As an example of forming gate contact 108 and source / drain via 110, openings for gate contact 108 and source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable optical lithography and etching techniques. A liner (not shown separately) such as a diffusion barrier layer, adhesive layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the top surface of the third ILD 106. The remaining lining and conductive material form the gate contact 108 and the source / drain via 110 in the opening. The gate contact 108 and the source / drain via 110 can be formed in distinctly different processes or in the same process. Although illustrated with the same cross-section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed with a different cross-section to avoid short circuits at the contacts.

[0066] The front interconnect structure 114 is formed on the device layer 112. The front interconnect structure 114 includes a dielectric layer 116 and a layer of conductive features 118 in the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may further include passivation layers formed of a non-low-k and dense dielectric material, such as undoped silica glass (USG), silicon oxide, silicon nitride, or the like over a low-k dielectric material. The dielectric layer 116 may also include a polymer layer.

[0067] Conductive feature 118 may include conductive wiring and vias formed using an inlay process. Conductive feature 118 may include metal wiring and metal vias, which include a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. Aluminum pads may also be present, which are attached above the metal wiring and vias and electrically connected to the metal wiring and vias. In some embodiments, contacts to the lower gate structure 90L and the lower source / drain region 62L may be formed through the back side of device layer 112 (e.g., the side opposite to the front interconnect structure 114).

[0068] Independent heating of the unwanted byproduct 531 can be achieved by utilizing the secondary heating component 527. Furthermore, this heating is separate from and independent of the heating controlled by the first heating component 530. Therefore, in this case of independent heating, the byproduct 531 can be removed and decomposed without affecting the remainder of the etching process.

[0069] Furthermore, although the above description indicates that the use of the secondary heating component 527 occurs after the start of the etching process 501, this is not intended to limit the embodiment. Rather, the secondary heating component 527 can be started at any desired point in the process, such as simultaneously with the start of the etching process 501.

[0070] Figure 10 illustrates another embodiment of the secondary heating component 527. In this embodiment, instead of the secondary heating component 527, a laser that outputs a laser beam (as described above with respect to Figure 5B) is used. The secondary heating component 527 can be an ultraviolet light emitter, an infrared light emitter, a light-emitting diode (LED), or a vacuum extreme ultraviolet emitter that outputs a beam 1001. However, light of any suitable wavelength can be used.

[0071] Additionally, in some embodiments, the secondary heating element 527 is tunable with respect to the wavelength of the output light and also tunable with respect to scanning. For example, in some embodiments, the wavelength of the generated light can be tuned at least in part based on the byproduct 531 that needs to be decomposed. Furthermore, if the output beam 1001 is not large enough to illuminate all desired areas, a scanning process can be utilized, wherein one or more of the semiconductor substrate 20 or the secondary heating element 527 are rotated with respect to each other. Any suitable tuning can be used.

[0072] Figure 11 illustrates another embodiment of the secondary heating component 527. In this embodiment, instead of a laser (as described above with respect to Figure 5B) or a light-emitting diode (LED) (as discussed above with respect to Figure 10) that outputs a laser beam, the secondary heating component 527 may be an electron beam generator. In this embodiment, the secondary heating component 527 outputs an electron beam 1101, which functions to independently heat the byproduct 531 separately from the remainder of the semiconductor substrate 20.

[0073] Furthermore, in this embodiment, the secondary heating component 527 is tunable with respect to both the wavelength and incident angle of the positively output electron beam 1101, and is also tunable with respect to scanning. For example, in some embodiments, the wavelength of the positively generated electron beam 1101 can be tuned at least in part based on the desired byproduct 531. Additionally, if the output electron beam 1101 is not large enough to irradiate all desired areas, a scanning process can be utilized, wherein one or more of the semiconductor substrate 20 or the secondary heating component 527 are rotated with respect to each other.

[0074] Figure 12 illustrates another embodiment of the secondary heating component 527. In this embodiment, instead of the secondary heating component 527, a laser that outputs a laser beam (as described above with respect to Figure 5B), a light-emitting diode (LED) (as discussed above with respect to Figure 10), or an electron beam generator (as described above with respect to Figure 11), the secondary heating component 527 may be a thermal neutron injection device. In this embodiment, the secondary heating component 527 inputs gas or free radicals from, for example, a neutron heating box 1201 to the etching chamber 504. In this embodiment, the neutron heating box 1201 receives the gas and / or free radicals and heats the gas and / or free radicals using heating methods such as laser, microwave (MW), light-emitting diode, plasma process, combinations of these, or the like. However, any suitable heating method may be used.

[0075] Once the gas and / or free radicals have been heated within the neutron heating chamber 1201, the gas and / or free radicals are injected into the etching chamber 504 via one or more secondary nozzles 1203. In embodiments, the one or more secondary nozzles 1203 may resemble nozzle 532 (described above with respect to Figure 5B). However, any suitable method or apparatus may be used to inject heater neutrons into the etching chamber 504.

[0076] Additionally, in this embodiment, the secondary heating component 527 may be tunable with respect to the introduction of thermal neutrons. For example, if the introduction of thermal neutrons is not large enough to introduce thermal neutrons to all desired areas, a scanning process may be used in which one or more of the semiconductor substrate 20 or the secondary heating component 527 are rotated with respect to each other.

[0077] Figure 13 illustrates another embodiment of the secondary heating component 527. In this embodiment, instead of a laser that outputs a laser beam (as described above with respect to Figure 5B), a light-emitting diode (LED) (as discussed above with respect to Figure 10), an electron beam generator (as described above with respect to Figure 11), or a thermal neutron injector (as described above with respect to Figure 12), the secondary heating component 527 may be an electron bombardment device. In this embodiment, the secondary heating component 527 inputs electrons 1301 from, for example, an electron injector into the etching chamber 504. Once electrons 1301 have been injected into the etching chamber 504, electrodes 1303 may be used to provide a DC bias to accelerate the electrons 1301 toward the semiconductor substrate 20.

[0078] Of course, while a specific number of embodiments have been presented above, the concept is not intended to be limited to the precise embodiments described. Rather, any other suitable method may be used to independently heat the byproduct 531 to decompose it. All such methods are fully intended to be included within the scope of the embodiments.

[0079] Figure 14 illustrates that, although specific structures have been presented above, the presented concepts are not intended to limit one to the precise embodiments described. Rather, the concepts can be applied to any suitable material (e.g., first material 1401) recessed within any other suitable material (e.g., second material 1403). In such embodiments, the first material 1401 may be a material such as silicon oxide, silicon carbide, silicon oxynitride, combinations thereof, or the like, while the second material 1403 may be a material such as silicon, silicon nitride, silicon carbonitride, SiOCN, alumina, titanium nitride, tungsten, combinations thereof, or the like. However, any suitable material may be used.

[0080] Once the first material 1401 has been deposited within the second material 1403, the first material 1401 is recessed. The first material 1401 can be recessed using the processes described above with respect to Figures 1 through 14, including the use of a separate heat source to heat and decompose unwanted byproducts 531 during the etching process 501. Thus, byproducts 531 can be removed without interfering with the remainder of the etching process 501.

[0081] By utilizing the embodiments described herein, a separate heating source is employed to remove byproduct 531 and salt generated during the chemical etching process. This function enables temperature control of the semiconductor substrate 20 and byproduct 531 to separate them from each other. This separation helps improve depth variation and avoids a decrease in etching rate by using a generally high temperature.

[0082] According to one embodiment, a method of manufacturing a semiconductor device includes: depositing a dielectric material into a trench over a semiconductor substrate; and recessing the dielectric material by an etching process, wherein the etching process includes the steps of: heating the semiconductor substrate; and separately heating a byproduct of the etching process. In one embodiment, the byproduct is ammonium hexafluorosilicate. In one embodiment, the separate heating is performed at least partially by a laser. In one embodiment, the separate heating is performed at least partially by a photodiode. In one embodiment, the separate heating is performed at least partially by electron injection. In one embodiment, the separate heating is performed at least partially by thermal neutrons. In one embodiment, the separate heating is performed at least partially by an electron beam.

[0083] According to another embodiment, a method of manufacturing a semiconductor device includes: placing a semiconductor wafer in an etching chamber, the etching chamber including a first heating element, the semiconductor wafer holding a dielectric material located in a first recess; reacting the dielectric material to form a gas and causing the dielectric material to be recessed, the reaction of the dielectric material further generating a byproduct; and heating the byproduct by a second heating element different from the first heating element. In one embodiment, the second heating element is an electron injector. In one embodiment, the second heating element is an electron beam generator. In one embodiment, the second heating element is a neutron heating box. In one embodiment, the second heating element is a light-emitting diode. In one embodiment, the second heating element is a laser. In one embodiment, the byproduct is ammonium hexafluorosilicate.

[0084] According to yet another embodiment, an apparatus for manufacturing a semiconductor device includes: an etching chamber; a mounting platform; a first heating element; and a second heating element independent of the first heating element. In one embodiment, the first heating element is a resistive heating element. In one embodiment, the second heating element is a laser. In one embodiment, the second heating element is an electron beam. In one embodiment, the second heating element is a light-emitting diode. In one embodiment, the second heating element is an infrared generator.

[0085] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The present disclosure is best understood by reading in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates a perspective view of an example complementary field-effect transistor (CFET) according to some embodiments. Figures 2 through 14 are views of intermediate stages in the fabrication of a CFET according to some embodiments. [Biomaterial Storage]

[0087] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of manufacturing a semiconductor device, the method comprising the steps of: depositing a dielectric material into a trench above a semiconductor substrate; and recessing the dielectric material by an etching process, wherein the etching process comprises the steps of: heating the semiconductor substrate by a first heating element to cause the dielectric material to react to form a gas and produce a secondary product; and separately heating the secondary product of the etching process by a second heating element different from the first heating element.

2. The method as described in claim 1, wherein the byproduct is ammonium hexafluorosilate.

3. The method as described in claim 1, wherein the step of separate heating is performed at least in part by a laser.

4. The method as described in claim 1, wherein the step of separate heating is performed at least in part by a photodiode.

5. A method of manufacturing a semiconductor device, the method comprising the steps of: placing a semiconductor wafer in an etching chamber, the etching chamber including a first heating element, the semiconductor wafer including a dielectric material located in a first recess; reacting the dielectric material to form a gas and recessing the dielectric material, the step of reacting the dielectric material further generating a byproduct; and heating the byproduct by a second heating element different from the first heating element.

6. The method as described in claim 5, wherein the second heating component is an electron injector.

7. The method as described in claim 5, wherein the second heating component is an electron beam generator.

8. The method as described in claim 5, wherein the second heating component is a neutron heating box.

9. An apparatus for manufacturing a semiconductor device, the apparatus comprising: an etching chamber; a mounting platform located in the etching chamber; a first heating assembly located in the etching chamber, wherein the first heating assembly is configured to heat a dielectric material located in a recess in a semiconductor wafer above the first heating assembly to produce a byproduct; and a second heating assembly independent of the first heating assembly located in the etching chamber, wherein the second heating assembly is configured to heat the byproduct.

10. The device as claimed in claim 9, wherein the first heating element is a resistance heating element.

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