Semiconductor structure forming method and semiconductor structure

Abstract

A method of forming a semiconductor structure includes etching at least one conductive structure to form openings that divide the conductive structure into shorter portions, and applying at least one passivation treatment to a portion above the openings. The method may also include forming a non-conformal material layer having a lower fixed charge concentration than silicon nitride. In some embodiments, the non-conformal material layer has a first portion passivated by at least one passivation treatment on the portion above the openings, and a second portion extending to a base of the openings, the first portion of the non-conformal material layer having a thickness smaller than the second portion. In some embodiments, the method further includes depositing a fill dielectric on the non-conformal material layer.

Description

Technical Field

[0001] none Prior Technology

[0002] Advances in integrated circuit (IC) materials and design technologies have resulted in generations of ICs, each generation being smaller and more complex than the previous ones. Throughout IC development, functional density (e.g., the number of interconnects per unit chip area) has increased overall, while geometric dimensions have decreased. This scaling down typically benefits production efficiency and reduces associated costs.

[0003] This reduction in scale also increases the complexity of integrated circuit fabrication and manufacturing, and similar advancements in integrated circuit fabrication and manufacturing are needed to achieve these advancements. For example, dielectrics (e.g., dielectric materials) can be used as spacers, pads, and gap fillers to achieve component isolation. However, in some cases, dielectric materials can have high levels of positive fixed charge due to point defects. In some cases, high levels of positive fixed charge within semiconductor devices can lead to various device performance problems. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The best understanding of this disclosure will be achieved by reading the following embodiments in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11, 18A, 18B, 19A, 19B, 20, 37A, 37B, 38A, and 38B are views illustrating intermediate stages of transistor formation according to some embodiments. Figures 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 17C, 17D, 17E, 17F, 17G, 17H, 17I, 17J, 17K, 17L, 17M, 17N, 17O, and 17P illustrate the formation of continuous polysilicon on diffusion edge (CPODE) according to a partial embodiment. Figures 21 to 36 illustrate the formation of the cut metal gate (CMG) isolation interface according to some embodiments. Figure 39 illustrates the process flow for forming a transistor according to a partial embodiment. Implementation

[0006] The following disclosure provides many different implementations or embodiments to carry out the various features of this disclosure. The specific embodiments of composition and arrangement described below are used to simplify this disclosure. Of course, these are merely embodiments and are not intended to limit this disclosure. For example, in the description below, the formation of a first feature on or above a second feature may include implementations where the formed first and second features are in direct contact, and may also include implementations where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplification and clarity, and does not in itself specify the relationship between the various discussed implementations and / or configurations.

[0007] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used in this disclosure to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the element during use or operation. The device may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptive symbols used in this disclosure may be interpreted accordingly.

[0008] Dielectric materials are used for device isolation in semiconductor device fabrication, for example, as spacers, pads, and gap fillers. However, some dielectric materials have high levels of positive fixed charge caused by point defects, such as K+ centers that may be present in silicon nitride (SiN) deposited using plasma-assisted chemical vapor deposition (PEVD) or plasma-assisted atomic layer deposition (PEALD). High levels of positive fixed charge can lead to various device performance problems. In some cases, high levels of positive fixed charge in materials used as isolation structures can induce inversion layers in adjacent p-type or p-type doped wells, resulting in undesirable leakage currents.

[0009] By positioning a buffer layer with a low fixed charge level between a material with a high fixed charge level and a gap-filling dielectric material with a high fixed charge level (e.g., n-type and / or p-type doped wells), the influence of induced charge on the dielectric gap-filling isolation structure can be mitigated.

[0010] In some embodiments, increasing the thickness of a buffer layer with a low fixed charge level dielectric composition within the isolation structure is advantageous to mitigate leakage between transistors. However, increasing the thickness of the buffer layer positioned within the trench or opening using conformal deposition methods can simultaneously reduce the critical dimension (CD) of the gap opening. Reducing the gap opening of the isolation structure can lead to difficulties in depositing the dielectric gap filler used to fill the isolation opening or trench structure.

[0011] The methods and structures described herein can use a bottom-up filling process to create a thick buffer layer at the base of an opening or trench structure. The thickness of the buffer layer at the base of the trench isolation structure can mitigate the induced charge effect of the fixed charge of the isolation material within the trench structure in p-type and n-type wells without narrowing the opening (e.g., critical dimension) of the trench isolation structure.

[0012] In the illustrated embodiments, the formation of a gate-all-around (GAA) transistor is used as an example to explain the concepts of this disclosure. Other types of transistors, such as FinFETs, planar transistors, etc., may also employ the concepts of this disclosure. The embodiments discussed herein are intended to provide examples that enable the manufacture or use of the subject matter of this disclosure, and those skilled in the art will readily understand that modifications can be made while remaining within the intended scope of the different embodiments. In the various views and illustrated embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0013] Figures 1 through 38B illustrate views of intermediate stages of transistor formation according to some embodiments of this disclosure.

[0014] Please refer to Figure 1, which shows a perspective view of wafer 10. Wafer 10 comprises a multilayer structure, which includes a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc., or other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained semiconductor-on-insulator, silicon-germanium-on-insulator, etc. Substrate 20 may be doped to be a p-type semiconductor; however, in other embodiments, it may be doped to be an n-type semiconductor.

[0015] According to some embodiments, the multilayer stack 22 is formed through a series of deposition processes involving alternating materials. The corresponding process is illustrated as process 202 in the process flow 200 shown in Figure 39. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0016] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or contains silicon germanium (SiGe), germanium (Ge), silicon (Si), gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), etc. According to some embodiments, the deposition of the first layer 22A (e.g., silicon germanium) is performed by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a first thickness between about 30 Å and about 300 Å. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0017] Once the first layer 22A is deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or contains a second semiconductor material, such as silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), and combinations thereof, wherein the second semiconductor material differs from the first semiconductor material of the first layer 22A. For example, according to a partial embodiment where the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0018] According to some embodiments, a second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the thickness of the first layer 22A is approximately between 4 nm and 7 nm, while the thickness of the second layer 22B ranges from approximately 8 nm to 12 nm.

[0019] Once the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same thickness as or a different thickness than the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as sacrificial layer 22A throughout the description. According to an alternative embodiment, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0020] According to some embodiments, several pad oxide layers (singular / plural) and hard photomask layers (singular / plural) (not shown) may be formed over the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0021] Referring to Figure 2, a portion of the multilayer stack 22 and the underlying substrate 20 is patterned using an etching process to form a trench 23. The trench 23 extends into the substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as the multilayer stack 22'. Below the multilayer stack 22', a portion of the substrate 20 remains, hereinafter referred to as substrate strip 20'. The multilayer stack 22' includes semiconductor layers 22A and 22B. Semiconductor layer 22A is alternatively referred to as a sacrificial layer, and semiconductor layer 22B is alternatively referred to as a nanostructure. The portion of the multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0022] In the embodiments illustrated above, the transistor structure can be patterned using any suitable method. For example, one or more lithography processes (including dual or multiple patterning processes) can be used to pattern the structure. Generally, dual or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns, for example, with a pitch smaller than that obtained using a single, direct lithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the element structure.

[0023] Figure 3 illustrates the formation of isolation region 26, which is also referred to as shallow trench isolation (STI) region throughout the description. The corresponding process is illustrated as process 206 in process flow 200 of Figure 39. Shallow trench isolation region 26 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation through the surface layer of substrate 20. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition, etc. Shallow trench isolation region 26 may also include a dielectric material above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, high-density plasma chemical vapor deposition, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, can then be performed to flatten the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes shallow trench isolation region 26.

[0024] The shallow trench isolation region 26 is then recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the shallow trench isolation region 26 to form a protruding fin 28. The protruding fin 28 comprises the top of a multilayer stack 22' and a substrate strip 20'. The recess of the shallow trench isolation region 26 can be performed via a dry etching process, wherein, for example, nitrogen trifluoride (NF3) and nitrogen (NH3) are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the shallow trench isolation region 26 is performed via a wet etching process. For example, the etching chemicals may include hydrogen fluoride (HF).

[0025] Referring to Figure 4, a virtual gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is illustrated as process 208 in the process flow 200 shown in Figure 39. The virtual gate stack 30 may include a virtual gate dielectric 32 and a virtual gate electrode 34 located above the virtual gate dielectric 32. The virtual gate dielectric 32 may be formed by oxidizing a portion of the surface of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. The virtual gate electrode 34 may be formed using, for example, polycrystalline silicon or amorphous silicon, or other materials such as amorphous carbon.

[0026] Each virtual gate stack 30 may also include one (or more) hard photomasks 36 located above the virtual gate electrode 34. The hard photomask 36 may be formed from silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The virtual gate stack 30 may span one or more protruding fins 28 and shallow trench isolation regions 26 between the protruding fins 28. The virtual gate stack 30 also has a length direction perpendicular to the length direction of the protruding fins 28. The formation of the virtual gate stack 30 includes forming a virtual gate dielectric layer, depositing a virtual gate electrode layer above the virtual gate dielectric layer, depositing one or more hard photomask layers, and then patterning the formed layers through a patterning process.

[0027] Next, gate spacers 38 are formed on the sidewalls of the virtual gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), etc., and may have a single-layer structure or a multilayer structure containing multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layers constitutes the gate spacers 38.

[0028] Figures 5A and 5B illustrate cross-sectional views of the structure shown in Figure 4. Figure 5A shows a reference cross-section A1-A1 from Figure 4, which cuts through the portion of the protruding fin 28 not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the length direction of the gate. The gate spacer 38 is also shown on the sidewall of the protruding fin 28. Figure 5B shows a reference cross-section BB from Figure 4, which is parallel to the length direction of the protruding fin 28.

[0029] Referring to Figures 6A and 6B, a recess 42 is formed by etching a portion of the protruding fin that is not directly below the virtual gate stack 30 and the gate spacer 38. The corresponding process is illustrated as process 210 in process flow 200 shown in Figure 39. For example, a dry etching process can be performed using a mixture of hexafluoroethane (C2F6), carbon tetrafluoride (CF4), silicon dioxide (SO2), hydrogen bromide (HBr), chlorine (Cl2), and oxygen (O2), or a mixture of hydrogen bromide (HBr), chlorine (Cl2), oxygen (O2), and difluoromethane (CH2F2) to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The base of the recess 42 is at least flush with the base of the multilayer semiconductor stack 22', or may be lower than the base of the multilayer semiconductor stack 22' (as shown in Figure 6B). The etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in Figure 6B.

[0030] Referring to Figures 7A and 7B, the sacrificial semiconductor layer 22A is laterally recessed to form lateral grooves 41, which recess from the edges of the nanostructures 22B above and below them, respectively. The corresponding process is illustrated as process 212 in the process flow 200 shown in Figure 39. The lateral recesses of the sacrificial semiconductor layer 22A can be achieved through a wet etching process using an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon (Si)) than the material of the nanostructures 22B and the substrate 20 (e.g., silicon germanium (SiGe)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, a wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using immersion processes, spraying processes, spin coating processes, etc.

[0031] According to an alternative implementation, the lateral recess of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0032] Please refer to Figures 8A and 8B to illustrate the formation of the inner spacer 44. The corresponding process is illustrated as process 214 in process flow 200 shown in Figure 39. According to a partial embodiment, the formation of the inner spacer 44 includes depositing a conformal dielectric layer that extends into the lateral groove 41 (Figure 7B). Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral groove 41, leaving the portion of the spacer layer inside the lateral groove 41. The remaining portion of the spacer layer is referred to as the inner spacer 44.

[0033] Figures 9A and 9B illustrate cross-sectional views of the source / drain region 48 formed in the groove 42 through epitaxy. The corresponding process is illustrated as process 216 in process flow 200 shown in Figure 39. The source / drain region (singular / plural) may refer to either the source or the drain, individually or collectively depending on the context. According to some embodiments, the source / drain region 48 may apply stress to the nanostructure 22B, which serves as a channel for a corresponding all-around gate transistor, thereby improving performance.

[0034] According to some embodiments, the corresponding transistor is n-type, and the epitaxial source / drain region 48 is thus formed as n-type by doping with an n-type dopant. For example, silicon phosphide (SiP), silicon carbide phosphide (SiCP), etc., can be grown to form the epitaxial source / drain region 48. According to an alternative embodiment, the corresponding transistor is p-type, and the epitaxial source / drain region 48 is thus formed as p-type by doping with a p-type dopant. For example, silicon boron (SiB), silicon germanium boron (SiGeB), etc., can be grown to form the epitaxial source / drain region 48. After the groove 42 is filled with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally and can form facets. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other, forming gaps.

[0035] After the epitaxial process, n-type or p-type impurities can be further implanted into the epitaxial region 48 to form a source region and a drain region, which are also denoted by reference numeral 48. According to an alternative embodiment disclosed herein, when the epitaxial region 48 is doped with n-type or p-type impurities in situ during epitaxy, the implantation process can be omitted, and the epitaxial region 48 is also a source / drain region.

[0036] Figures 10A and 10B illustrate cross-sectional views of the structure after the formation of the contact etch stop layer (CESL) 50 and the interlayer dielectric (ILD) 52. The corresponding process is illustrated as process 218 in process flow 200 shown in Figure 39. The contact etch stop layer 50 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using chemical vapor deposition, atomic layer deposition, etc. The interlayer dielectric 52 can comprise a dielectric material formed using, for example, flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric 52 can be formed from an oxygen-containing dielectric material, which can be a silica-based material formed using tetraethyl silicate (TEOS) as a precursor, phosphosilate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilate glass (BPSG), undoped silicate glass (USG), etc.

[0037] The contact etch stop layer 50 and interlayer dielectric 52 are planarized via a planarization process (e.g., chemical mechanical polishing or mechanical polishing). According to one embodiment, the planarization process may remove the hard photomask 36 to expose the dummy gate electrode 34, as shown in Figure 10A. According to an alternative embodiment, the planarization process may expose the hard photomask 36 and stop on it. According to one embodiment, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard photomask 36), the gate spacer 38, and the interlayer dielectric 52 are planar within the process variation.

[0038] Figure 10C illustrates a top view of the structure shown in Figures 10A and 10B according to a partial embodiment. The multilayer stack 22', substrate strip 20', and protruding fins 28 (refer to Figure 10A) have a length direction in the X direction, and the corresponding cross-sectional view is referred to as the X-cut view. The gate stack 30, including the dummy gate electrode 34 (e.g., a polycrystalline silicon strip), has a length direction along the Y direction, and the corresponding cross-sectional view is referred to as the Y-cut view. The source / drain region 48 is formed based on certain portions of the multilayer stack 22' (as shown in Figures 5B and 10B). The edges of the source / drain region may contact or be separated from the gate spacer 38.

[0039] Figure 11 illustrates a top view of the formation of the fin isolation region 112. According to a partial embodiment, as shown in Figure 11, the fin isolation region 112 is a continuous polysilicon region on a diffusion edge, and its formation involves etching the dummy gate stack 30, the multilayer stack 22', and the substrate strip 20'. The corresponding process is illustrated as process 220 in the process flow 200 shown in Figure 39. Figures 12A through 17P illustrate the detailed process of forming the fin isolation region 112 by cutting the dummy gate stack 30.

[0040] Figures 12A through 17P illustrate the fin isolation region 112 formed according to a partial embodiment (using a continuous polysilicon process on the diffusion edge). In the following figures, figures with the letter A following the corresponding figure number are obtained from a Y cut (along the Y direction) in Figure 11, while figures with the letter B following the corresponding figure number are obtained from an X cut (along the X direction) in Figure 11.

[0041] Figures 12A and 12B illustrate the structure in Figure 10C, obtained from Y-cut and X-cut cross-sections, respectively. Figures 12A and 12B also correspond to Figures 10A and 10B, respectively. Therefore, Figure 12A illustrates the multilayer stack 22' and the virtual gate stack 30 on the multilayer stack 22'. Figure 12B illustrates the source / drain region 48, the multilayer stack 22', the inner spacer 44, and the virtual gate stack 30.

[0042] Referring to Figures 12A and 12B, a hard photomask 116 is formed. The hard photomask 116 may contain a dielectric material such as silicon nitride (SiN), silicon, or multiple layers thereof. A patterned etch photomask 117 (e.g., a three-layer photoresist) is formed over the hard photomask 116. Next, as shown in Figures 13A to 14B, the hard photomask 116 is etched to form an opening 118, through which the virtual gate electrodes of the virtual gate stack 30 are exposed. The lower virtual gate electrodes of the virtual gate stack 30 are then etched using the hard photomask 116 until the virtual gate dielectric 32 is exposed, as shown in Figures 15A and 15B. The etching is anisotropic, such that the edges of the virtual gate electrodes facing the opening 118 are vertical and straight. The virtual gate dielectric 32 can be used as an etch stop layer during the etching process.

[0043] Then, for example, the dummy gate dielectric 32 is removed by an isotropic etching process, thereby exposing the multilayer stack 22'. The final structure is shown in Figures 16A and 16B. Next, an etching process is performed to remove the exposed multilayer stack 22', and then the underlying semiconductor material (e.g., substrate strip 20') is further etched. Thus, openings 120 are formed between adjacent shallow trench isolation regions 26, as shown in Figures 17A and 17B. The openings 120 may extend below the bottom surface of the shallow trench isolation regions 26 to reduce leakage. In some embodiments, the openings 120 may extend into regions of the substrate 20 containing wells of n-type and / or p-type dopants.

[0044] Figures 17C to 17E illustrate an embodiment of a method for forming a buffer layer 300 within an opening 118 to mitigate induced charges in wells within the substrate 20 due to the fixed charge of the insulating material, without reducing the width W1 of the opening 118, for example, without reducing the critical size of the opening 118. The wells within the substrate 20 are n-type or p-type doped regions that may surround the base and sidewalls of the opening 118. To avoid narrowing of the width W1 of the opening 118, the method and structure described with reference to Figures 17C to 17E employ a bottom-up deposition method including a suppression treatment (passivation) in which the amount of material forming the buffer layer 300 at the base of the opening 118 is greater than the amount of material forming the buffer layer 300 at the top of the opening 118. This reduces the incidence of opening 118 pinching.

[0045] Figure 17C illustrates a suppression treatment 301, which may be a stage in a series of suppression and deposition steps that together provide a dense, thick buffer layer 300 at the base of the opening 118 (as shown in Figure 17D) while limiting the growth of the buffer layer 300 at the upper portion 302 of the opening 118. In some embodiments, the suppression treatment 301 may comprise at least one passivation or heat treatment applied to the upper portion 302 of the opening 118. In some embodiments, when the suppression treatment 301 is a heat treatment, the heat treatment may be performed at a temperature of approximately 600˚C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or combinations thereof, wherein the heat treatment comprises a pressure of 10 Torr to 5 atm (ATM). In some embodiments, when the suppression treatment 301 is a plasma treatment, the plasma treatment may comprise a plasma of argon, helium, hydrogen, or combinations thereof. In some embodiments, the temperature of the plasma treatment is 300˚C to 500˚C. In some embodiments, the plasma treatment includes pressures from 10 Torr to 5 Atmospheres (ATM). The plasma process used for suppression treatment 301 can be in-situ and / or ex-situ. In-situ processes can use the same tools for suppression treatment 301 as a subsequent deposition step using plasma-enhanced chemical vapor deposition (PECVD) and / or plasma-enhanced atomic layer deposition. Ex-situ processes use different tools for suppression treatment 301 as a subsequent deposition step using plasma-enhanced chemical vapor deposition and / or plasma-enhanced atomic layer deposition.

[0046] The process conditions for the inhibition treatment 301 are selected to ensure that only the upper portion 302 of the opening 118 is treated. For example, the inhibition treatment 301 may be applied only to the upper half of the depth of the opening 118. In some embodiments, the diffusion path of the deposited material can be limited by controlling the pressure of the inhibition treatment 301 within the range of 10 Torr to 5 Atmospheric Pressures (ATM). For example, the process conditions for the inhibition treatment 301 are selected to control the diffusion path of the gas or plasma material to treat only the upper portion 302 of the opening 118. For example, the diffusion path of the gas or plasma material used for the inhibition treatment can be controlled so that the inhibition treatment can be limited to the range of 5 nm to 5 µm. In some embodiments, the gas or plasma material reacts with the sidewalls of the opening 118 (e.g., the interlayer dielectric layer 52) and removes hydroxyl groups (OH), thereby inhibiting the deposition of dielectric material (e.g., the material of the buffer layer 300) onto the sidewalls of the opening 118. After suppression treatment 301, the exposed sidewalls through the opening 118 of the interlayer dielectric layer 52, after the removal of hydroxyl (-OH) groups, have a high concentration of silicon hydrogen (Si-H) bonds, silicon oxygen (Si-O) bonds, and disilicon (Si-Si) bonds.

[0047] Figure 17D illustrates an embodiment of the deposition step, which may be a stage of cyclic suppression and deposition steps that together provide a dense, thick buffer layer 300 at the base of the opening 118 while restricting the growth of the buffer layer 300 at the upper portion 302 of the opening 118. In some embodiments, forming the buffer layer 300 includes forming a non-conformal material layer, such as Si3N4, having a fixed charge concentration lower than that of silicon nitride. The non-conformal material layer has a first portion passivated by at least one passivation treatment located on the upper portion 302 of the opening 118, and a second portion extending to the lower portion 303 of the opening 118, which includes the base of the opening 118. In some embodiments, the thickness of the first portion of the non-conformal material layer providing the buffer layer 300 in the upper portion 302 of the opening 118 is less than the thickness of the second portion of the non-conformal material layer providing the buffer layer 300 in the lower portion 303 of the opening 118. Compared to the thickness of the buffer layer 300 in the upper portion 302 of the opening 118, the greater the thickness of the buffer layer 300 in the lower portion 303 of the opening 118, the more abundant the dielectric film with a lower fixed charge level is provided between the gap-filling dielectric with a high fixed charge level (as shown in Figure 17E) and the doped well regions (e.g., n-type and / or p-type doped wells) present in the substrate 20. The smaller thickness of the buffer layer 300 in the upper portion 302 of the opening 118 does not significantly reduce the width W1 of the opening 118, and therefore does not limit the dielectric filling deposition process of filling the opening 118 with an insulating material (as shown in Figure 17E). A low fixed charge level dielectric is a material used as an insulator with a very small amount of trapped charge (fixed charge) within its structure. By minimizing the fixed charge, a low fixed charge level dielectric can minimize unwanted electrical effects such as leakage current. Examples of dielectric materials with low fixed charge levels in the buffer layer 300 may include silicon oxide (SiO2), silicon carbon oxide (SiCO), silicon carbonitride (SiCN), and / or silicon carbon oxynitride (SiCON). An example of a filler dielectric material with a high fixed charge level is silicon nitride (SiN).

[0048] The buffer layer 300 can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), or a combination thereof. The inhibition treatment 301 reduces the concentration of hydroxyl (-OH) groups in the upper portion 302 of the opening 118, thereby reducing the reactivity of the sidewalls of the opening 118 to the deposition of the buffer layer 300 in the upper portion of the opening 118. This reduced reactivity results in a thinner buffer layer 300 deposited in the upper portion 302 of the opening 118 than the thinner buffer layer 300 deposited in the lower portion 303 of the opening 118. The lower portion 303 of the opening 118 has higher reactivity with the deposited material, and because the diffusion path of the inhibition treatment 301 is shorter, it avoids reaching the lower portion 303 of the opening 118. In some embodiments, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal material layer of the buffer layer 300 in the lower portion 303 of the opening 118 ranges from 2 nm to 10 nm. In one embodiment, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal material layer of the buffer layer 300 in the lower portion 303 of the opening 118 can be from 2 nm to 5 nm. In some embodiments, the difference in thickness of the buffer layer 300 from the upper portion 302 of the opening 118 to the lower portion 303 of the opening 118 can be gradual.

[0049] It is worth noting that the suppression step shown in Figure 17C and the deposition step shown in Figure 17D are repeatable cyclic stages to provide bottom-up filling of the opening 118 using a non-conformal material layer with a fixed charge concentration lower than silicon nitride. For example, the cycle of the suppression step depicted in Figure 17C and the deposition step depicted in Figure 17D can be repeated 2 to 100 times. However, the number of times the suppression and deposition steps are repeated can be arbitrary to provide an appropriate amount of material for the buffer layer 300 at the base of the opening 118.

[0050] Figure 17E illustrates an embodiment in which a fill dielectric 305 is deposited on a non-conformal material layer providing a buffer layer 300. The fill dielectric 305 may be composed of an etch-resistant material. For example, the fill dielectric 305 may be composed of silicon nitride (e.g., Si3N4). The fill dielectric 305 composed of silicon nitride may be a high fixed charge level isolator (dielectric material). The fill dielectric 305 may be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), and combinations thereof. Notably, in some embodiments, the fill dielectric 305 is located directly on top of the buffer layer 300 and completely fills the opening 118.

[0051] Figures 17A through 17E illustrate an embodiment in which openings 118 and 120 are filled to form a continuous polycrystalline silicon isolation region 112 on the diffusion edge. A planarization process, such as a chemical mechanical polishing (CMP) process, can then be performed to form the fin isolation region 112, which is a continuous polycrystalline silicon isolation region on the diffusion edge, as also shown in Figure 11.

[0052] Figure 17F illustrates another embodiment in which the suppression step shown in Figure 17C can be adjusted to adjust the thickness of the buffer layer 300 on the sidewalls and base of the opening 118. For example, the pressure and / or time period of the suppression step shown in Figure 17C can be increased to increase the removal of hydroxyl (-OH) from the upper portion 302 of the opening 118. By increasing the intensity of the suppression step, a smaller amount of buffer layer 300 can be deposited in the upper portion 302 of the opening 118. In the embodiment shown in Figure 17F, the buffer layer 300 is not present in the upper portion 302 of the opening 118, but is present entirely in the lower portion 303 of the opening 118, including the base. In some embodiments, the top surface of the buffer layer 300 is lower than the top surface of the source / drain 48.

[0053] Figures 17G to 17I illustrate another embodiment of the method for forming a buffer layer 300 within the opening 118 to mitigate induced charges caused by the fixed charge of the insulating material in the well present in the substrate 20 without reducing the width W1 of the opening 118, for example, without reducing the critical dimension (CD) of the opening 118. To avoid narrowing of the width W1 of the opening 118, the method and structure described with reference to Figures 17G to 17I employ a bottom-up deposition method comprising a cyclic deposition step and a trench etching step, wherein the amount of material of the buffer layer 300 formed at the base of the opening 118 is greater than the amount of material of the buffer layer 300 formed at the top of the opening 118. The method shown in Figures 17G to 17I illustrates a cyclic deposition, which may be conformal or oriented, and removes the buffer layer in situ from the top and sidewalls of the opening 118. The method shown in Figures 17G to 17I also reduces the incidence of pinch-off of the opening 118.

[0054] Figure 17G illustrates an embodiment in which a buffer layer 300 of a low fixed charge dielectric is formed within the opening 118. For example, in some embodiments, the buffer layer 300 has a lower fixed charge concentration than silicon nitride. In some embodiments, the buffer layer 300 may be composed of silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbon oxynitride (SiCON), or combinations thereof.

[0055] The buffer layer 300 can be deposited onto the opening 118 using either a directional deposition process or a conformal deposition process. In some embodiments, the directional deposition process forms a buffer layer material of greater thickness at the base of the opening 118 and on the upper surface (which may be referred to as the horizontally oriented surface) of the interlayer dielectric (ILD) layer 52 adjacent to the opening 118. The thickness of the buffer layer 300 material deposited on the sidewalls of the opening 118 using the directional deposition process is less than the thickness of the buffer layer 300 located at the base of the opening 118. Compared to the directional deposition process, the conformal deposition process deposits a buffer layer 300 material of substantially the same thickness on both the sidewalls of the opening 118 and at the base of the opening 118.

[0056] The buffer layer 300 can be deposited onto the opening 118 using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), or a combination thereof. In some embodiments, to adjust the deposition process to provide directional deposition of the buffer layer 300, the deposition process pressure can be set to provide a low pressure of 1 Torr or lower.

[0057] Figure 17H ​​illustrates an embodiment of etching a buffer layer 300 to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer 300 includes a first portion in the upper portion 302 of the opening 118, the thickness of which is less than a second portion of the buffer layer 300 in the lower portion 303 of the opening 118, which includes the base of the opening 118. The etching process can be gas etching or plasma etching. The composition of the etchant used to etch the buffer layer 300 can be a fluorine-containing composition, such as hydrofluoric acid etchant (HF). Etching process conditions can be selected such that the amount of material removed by the etchant from the upper portion 302 of the opening 118 is greater than the amount of material removed from the lower portion 303 of the opening 118. For example, the non-conformal characteristics of the etch buffer layer 300 can be included in the thicker portion of the material of the buffer layer 300 at the base of the opening 118, and the maximum sidewall thickness of the etch buffer layer 300 towards the base of the opening 118. The sidewall thickness of the buffer layer 300 can decrease from the base of the opening 118 towards the upper surface of the opening 118. The thickness of the buffer layer 300 can be varied gradually.

[0058] For example, when the etching process is plasma etching, the etching conditions providing the non-conformal thickness of the buffer layer 300 may include a pressure range of 10 Torr to 30 Torr, a temperature range of 300 to 500 degrees Celsius, and a plasma with a large free radical to ion ratio. In some embodiments, in order to remove more material of the buffer layer 300 from the upper part 302 of the opening 118 without removing (or significantly removing) the material of the buffer layer 300 from the lower part 303 of the opening 118, the plasma may be adjusted to provide a free radical concentration greater than that of ions. The diffusion path of ions is greater than that of free radicals. By minimizing the ion concentration, the diffusion path of the etchant can be limited. In some embodiments, the free radical to ion ratio of the plasma etchant can range from 1000:1 to 100000:1.

[0059] In some embodiments, the etching process reduces the thickness of the buffer layer 300 in the upper portion 302 of the opening 118 to less than the thickness of the buffer layer 300 in the lower portion 303 of the opening 118. In some embodiments, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal layer of the buffer layer 300 in the lower portion 303 of the opening 118 ranges from 2 nm to 10 nm. In one embodiment, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal layer of the buffer layer 300 in the lower portion 303 of the opening 118 can be from 2 nm to 5 nm.

[0060] It is worth noting that the deposition step shown in Figure 17G and the etching step shown in Figure 17I are repeatable cyclic stages to provide a bottom-up filled non-conformal material layer with a fixed charge concentration lower than that of silicon nitride. For example, the deposition step illustrated in Figure 17G and the etching step illustrated in Figure 17H ​​can be repeated 2 to 100 times. However, the number of repetitions of the deposition and etching steps can be arbitrary to provide an appropriate amount of material for the buffer layer 300 at the base of the opening 118.

[0061] Figure 17I illustrates an embodiment in which a fill dielectric 305 is deposited on a non-conformal material layer providing a buffer layer 300. The fill dielectric 305 may be composed of an etch-resistant material. For example, the fill dielectric 305 may be composed of silicon nitride (e.g., Si3N4). The fill dielectric 305 composed of silicon nitride may be a high fixed charge level isolator (dielectric material). The fill dielectric 305 may be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), and combinations thereof. Notably, in some embodiments, the fill dielectric 305 is located directly on top of the buffer layer 300 and completely fills the opening 118.

[0062] Figures 17G through 17I illustrate an embodiment in which openings 118 and 120 are filled to form fin isolation region 112 (also referred to as continuous polycrystalline silicon region 112 on diffusion edge). A planarization process, such as a chemical mechanical polishing (CMP) process, can then be performed to form the fin isolation region, which is fin isolation region 112 (also referred to as continuous polycrystalline silicon region 112 on diffusion edge), also shown in Figure 11.

[0063] Figure 17J illustrates another embodiment of this disclosure, which uses a deposition step as described in Figure 17G above, combined with an etching step similar to the etching process described in Figure 17H, to form a buffer layer 300, wherein the etching process is adjusted to more aggressively remove material from the upper portion 302 of the opening 118. In Figure 17J, the buffer layer 300 has been removed from the entire upper portion 302 of the opening 118. For example, the etching time, etching temperature, or pressure of the etching process can be adjusted to increase the corrosiveness of the etchant in removing material.

[0064] Figures 17K to 17M illustrate a partial embodiment in which the buffer layer 300 is formed by a combination of a directional deposition process (refer to Figure 17G as described above) and an etching process (refer to Figure 17H ​​as described above). Compared to a conformal deposition process, the directional deposition process deposits a larger amount (e.g., a thicker thickness) of buffer layer 300 material at the base of the lower portion 303 of the opening 118.

[0065] Figure 17K illustrates an embodiment of the buffer layer 300, which is formed by a combination of the directional deposition process described in Figure 17G as above and the etching process described in Figure 17H ​​as above. The thickness of the buffer layer 300 formed in the lower portion 303 of the opening 118 by the directional deposition process shown in Figure 17K is greater than the thickness of the buffer layer 300 in the upper portion 302 of the opening 118. The buffer layer 300 has a flat upper surface at the base of the lower portion 303 of the opening 118. This flat upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300.

[0066] Figure 17L illustrates an embodiment of the buffer layer 300, which is formed by a combination of the directional deposition process described in Figure 17G and the etching process described in Figure 17H. The directional deposition process shown in Figure 17K for forming the buffer layer 300 results in a thicker buffer layer 300 in the lower portion 303 of the opening 118 compared to the thickness of the buffer layer 300 in the upper portion 302 of the opening 118. The buffer layer 300 has a raised upper surface at the base of the lower portion 303 of the opening 118. This raised upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300.

[0067] Figure 17M illustrates an embodiment of the buffer layer 300, which is formed by a combination of a directional deposition process described in Figure 17G and an etching process described in Figure 17H. The directional deposition process shown in Figure 17M for forming the buffer layer 300 results in a thicker buffer layer 300 in the lower portion 303 of the opening 118 compared to the thickness of the buffer layer 300 in the upper portion 302 of the opening 118. The buffer layer 300 has a recessed upper surface at the base of the lower portion 303 of the opening 118. This recessed upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300.

[0068] Figures 17N through 17P illustrate a partial embodiment in which the buffer layer 300 is formed by a combination of a directional deposition process (refer to Figure 17G as described above) and a more aggressive etching process (refer to Figure 17J as described above). Figure 17N illustrates a buffer layer 300 formed by a combination of a direct deposition step (refer to Figure 17K as described above) and an aggressive etching process (refer to Figure 17J as described above). The buffer layer shown in Figure 17N has a portion of the buffer layer 300 that has been removed from the entire upper portion 302 of the opening 118, and includes a thick portion of the buffer layer 300 in the lower portion 303 of the opening 118, which has a flat upper surface.

[0069] Figure 170 illustrates a buffer layer 300 formed by combining a direct deposition step (see Figure 17L) with an etch process (see Figure 17J). The buffer layer shown in Figure 170 has a buffer layer 300 that has been removed from the entire upper portion 302 of the opening 118, and includes a thick portion of the buffer layer 300 in the lower portion 303 of the opening 118, which has a raised upper surface.

[0070] Figure 17P illustrates a buffer layer 300 formed by combining a direct deposition step (refer to Figure 17M) with an etch process (refer to Figure 17J). The buffer layer shown in Figure 17P has a buffer layer 300 that has been removed from the entire upper portion 302 of the opening 118, and includes a thick portion of the buffer layer 300 in the lower portion 303 of the opening 118, which has a concave upper surface.

[0071] Referring to Figures 18A and 18B, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if remaining) are removed in one or more etching processes to form a recess 58. As shown in Figure 39, the corresponding process is illustrated as process 222 in process flow 200. According to some embodiments, the dummy gate electrode 34 and dummy gate dielectric 32 are removed via an anisotropic dry etching process. For example, the etching process can be performed using a reactive gas that selectively etches the dummy gate electrode 34 and dummy gate dielectric 32 at a rate faster than the interlayer dielectric (ILD) 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22' containing future channel regions in the subsequently completed transistor.

[0072] The sacrificial layer 22A is then removed to extend the grooves 58 between the nanostructures 22B. As shown in Figure 39, the corresponding process is illustrated as process 224 in process flow 200. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process using an etchant selective for the material of the sacrificial layer 22A), while the nanostructures 22B, substrate 20, and shallow trench isolation (STI) regions 26 remain relatively unetched compared to the sacrificial layer 22A. According to some embodiments, the sacrificial layer 22A comprises, for example, SiGe, and the nanostructures 22B comprise, for example, Si or SiC, and the sacrificial layer 22A can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0073] Referring to Figures 19A and 19B, gate dielectric 62 and gate electrode 68 are formed to form an alternative gate stack 70. As shown in Figure 39, the corresponding process is illustrated as process 226 in process flow 200. According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide, which may be deposited via conformal deposition processes (e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD)) or via an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the high-k dielectric layer may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0074] Gate electrode 68 is also formed. During formation, a conductive layer is first formed on the high-k dielectric layer, filling the remaining portion of the groove 58. Gate electrode 68 may comprise metallic materials such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, gate electrode 68 may comprise any number of layers, any number of work function layers, and possible filler materials. Gate dielectric 62 and gate electrode 68 also fill the space between adjacent nanostructures 22B and the space between the base of nanostructure 22B and the underlying substrate strip 20'. After filling the groove 58, a planarization process (e.g., CMP or mechanical polishing) is performed to remove excess material from the gate dielectric and gate electrode 68 located on the top surface of the interlayer dielectric (ILD) 52. Gate electrode 68 and gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0075] After the gate stack 70 is formed, a cut metal gate (CMG) region 110 can be formed, as shown in Figures 20 to 32. Figure 20 shows a top view of the formation of the cut metal gate (CMG) region 110, which separates / segments the replacement (metal) gate stack 70 into shorter portions. As shown in Figure 39, the corresponding process is shown as process 228 in process flow 200. The cut metal gate (CMG) isolation region 110 is also called the gate isolation region 110. As shown in Figure 23, according to a partial embodiment, the cut metal gate (CMG) isolation region 110 is formed by cutting the replacement gate stack 70.

[0076] The detailed process for forming the diced metal gate (CMG) isolation region 110 can be implemented from the processes shown in Figures 21 to 32. Figure 22 illustrates a cross-sectional view of an intermediate structure where the gate stack 70 has been formed and includes the gate dielectric 62 and the gate electrode 68, while the diced metal gate (CMG) isolation region 110 has not yet been formed. According to some embodiments, a hard photomask layer 88 is deposited, and the hard photomask layer 88 may comprise a multilayer structure with multiple layers. According to some embodiments, the hard photomask layer 88 comprises silicon nitride layers 88A, silicon layers 88B, and silicon nitride layers 88C. According to an alternative embodiment, a single-layer hard photomask 88 is used, which may be formed of or comprise silicon nitride.

[0077] As shown in Figure 23, an etched mask 90 is then formed. The etched mask 90 may also have a single-layer structure (which may contain photoresist) or a two-layer structure containing a base anti-reflective coating (BARC) and photoresist. Alternatively, the etched mask 90 may have three layers, which may include a bottom layer, an intermediate layer above the bottom layer, and a top layer, which may be a patterned photoresist. Trench 92 is formed in the etched mask 90.

[0078] Next, an etch mask 90 is used to etch the mask layer 88, extending the trench 92 into the hard mask layer 88. The etching can be anisotropic. According to some embodiments, the trench 92 extends to the top surface of the hard mask. After the trench 92 is formed in the hard mask layer 88, the etch mask 90 can be removed.

[0079] Next, as shown in Figure 23, the alternative gate stack 70 is etched. The etching of the alternative gate stack 70 is anisotropic. According to one embodiment, etching is performed until the shallow trench isolation (STI) region 26 is exposed. The trench 92 may or may not extend into the shallow trench isolation (STI) region 26. After the etching process, the hard photomask layer 88 may or may not be removed. Thus, the gate stack 70 is divided into gate stacks 70A and 70B.

[0080] Figures 24 through 32 illustrate an embodiment of the method for forming a buffer layer 300 within a trench 92 to form a cut-metal gate (CMG) isolation region 110. Similar to the buffer layer 300 used in the fin isolation region 112 (also referred to as the CPODE isolation region), the buffer layer 300 used in the cut-metal gate (CMG) isolation region 110 mitigates induced charges caused by the fixed charge of the isolation material in the traps present in the substrate 20 without reducing the opening width W2 of the trench 92; for example, it does not narrow the critical dimension (CD) of the opening of the trench 92. To avoid narrowing the opening width W2 of the trench 92, the method and structure described with reference to Figures 24 through 32 employ a bottom-up deposition method, where the amount of material forming the buffer layer 300 at the base of the trench 92 is greater than the amount of material forming the buffer layer 300 at the top of the trench 92. This reduces the incidence of pinch-off at the opening of the trench 92.

[0081] Figure 24 illustrates the formation of a buffer layer 300, which is formed by a series of cyclic suppression and deposition steps. These steps together provide a dense, thick buffer layer 300 at the base of the trench 92 while limiting the growth of the buffer layer 300 at the upper portion 302 of the trench 92. Figure 24 illustrates an embodiment in which a seam exists in the lower portion 303 of the trench 92. The buffer layer 300 shown in Figure 24 for cutting the metal gate (CMG) isolation region 110 is similar to the buffer layer 300 for the fin isolation region 112 (the continuous polycrystalline silicon (CPODE) region on the diffusion edge) described above with reference to Figures 17C and 17D. Therefore, the description of the buffer layer 300 described above with reference to Figures 17C and 17D applies to the description of the buffer layer 300 shown in Figure 24, where elements with the same reference numerals can share their detailed descriptions.

[0082] For example, the buffer layer 300 shown in Figure 24 may be formed after a suppression treatment is applied to the trench 92, the suppression treatment including applying one or more passivation treatments or heat treatments to the upper portion 302 of the trench 92. In some embodiments, when the suppression treatment 301 is a heat treatment, the heat treatment may be carried out at a temperature above 600˚C in an inert gas atmosphere including hydrogen, helium, nitrogen, or combinations thereof, wherein the heat treatment includes a pressure ranging from 10 Torr to 5 Atm (ATM). In some embodiments, when the suppression treatment 301 is a plasma treatment, the plasma treatment may include a plasma of argon, helium, hydrogen, or combinations thereof, wherein the plasma treatment temperature is from 300˚C to 500˚C, and wherein the plasma treatment includes a pressure ranging from 10 Torr to 5 Atm (ATM). Referring to Figure 17C, which is similar to the embodiments described above, the process conditions for forming the buffer layer 300 shown in Figure 24 may be selected such that only the upper portion 302 of the trench 92 is treated. After the suppression treatment, the sidewalls of the trench 92 exposed through the interlayer dielectric (ILD) 52 have a high concentration of silicon-hydrogen (Si-H), silicon-oxygen (Si-O), and silicon-silicon (Si-Si) bonds after the removal of hydroxyl groups (-OH). This will suppress the formation of dielectric material attempting to form directly on it. The suppression treatment is a passivation treatment applied to the upper part 302 of the trench 92.

[0083] After a suppression treatment (passivation treatment), a non-conformal material layer with a lower fixed charge concentration than silicon nitride is formed within the trench 92 as a buffer layer 300. For example, the non-conformal material layer may be composed of silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbon oxynitride (SiCON), or combinations thereof. The non-conformal material layer has a first portion located on the upper portion 302 of the trench 92, which is passivated by at least one passivation treatment (also called a suppression treatment), and a second portion located in the lower portion 303 of the trench 92, extending to the base of the trench. The thickness of the first portion of the non-conformal material layer of the buffer layer 300 located in the upper portion 302 of the trench 92 is less than the thickness of the second portion of the non-conformal material layer of the buffer layer 300 located in the lower portion 303 of the trench 92. For example, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 located in the upper part 302 of the trench 92 and the second portion of the non-conformal material layer of the buffer layer 300 located in the lower part 303 of the trench 92 is 2 nm to 10 nm.

[0084] Referring to Figure 17C, which is similar to the embodiment described above, the process conditions for forming the buffer layer 300 shown in Figure 24 can be selected such that only the upper portion 302 of the trench 92 is subjected to the suppression step. After the suppression step, the buffer layer 300 can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and / or plasma-assisted atomic layer deposition (PEALD).

[0085] It is worth noting that the suppression step and the deposition step shown in Figure 24 are repeatable cyclic stages to provide bottom-up filling of a non-conformal material layer with a fixed charge concentration lower than that of silicon nitride. For example, the cycle of the suppression and deposition steps shown in Figure 24 can be repeated 2 to 100 times. However, the number of repetitions of the suppression and deposition steps can be arbitrary to provide an appropriate amount of material for the buffer layer 300 at the base of trench 92.

[0086] Referring again to Figure 24, after forming the buffer layer 300, a filling dielectric 305 can be deposited on the buffer layer 300. The filling dielectric 305 shown in Figure 24 is similar to the filling dielectric 305 described above with reference to Figure 17I. Therefore, the description of the filling dielectric 305 shown in Figure 17I applies to the description of the filling dielectric 305 of the filling trench 92 shown in Figure 24. For example, the filling dielectric 305 may be composed of silicon nitride.

[0087] After depositing the fill dielectric 305, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process, is performed. The planarization process may stop on the top surface of the gate stack 70. As shown in Figure 24, the remaining portion of the buffer layer 300 and the fill dielectric 305 are collectively referred to below as the cut metal gate (CMG) isolation region 110. Due to the separation of the cut metal gate (CMG) isolation region 110 from the fin isolation region 112, there may be some regions that separate the cut metal gate (CMG) isolation region 110 from its adjacent fin isolation region 112 (also referred to as the CPODE isolation region). The length of the cut metal gate (CMG) isolation region 110 can be selected according to the circuit layout.

[0088] Figure 25 illustrates another embodiment of the cut metal gate (CMG) isolation region 110, wherein the formation of the buffer layer 300 comprises a series of cyclic suppression and deposition steps, which together provide a dense, thick buffer layer 300 at the base of the trench 92. In the embodiment shown in Figure 25, the suppression steps are more aggressive than those shown in Figure 24. Due to the greater passivation of the upper portion 302 of the trench 92, the buffer layer 300 will not be formed on the upper portion 302 of the trench 92 in the embodiment shown in Figure 25. The conditions for the suppression steps to form the buffer layer 300 in the embodiment shown in Figure 25 have been further described above with reference to Figure 17F.

[0089] The embodiments illustrated in Figures 24 and 25 depict a buffer layer geometry for the cut metal gate (CMG) isolation region 110 that can also be formed using a process sequence comprising depositing the buffer layer 300 using conformal or directional deposition processes (without a suppression step), followed by an etching step, wherein the etching step produces a non-conformal thickness of the buffer layer 300. More specifically, a method for forming a non-conformal thickness buffer layer 300 for the cut metal gate (CMG) isolation region 110 in the trench 92 using a cycle of deposition and etching steps can comprise forming a buffer layer 300 having a fixed charge concentration lower than that of silicon nitride, and etching the buffer layer 300 to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer 300 includes a first portion in a first portion 302 of the trench 92, the thickness of which is less than the thickness of a second portion of the buffer layer 300 in a second portion 303 of the trench 92.

[0090] The deposition steps for forming the geometry of the buffer layer 300 shown in Figures 24 and 25 have been described above with reference to Figure 17G. The etching steps for forming the buffer layer 300 shown in Figure 24 have been described above with reference to Figure 17H. As shown in Figure 25, the etching process of the etching step can be adjusted to remove the entire buffer layer 300 from the first portion 302 of the trench 92. In some embodiments, the etching steps for forming the buffer layer 300 shown in Figure 25 have been described above with reference to Figure 17J. After the cycle of deposition and etching steps for forming the buffer layer 300, the trench 92 can be filled with a filling dielectric 305 and planarized.

[0091] Figures 26 through 28 illustrate other embodiments of the cut metal gate (CMG) isolation region 110, including a buffer layer 300 with a non-conformal thickness, which provides a thick portion of dielectric material with a low fixed charge level at the base of the trench 92 without pinching the upper portion 302 of the trench 92. In the embodiments shown in Figures 26 through 28, directional deposition is combined with an extreme etching step to configure the geometry of the material of the buffer layer 300 at the base of the trench 92. For each embodiment shown in Figures 26 through 28, the etching process has been described with reference to Figure 17H.

[0092] For example, Figure 26 illustrates an embodiment of the buffer layer 300, which is thicker in the lower part 303 of the trench 92 than in the upper part 302. The buffer layer 300 has a flat upper surface at the base of the lower part 303 of the trench 92. As described above with reference to Figure 17K, the flat upper surface can be formed by adjusting the deposition conditions of the directional deposition process used to form the buffer layer 300. The filler dielectric 305 is formed directly on top of the buffer layer 300.

[0093] Figure 27 illustrates an embodiment of the buffer layer 300, which is formed using a cycle of directional deposition and etching processes, resulting in a greater thickness of the buffer layer 300 in the lower portion 303 of the trench 92. In the embodiment shown in Figure 27, the thickness of the buffer layer 300 formed in the lower portion 303 of the trench 92 by the directional deposition process for forming the buffer layer 300 is greater than the thickness of the buffer layer 300 in the upper portion 302 of the trench 92, wherein the buffer layer 300 has a raised upper surface at the base of the lower portion 303 of the trench 92. As described above with reference to Figure 17L, the raised upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300. The filler dielectric 305 is formed directly on top of the buffer layer 300.

[0094] Figure 28 illustrates an embodiment of a buffer layer 300 for a cut metal gate (CMG) isolation region 110, wherein the buffer layer 300 is formed using a cycle of directional deposition and etching processes, resulting in a greater buffer layer 300 thickness in the lower portion 303 of the trench 92. In the embodiment shown in Figure 28, the thickness of the buffer layer 300 formed in the lower portion 303 of the trench 92 by the directional deposition process for forming the buffer layer 300 is greater than the thickness of the buffer layer 300 in the upper portion 302 of the trench 92, wherein the buffer layer 300 has a recessed upper surface at the base of the lower portion 303 of the trench 92. As described above with reference to Figure 17M, the recessed upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300. A filler dielectric 305 is formed directly on top of the buffer layer 300.

[0095] Figures 29 through 31 illustrate other embodiments of the formed cut metal gate (CMG) isolation region 110, including a buffer layer 300 with a thick portion of dielectric material having a low fixed charge level at the base of the trench 92 of the cut metal gate (CMG) isolation region 110. In the embodiments shown in Figures 29 through 31, the buffer layer 300 is formed by a cycle of deposition and etching steps, wherein the erosiveness of the etching step has been adjusted to remove the entire buffer layer 300 from the upper portion 302 of the trench 92, while the thicker portion of the buffer layer 300 remains at the base of the lower portion 303 of the trench 92. In the embodiments shown in Figures 29 through 31, the buffer layer 300 is deposited using a directional deposition process. The etching process for removing the buffer layer 300 from the upper portion 302 of the trench 92 is described with reference to Figure 17J.

[0096] Figure 29 illustrates an embodiment of the buffer layer 300, which is formed through a combination of a directional deposition process as described above with reference to Figure 26 and an etching process as described above with reference to Figure 17J. The directional deposition process for forming the buffer layer 300 shown in Figure 29 results in a greater thickness of the buffer layer 300 in the lower portion 303 of the trench 92. The portion of the buffer layer 300 located at the base of the lower portion 303 of the trench 118 has a flat upper surface. The buffer layer 300 shown in Figure 29 has been removed from the entire upper portion 302 of the trench 92. A filler dielectric 305 is formed directly on top of the buffer layer 300.

[0097] Figure 30 illustrates a buffer layer 300 formed through a combination of a direct deposition step (refer to Figure 27) and an etch process (refer to Figure 17J). The buffer layer 300 shown in Figure 30 has been removed from the entire upper portion 302 of the trench 92 of the cut metal gate (CMG) isolation region 110 and includes the thicker portion of the buffer layer 300 in the lower portion 303 of the trench 92, which has a raised upper surface. A filler dielectric 305 is formed directly on top of the buffer layer 300.

[0098] Figure 31 illustrates a buffer layer 300 for a cut metal gate (CMG) isolation region 110, formed by a combination of a directional deposition step described with reference to Figure 28 and an etch process described with reference to Figure 17J. The buffer layer shown in Figure 31 has been removed from the entire upper portion 302 of the trench 92 and includes a thicker portion of the buffer layer 300 in the lower portion 303 of the trench 92, which has a concave upper surface. A filler dielectric 305 is formed directly on top of the buffer layer 300.

[0099] Figure 32 illustrates one embodiment of applying a planarization process to the portions of the buffer layer 300 and the fill dielectric 305 extending outside the trench 92 of the cut metal gate (CMG) isolation region 110. The planarization process may include chemical mechanical polishing (CMP). It is worth noting that although Figure 32 illustrates the application of a planarization process to the buffer layer 300 and the fill dielectric 305 in the embodiment shown in Figure 24, the planarization process shown in Figure 32 is equally applicable to any embodiment described with reference to Figures 24 through 31.

[0100] Figures 33 through 36 illustrate another embodiment of how the buffer layer 300 is integrated into the trench 92 of the cut metal gate (CMG) isolation region 110. In the above embodiment, after forming the buffer layer 300, a filler dielectric 305 is deposited to fill the trench 92. In some embodiments, the filler dielectric 305 does not necessarily need to fill the entire trench. In the embodiment shown in Figures 33 through 36, after forming the filler dielectric 305, a low-k dielectric filler material 306 may be deposited to fill the trench 92. The integration of the low-k dielectric filler material 306 can reduce the incidence of parasitic capacitance in the region surrounding the isolation structure. In this embodiment, the filler dielectric 305 may have a liner geometry, while the low-k dielectric filler material 306 may be the filler material filling the remaining opening portion of the trench 92. In some embodiments, the low-k dielectric filler material 306 is composed of silicon oxide (SiO2). However, in other embodiments, the low-k dielectric filler 306 may be composed of any material having a silicon oxide dielectric constant (e.g., about 4.0 or less) at room temperature. The low-k dielectric filler 306 may be deposited via chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)) and / or atomic layer deposition (ALD) (e.g., plasma-enhanced atomic layer deposition (ALD)).

[0101] Figure 33 illustrates one embodiment of a low-k dielectric filler material 306 integrated onto a filler dielectric layer 305 situated above a buffer layer 300, which is formed using the deposition and etching cycles described above with reference to Figure 24. Figure 34 illustrates one embodiment of a low-k dielectric filler material 306 integrated onto a filler dielectric layer 305 situated above a buffer layer 400, which is formed using the deposition and etching cycles described above with reference to Figure 25. In the embodiment shown in Figure 34, the buffer layer 300 is removed from the entire upper portion 302 of the trench 92. Figure 35 illustrates one embodiment of a low-k dielectric filler material 306 integrated onto a filler dielectric 305 located above a buffer layer 400, which is formed using a deposition and etching cycle as described above with reference to Figure 26. The buffer layer shown in Figure 35 has a thicker portion of the low fixed charge level dielectric composition material with a flat upper surface at the base of the trench 92. Figure 36 illustrates one embodiment of a low-k dielectric filler material 306 integrated onto a filler dielectric 305 located above a buffer layer 400, which is formed using a deposition and etching cycle as described above with reference to Figure 29. The buffer layer 300 has been completely removed from the upper portion 302 of the trench 92. The buffer layer 300 shown in Figure 36 has a thick portion of dielectric composition material with a low fixed charge level, and has a flat upper surface at the base of the trench 92.

[0102] Although the low-k dielectric filler 306 is integrated into the isolation structure of the cut-metal gate (CMG) isolation region 110, the low-k dielectric filler 306 is not limited to these embodiments. For example, the low-k dielectric filler 306 can also be used as a filler material on top of the filler dielectric 305 within the opening 118 of the fin isolation region 112 (using the CPODE process). It is worth noting that the low-k dielectric filler 306 can be integrated into any of the embodiments described herein, such as those shown in Figures 17E, 17F, 17I through 17P, and 24 through 32.

[0103] After the process shown in Figure 36, the remaining processes shown in Figures 37A, 37B, 38A, and 38B are performed to complete the formation of the transistor.

[0104] Figure 37A illustrates a cross-section of the structure shown in Figure 21, wherein a cut metal gate (CMG) isolation region 110 has been formed to cut the long metal gate stack 70 into metal gate stacks (parts) 70A and 70B. Although the cut metal gate (CMG) isolation region 110 is consistent with that in Figure 32, any embodiment of the cut metal gate (CMG) isolation region 110 described herein is applicable, for example, with reference to the embodiments described in Figures 24 through 36. Next, as shown in Figures 37A and 37B, the gate stack 70 is recessed, thereby forming a groove (occupied by the cut metal gate (CMG) isolation region 110) directly above the gate stack 70 and between the opposite portion of the gate spacer 38. Each groove is filled with a gate photomask 74 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and then a planarization process is performed to remove excess portion of dielectric material extending above the interlayer dielectric (ILD) 52.

[0105] As further shown in Figures 37A and 37B, an interlayer dielectric (ILD) 76 is deposited over the interlayer dielectric (ILD) 52 and the gate mask 74. The corresponding process is illustrated as process 230 in the process flow 200 shown in Figure 39. An etch stop layer (not shown) may or may not be deposited before forming the interlayer dielectric (ILD) 76. According to some embodiments, the interlayer dielectric (ILD) 76 is formed by flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The interlayer dielectric (ILD) 76 is formed of a dielectric material, which may be selected from silica, phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), undoped silicate glass (USG), etc.

[0106] In Figures 38A and 38B, interlayer dielectric (ILD) 76, interlayer dielectric (ILD) 52, contact etch stop layer (CESL) 50, and gate photomask 74 are etched to form grooves (occupied by contact plugs 80A and 80B), thereby exposing the surfaces of the source / drain region 48 and / or the gate stack 70. The grooves can be formed by etching using anisotropic etching processes (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.).

[0107] After the groove is formed, a siliconized region 78 is formed above the source / drain region 48. The corresponding process is illustrated as process 232 in process flow 200 shown in Figure 39. Then, a contact plug 80B is formed above the siliconized region 78. Furthermore, a contact plug 80A (also referred to as a gate contact plug) is formed in the groove and is located above and in contact with the gate electrode 68. The corresponding process is illustrated as process 234 in process flow 200 shown in Figure 39. This forms transistors 82A and 82B. Although Figure 38B shows contact plugs 80A and 80B in the same cross-section, in various embodiments, contact plugs 80A and 80B can be formed in different cross-sections, thereby reducing the risk of short-circuiting between them.

[0108] The embodiments disclosed herein have several advantageous features. In the methods and structures disclosed herein, a bottom-up deposition technique is proposed to form a buffer layer 300 in the isolation region to prevent induced charges in the isolation structure. In some embodiments, the buffer layer 300 can be selectively deposited from the base without blocking the gap opening.

[0109] In one embodiment, the method includes: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; applying at least one passivation treatment to the upper portion of the opening; forming a nonconformal material layer having a first fixed charge concentration, wherein the nonconformal material layer has a first portion passivated by at least one passivation treatment located at the upper portion of the opening, and the nonconformal material layer has a second portion extending to the base of the opening, the first portion of the nonconformal material layer having a smaller thickness than the second portion of the nonconformal material layer; and depositing a filling dielectric having a second fixed charge concentration higher than the first fixed charge concentration on the nonconformal material layer.

[0110] In one embodiment, at least one conductive structure comprises a plurality of semiconductor regions. In one embodiment, at least one conductive structure comprises a gate structure present on a semiconductor region. In one embodiment, the nonconformal material layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon oxycarbonitride (SiCON). In one embodiment, passivation is a heat treatment at a temperature above 600˚C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or combinations thereof, wherein the heat treatment comprises a pressure of 10 Torr to 5 atm (ATM). In one embodiment, passivation is a plasma treatment comprising a plasma comprising argon, helium, hydrogen, or combinations thereof, wherein the plasma treatment comprises a temperature of 300˚C to 500˚C, wherein the plasma treatment comprises a pressure of 10 Torr to 5 atm (ATM). In one embodiment, the thickness difference between a first portion of the nonconformal material layer and a second portion of the nonconformal material layer is 2 nm to 10 nm.

[0111] In one embodiment, the method includes: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; forming a buffer layer having a fixed charge concentration lower than that of silicon nitride; etching the buffer layer to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer includes a first portion above the opening, the thickness of which is less than that of a second portion of the buffer layer at the base of the opening; and depositing a fill dielectric on the buffer layer having the non-conformal thickness. In one embodiment, the buffer layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon carbon oxynitride (SiCON). In one embodiment, the etching comprises a fluorine-based etchant. In one embodiment, the etching comprises plasma etching, the plasma etching comprising a pressure of 10 Torr to 30 Torr, a temperature of 300˚C to 500˚C, and a plasma having a higher radical to ion ratio. In one embodiment, forming the buffer layer comprises directional deposition. In one embodiment, forming the buffer layer comprises conformal deposition. In one embodiment, the method further includes forming a low-k dielectric filler on the filler dielectric, wherein the filler dielectric comprises silicon nitride.

[0112] In one embodiment, the structure includes: at least one conductive feature; a trench extending through the conductive feature; and a trench filler comprising: a non-conformal material layer having a fixed charge concentration lower than that of silicon nitride, wherein the non-conformal material layer has a first portion located above the trench and having a first thickness, and a second portion extending to the base of the trench and having a second thickness, wherein the second thickness is less than the first thickness; and a filling dielectric on the non-conformal material layer. In one embodiment, the at least one conductive feature is a gate structure. In one embodiment, the at least one conductive feature is a stack of nanosheets. In one embodiment, the non-conformal material layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon carbon oxynitride (SiCON). In one embodiment, the thickness difference between the first thickness and the second thickness is 2 nm to 10 nm. In one embodiment, the filling dielectric comprises silicon nitride.

[0113] The numerous implementation methods or embodiments outlined above enable those skilled in the art to better understand the embodiments disclosed herein. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes or structures to achieve the same purpose and / or realize the same advantages of the implementation methods or embodiments described herein. Those skilled in the art should also recognize that equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

[0114] 10: Wafer 20: Substrate 20': Substrate strip 22,22': Multi-layer stacking 22A: First layer / Sacrificial semiconductor layer 22B: Second layer / nanostructure 23,92: Trench 24: Semiconductor Strip 26: Quarantine Zone 26T: Top surface 28: Protruding fins 30: Virtual Gate Stacking 32: Virtual gate dielectric 34: Virtual gate electrode 36: Hard Light Mask 38: Gate spacer 41: Horizontal groove 42, 58: Groove 44: Internal spacers 48: Source / Drain Region, Epitaxial Region 50: Contact Etching Stop Layer 52,76: Interlayer dielectric 62: Gate Dielectric 68: Gate electrode 70, 70A, 70B: Gate stacking 74: Gate Electrode Cover 78: Silicone region 80A, 80B: Contact plugs 82A, 82B: Transistors 88: Hard photomask layer 88A, 88C: Silicon nitride layers 88B: Silicon layer 90: Etched photomask 110: Cutting the metal gate region 112: Fin isolation zone 116: Hard Photomask 117: Etched Photomask 118, 120: Opening 200: Manufacturing Process 202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232,234: Manufacturing Process 300, 400: Buffer layer 301: Suppression / Passivation Treatment 302: Upper part 303: Lower part 305: Filled dielectric 306: Low-k dielectric filler material A1-A1,BB: Cross section W1, W2: Width X, Y: Direction

[0115] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor structure, comprising: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; applying at least one passivation treatment to an upper portion of the opening; forming a nonconformal material layer having a first fixed charge concentration, wherein the nonconformal material layer has a first portion passivated by the at least one passivation treatment on the upper portion of the opening, and the nonconformal material layer has a second portion extending to a base of the opening, the first portion of the nonconformal material layer having a thickness smaller than the second portion of the nonconformal material layer; and depositing a filling dielectric on the nonconformal material layer, the filling dielectric having a second fixed charge concentration higher than the first fixed charge concentration of the nonconformal material layer, wherein the filling dielectric and the nonconformal material layer comprise different materials.

2. The method as described in claim 1, wherein the at least one conductive structure comprises a plurality of semiconductor regions.

3. The method as described in claim 1, wherein the at least one conductive structure comprises a gate structure on a semiconductor region.

4. The method as described in claim 1, wherein the non-conformal material layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon carbon oxynitride (SiCON).

5. The method as claimed in claim 1, wherein the passivation process is a heat treatment performed at a temperature above 600˚C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or a combination thereof, wherein the heat treatment comprises a pressure of 10 Torr to 5 Atm (ATM).

6. The method as claimed in claim 1, wherein the passivation process is a plasma process comprising a plasma including argon, helium, hydrogen, or a combination thereof, wherein the plasma process comprises a temperature of 300˚C to 500˚C, and wherein the plasma process comprises a pressure of 10 Torr to 5 Atm (ATM).

7. The method as described in claim 1, wherein a thickness difference between the first portion of the non-conformal material layer and the second portion of the non-conformal material layer is 2 nm to 10 nm.

8. A method of forming a semiconductor structure, comprising: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; forming a buffer layer having a fixed charge concentration lower than that of silicon nitride; etching the buffer layer to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer includes a first portion in an upper portion of the opening, the first portion having a thickness smaller than that of a second portion of the buffer layer in a base portion of the opening; and depositing a filler dielectric on the buffer layer having the non-conformal thickness, wherein the filler dielectric and the buffer layer comprise different materials.

9. The method of claim 8 further comprises forming a low-k dielectric filler on the filler dielectric, wherein the filler dielectric comprises silicon nitride.

10. A semiconductor structure comprising: at least one conductive feature; a trench extending through the conductive feature; and a trench filler comprising: a non-conformal material layer having a first fixed charge concentration, wherein the non-conformal material layer has a first portion located on an upper portion of the trench, the first portion having a first thickness, and the non-conformal material layer has a second portion extending through a base of the trench and having a second thickness, wherein the second thickness is less than the first thickness; and a filling dielectric having a second fixed charge concentration higher than the first fixed charge concentration on the non-conformal material layer, wherein the filling dielectric and the non-conformal material layer comprise different materials.

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