Content-addressable memory

Abstract

A content-addressable memory includes a voltage mode selector, a memory array, and a self-test circuit. The voltage mode selector outputs the system voltage as a power supply voltage to the memory cells of the memory array via a row address signal. The memory cells receive control signals output by the controller. The comparison unit of the memory array receives lookup data and compares it with the data stored in the memory cells to see if they match. The self-test circuit transmits test data and random addresses to the controller. The controller outputs control signals to the memory array, writes the test data into the random addresses of the memory array, and then reads the data stored in the random addresses of the memory array into the self-test circuit for comparison.

Claims

1. A content-addressable memory, comprising: a voltage mode selector that receives a system voltage and a row address signal, wherein the voltage mode selector outputs a power supply voltage from the system voltage via the row address signal; a memory array having a plurality of memory cells and a plurality of comparison units, each memory cell being electrically connected to the voltage mode selector to receive the power supply voltage, the memory cells also receiving a plurality of control signals output by a controller, the memory cells being controlled by the control signals to be written to or read from data, each comparison unit being electrically connected to each memory cell, the comparison unit receiving lookup data and comparing the data stored in each memory cell against the lookup data to output a comparison signal; and a built-in self-testing circuit. The self-test circuit (BIST) is electrically connected to the memory array. The self-test circuit transmits test data and a random address to the controller. The controller outputs the control signal to the memory array to write the test data into the random address of the memory array. The controller then compares the data stored in the random address of the memory array with the self-test circuit.

2. As requested in Item 1, the memory array is addressable, wherein each memory cell of the memory array has a first storage transistor, a second storage transistor, a pull-up transistor, a discharge transistor, a transmission transistor, and a disturbance suppressor transistor. The first storage transistor is electrically connected to the voltage mode selector to receive the power supply voltage and is electrically connected to a data storage node and an inverting data storage node. The second storage transistor is electrically connected to the data storage node and the inverting data storage node. The pull-up transistor is electrically connected to the first storage transistor, the second storage transistor, and a transmission node. The pull-up transistor receives a pull-up control signal. The discharge transistor is electrically connected to the data storage node, the inverting data storage node, and a ground terminal. The transmission transistor is electrically connected to the inverting data storage node and the transmission node, and receives a transmission control signal. The disturbance suppressor transistor is electrically connected to the transmission node and an inverting data bit line, and receives a disturbance suppressor control signal.

3. If the content of request item 2 is addressable memory, the comparison unit has a first comparison data transistor, a storage data control transistor, an inverting storage data control transistor, and a second comparison data transistor. The first comparison data transistor receives the lookup data and a precharge signal. The storage data control transistor is electrically connected to the data storage node and receives the lookup data. The inverting storage data control transistor is electrically connected to the inverting data storage node, the storage data control transistor, and the comparison data transistor. The second comparison data transistor is electrically connected to the first comparison data transistor and the inverting storage data control transistor and receives the lookup data. The comparison signal is output at the connection point between the storage data control transistor and the inverting storage data control transistor.

4. If the content of request item 1 is addressable memory, wherein the voltage mode selector has an inverting horizontal control transistor, a load transistor and a horizontal control transistor, the inverting horizontal control transistor and the load transistor receive the system voltage, and the inverting horizontal control transistor receives an inverting horizontal address signal, the horizontal control transistor is electrically connected to the inverting horizontal control transistor and the load transistor, and the horizontal control transistor receives a horizontal address signal, and the connection between the inverting horizontal control transistor and the horizontal control transistor outputs the power supply voltage.

5. As requested in item 2, the memory array has a positive feedback sensing amplifier (PFSA) electrically connected to the inverting data bit line and a data bit line.

6. As requested in item 5, the addressable memory includes a positive feedback sensing operational amplifier comprising a PFSA pull-up crystal, a cross-coupled amplifier, an inverter, an output pull-up crystal, and an output pull-down crystal. The PFSA pull-up crystal receives the system voltage and a PFSA control signal. The cross-coupled amplifier is electrically connected to the PFSA pull-up crystal, the inverting data bit line, and the ground terminal, and the cross-coupled amplifier receives inverted data from the inverting data bit line. The inverter is electrically connected to the cross-coupled amplifier. The output pull-up crystal is electrically connected to the inverter, and the output pull-up crystal receives the system voltage. The output pull-down crystal is electrically connected to the output pull-up crystal and the ground terminal, and the output pull-down crystal receives the PFSA control signal. A data signal is output to the data bit line at the connection between the output pull-up crystal and the output pull-down crystal.

7. If the content of request item 1 is addressable memory, wherein the self-test circuit has a sample generation circuit, a self-test control circuit, and a self-test analysis circuit, the sample generation circuit receives a self-test enable signal and a clock signal, the sample generation circuit outputs the random address, the self-test control circuit receives the self-test enable signal, the clock signal, and a hold time signal, the self-test control circuit outputs the test data, the self-test analysis circuit is electrically connected to the self-test control circuit and the memory array to receive the test data, the self-test analysis circuit also receives the data stored at the random address of the memory array, the self-test analysis circuit compares the test data and the stored data to see if they are the same and outputs a self-test comparison signal.

8. If the content of request item 7 is addressable memory, wherein the sample generation circuit of the self-test circuit has a plurality of multiplexers, a plurality of sample generation flip-flops and an XNOR gate, each of the multiplexers and each of the sample generation flip-flops connected to each other constitutes a random address generation unit, the plurality of random address generation units are connected in series with each other, the XNOR gate is electrically connected to the random address generation units, each of the multiplexers and each of the sample generation flip-flops receives the self-test enable signal, and the random address generation units are connected in series to output the random address.

9. If the content of request item 7 is addressable memory, wherein the self-test control circuit of the self-test circuit has a first inverter, a NOR gate, a first self-test control flip-flop, a second self-test control flip-flop, and a second inverter, the first inverter receives the self-test enable signal, the NOR gate is electrically connected to the first inverter to receive the inverted self-test enable signal, the NOR gate also receives the hold time signal, the first self-test control flip-flop is electrically connected to the NOR gate, the first self-test control flip-flop also receives the clock signal, the second self-test control flip-flop is electrically connected to the first self-test control flip-flop, and the second self-test control flip-flop also receives the clock signal, the second self-test control flip-flop outputs the test data, the second inverter is electrically connected to the first and second self-test control flip-flops to receive the test data, and the second inverter outputs the inverted test data to the first self-test control flip-flop.

10. If the content of request item 9 is addressable memory, wherein the self-test analysis circuit has a test analysis flip-flop and an XNOR gate, the test analysis flip-flop is electrically connected to the second self-test control flip-flop to receive the test data, the XNOR gate is electrically connected to the test analysis flip-flop, and the XNOR gate receives the data stored at the random address of the memory array, and the XNOR gate outputs the self-test comparison signal.

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