Semiconductor device and method for forming the same
Patent Information
- Application Number
- TW114126295
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2045-07-10
Smart Images

Figure TWG2TB001917291_001 
Figure TWG2TB001917291_002 
Figure TWG2TB001917291_003
Abstract
Claims
1. A semiconductor device, comprising: A substrate having an active region and an isolation region adjacent to the active region; A stacked structure disposed on the substrate includes: a bit line plug located within the active region and protruding above the substrate; a bit line located on the bit line plug; an insulating cap layer located on the bit line; and a first spacer layer and a second spacer layer sequentially covering one side wall surface of the stacked structure from the inside out, wherein the insulating cap layer protrudes above the tops of the first spacer layer and the second spacer layer, such that there is a first step difference between the top of the insulating cap layer and the top of the first spacer layer, and a second step difference between the insulating cap layer and the top of the second spacer layer.
2. The semiconductor device as claimed in claim 1, wherein the first step difference is greater than the second step difference, and the second spacer covers the top of the first spacer.
3. The semiconductor device as described in claim 1, further comprising: A protective layer covers the top of the insulating cover, the first spacer liner, and the second spacer liner; And an insulating layer extending from one bottom of the second spacer liner into the isolation zone.
4. The semiconductor device as claimed in claim 3, wherein the protective layer extends from an outer sidewall surface of the second spacer to an upper surface of the substrate and into the isolation region, and the first spacer extends into the isolation region to partially surround the insulating layer and contact the protective layer located within the isolation region.
5. A method for forming a semiconductor device, comprising: A substrate is provided having a groove formed in an active region and an isolation region; A stacked structure is formed within the groove, wherein the stacked structure includes: a bit line plug located within the active region and protruding above the substrate; a bit line located on the bit line plug; and an insulating cap layer located on the bit line; a first spacer layer and a second spacer layer are sequentially formed to cover one sidewall surface of the stacked structure from the inside out and expose a top of the insulating cap layer, wherein the first spacer layer extends within the groove; and the first spacer layer and the second spacer layer are recessed such that the top of the insulating cap layer protrudes beyond the tops of the first spacer layer and the second spacer layer, wherein there is a first step difference between the top of the insulating cap layer and the top of the first spacer layer, and a second step difference between the insulating cap layer and the top of the second spacer layer.
6. The method of forming a semiconductor device as described in claim 5 further includes: Before the second spacer is formed, an insulating layer is formed on the first spacer within the groove, wherein the second spacer is located on top of the insulating layer.
7. The method of forming a semiconductor device as described in claim 6 further includes: A protective layer is formed to cover the tops of the insulating cover, the first spacer liner, and the second spacer liner, and to cover an outer wall surface of the second spacer liner and a side wall surface of the insulating layer.
8. A method for forming a semiconductor device, comprising: A substrate is provided having a groove formed in an active region and an isolation region; A stacked structure is formed within the groove, wherein the stacked structure includes: a bit line plug located within the active region and protruding above the substrate; a bit line located on the bit line plug; and an insulating capping layer located on the bit line; a first spacer material layer is formed to cover one sidewall surface of the stacked structure and a top of the insulating capping layer, and extends within the groove; a first portion of the first spacer material layer is removed to expose the top of the insulating capping layer, wherein the top of the insulating capping layer protrudes beyond the top of the first spacer material layer; and a second spacer material layer is formed to cover the first spacer material layer and the insulating capping layer. The second spacer material layer is recessed to form a second spacer liner, wherein the top of the insulating cover layer protrudes beyond the top of the second spacer liner and exposes the first spacer material layer located on the substrate, wherein there is a second step difference between the top of the insulating cover layer and the top of the second spacer liner; and a second portion of the first spacer material layer located in the recess is removed to form a first spacer liner, wherein there is a first step difference between the top of the insulating cover layer and the top of the first spacer liner.
9. The method of forming a semiconductor device as described in claim 8 further includes: Before the second spacer liner is formed, an insulating layer is formed on the first spacer material layer within the groove, wherein the second spacer liner is located on top of the insulating layer.
10. The method of forming a semiconductor device as described in claim 9 further includes: After the first spacer liner is formed, a protective layer is formed to cover the tops of the insulating cover, the first spacer liner, and the second spacer liner, and to cover an outer sidewall surface of the second spacer liner and a sidewall surface of the insulating layer, wherein the protective layer extends into the groove to contact the first spacer liner.
Citation Information
Patent Citations
Semiconductor structure and forming method of the same
TW202420937A
Semiconductor memory device
US20230320080A1
