SWITCHED CAPACITOR POWER AMPLIFIER (ScPa) APPARATUS AND METHOD FOR CONTROLLING ScPa

Abstract

This specification describes an analog-cutting technique for a switched-capacitor power amplifier. The switched-capacitor power amplifier includes an array of multiple unit cells capable of sharing between in-phase (I) and quadrature-phase (Q) components. A pair of control bits is associated with each unit cell, including a first control bit for selectively enabling the unit cell to use the in-phase component, and a second control bit for selectively enabling the unit cell to use the Q component. Truth tables are configured for a first subset and a second subset of the multiple unit cells, such that the first subset is driven by the in-phase component in response to a double-enable condition of the individual pair of control bits. Truth tables are configured to drive the second subset of unit cells by the Q component in response to the double-enable condition.

Description

[Technical Field]

[0001] This specification is generally related to wireless communication technology. For example, some aspects of this specification relate to the tailoring of digital power amplifiers and / or switched capacitor power amplifiers, tailoring schemes that can be implemented in the output unit of a local capacitor array in the amplifier. [Previous Technology]

[0002] Power amplifiers (PAs) are used in radio frequency (RF) transmitters, which transmit electromagnetic energy. Because PAs can account for a large portion of the power consumed by a radio system, their efficiency significantly impacts the power consumption of the transceiver. PAs receive direct current (DC) power input and provide RF power output. The power conversion efficiency from DC power input to RF power output directly corresponds to the overall efficiency of the PA. Improving PA efficiency, or the power conversion efficiency from DC input to RF output, can save energy and extend the battery life of various mobile and / or wireless devices that use PAs. PAs are typically designed to achieve maximum power efficiency when operating at maximum output power. When a PA operates within various reduced output power ranges below its maximum output power, its power efficiency may decrease significantly.

[0003] Recently, digital power amplifiers (DPAs) have attracted increasing interest because they can integrate multiple functions and / or functionalities, such as digital-to-analog converters (DACs), frequency up-converters / mixers, and power amplifiers (PAs). Using DPAs in RF transceivers can improve energy efficiency and reduce power consumption, and can also reduce the chip area of ​​the implemented RF transceiver (e.g., based on multiple functions integrated into or performed by the DPA). "High-power" DPAs are directly related to relatively high power consumption, and various techniques can be employed to optimize efficiency. However, the efficiency optimizations currently used in high-power DPAs can also introduce distortion, especially when the input amplitude code driving the DAC (such as a DAC included in or integrated into the DPA) is quite large. The in-phase (I) and quadrature-phase (Q) components of the input signal can be separated and coupled to different segments of the DPA. The encoding circuitry in a DPA maps the individual amplitudes of the I and Q components to drive these independent segments of the DPA. The signals output from each segment are then summed (e.g., combined) to produce the final output of the DPA. A switched capacitor power amplifier (ScPa) is a type of DPA that uses capacitors paired with transistors as switches to achieve high linearity and efficiency, especially at higher output power levels. In the ScPa architecture, capacitors in the array can be selectively driven (or not driven) using an input clock signal, turning them on or off. The selective activation of capacitors can be controlled by amplitude codes derived from the amplitudes of the I and Q components of the input signal. For example, the amplitudes of the I and Q components can be encoded as amplitude codes and used to control the activation of specific capacitors in each capacitor array of the ScPa. [Summary of the Invention]

[0004] The following is a brief summary of one or more aspects disclosed in this specification. Therefore, it should not be considered a general overview of all aspects under consideration, nor should it be regarded as a key or essential element for identifying the relevant scope of all or any aspect under consideration. Thus, the sole purpose of the following overview is to present, in a concise manner, some concepts of one or more relevant aspects of the mechanisms disclosed in the specification before a detailed description.

[0005] This specification discloses systems, methods, apparatuses, and computer-readable media for digital power amplifiers with analog-cutting schemes. In one illustrative example, a switched capacitor power amplifier (ScPa) apparatus is provided, comprising: a switched capacitor array containing an input radio frequency signal (radio...) Multiple unit cells shared between the in-phase (I) and quadrature-phase (Q) components of the frequency (RF), each unit cell containing a capacitor and an inverter; a corresponding control bit pair associated with each unit cell, wherein the corresponding control bit pair contains a first control bit and a second control bit, the first control bit being configured to selectively enable or disable the drive of the corresponding unit cell based on the I component, and the second control bit being configured to selectively enable or disable the drive of the corresponding unit cell based on the Q component; and truth table logic for configuring a first unit cell subset and a second unit cell subset of the multiple unit cells, wherein the truth table logic responds to a double enable condition of the corresponding control bit pair to drive the first unit cell subset based on the I component, and the truth table logic responds to a double enable condition of the corresponding control bit pair to drive the second unit cell subset based on the Q component.

[0006] In some aspects, the ScPa device implements an analog slicing scheme based on a set of dual-enabled unit cells of a switching capacitor array configured with truth table logic, wherein the set of dual-enabled unit cells is contained within a plurality of unit cells.

[0007] In some aspects, the analog slicing scheme is implemented to use truth table logic to drive the unit cells of the first half of the group with the dual enable condition at an I clock corresponding to the I component, and to drive the unit cells of the second half of the group with the dual enable condition at a Q clock corresponding to the Q component.

[0008] In some respects, the unit cell of the group having dual-energized conditions is equal to the difference between the sum of the amplitudes of the I component and the Q component and the number of multiple unit cells.

[0009] In some respects, the dual enable condition is set to a high value for each bit of the corresponding control bit pair, indicating that the corresponding unit can be driven based on the I component and the corresponding unit can be driven based on the Q component.

[0010] In some respects, the first unit cell subset contains multiple unit cells of the first half, and the second unit cell subset contains multiple unit cells of the second half.

[0011] In some respects, the number of unit cells in the first unit cell subset is equal to the number of unit cells in the second unit cell subset.

[0012] In some aspects, the first subset of unit cells includes odd-indexed unit cells of the switched capacitor array, and the second subset of unit cells includes even-indexed unit cells of the switched capacitor array.

[0013] Optionally, the first subset of unit cells includes even-indexed unit cells of the switched capacitor array, and the second subset of unit cells includes odd-indexed unit cells of the switched capacitor array.

[0014] In some aspects, one of the first unit cell subset and the second unit cell subset contains an even-indexed unit cell of a switched capacitor array, and the other of the first unit cell subset and the second unit cell subset contains an odd-indexed unit cell of a switched capacitor array.

[0015] In some respects, truth table logic allows multiple unit cells to be driven according to corresponding control bit pairs without the need for double enable conditions.

[0016] In some aspects, the truth table logic encoding encodes the priority of the I component of the first unit cell subset as higher than the priority of the Q component, and the truth table logic maps the encoding of the priority of the I component as higher than the priority of the Q component to a double enable condition, wherein the first control bit and the second control bit of the corresponding unit cell in the first unit cell subset are both set to high values.

[0017] In some aspects, the truth table logic encodes the priority of the Q component of the second unit cell subset as higher than the priority of the I component, and the truth table logic maps the encoding of the priority of the Q component as higher than the priority of the I component to the double enable condition, where the first control bit and the second control bit of the corresponding unit cell in the second unit cell subset are both set to high values.

[0018] In some respects, each of the multiple unit cells in the switching capacitor array is switched and coupled to the main input of the inductor transformer or balun in the ScPa device.

[0019] In some respects, the truth table logic enables the switched capacitor power amplifier device to automatically implement an analog clipping scheme for IQ amplitude codes whose sum of amplitudes is greater than the number of unit cells in the plurality of unit cells; and each unit cell with dual enable conditions implements the analog clipping scheme locally based on the truth table logic configured for each unit cell with dual enable conditions.

[0020] In some aspects, the ScPa device further includes a level shifter in an output switching unit, wherein the output switching unit includes an NMOS switching device gate, an NMOS series gate, a PMOS series gate, and a PMOS switching device gate.

[0021] In some aspects, the gate of the NMOS switching device is driven by a core voltage inverter driven by the core voltage (VDDL) rail, the NMOS series gate is coupled to the core voltage rail, the PMOS series gate is biased below the fixed voltage of the input-output voltage (VDDH) rail, and the PMOS switching device gate performs signal voltage conversion through the capacitor between the NMOS switching device gate and the PMOS switching device gate to charge to the VDDH-VDDL voltage.

[0022] In some respects, the input-output voltage (VDDH) is set to be at most twice the core voltage (VDDL).

[0023] In some respects, the output switching unit also includes cross-coupled PMOS elements for periodically replenishing any small amount of charge that leaks from the capacitor over time.

[0024] In some aspects, the PMOS series gate is coupled to a charge pump driven by a core voltage level clock input, and the core power supply voltage of the charge pump is DC-DC converted through a series capacitor to produce a rail that is one core voltage lower than the input and output voltage rails.

[0025] In another illustrative example, a method is provided for controlling an ScPa with adaptive clipping, the method comprising: acquiring I-codes and Q-codes corresponding to an input radio frequency signal; comparing the sum of the absolute values ​​of the I-codes and Q-codes with a threshold corresponding to the number of unit cells in a plurality of unit cells of a switched capacitor array of the ScPa; determining, based on the I-codes and Q-codes, each output unit of the inverter and capacitor array in the ScPa is an I-clock enabled output unit, a Q-clock enabled output unit, a dual-enabled output unit, or a disabled output unit, wherein, when the I-codes and Q-codes are... When the sum of the absolute values ​​of the codes is less than or equal to a threshold, the number of dual-enabled output units is zero; and when the sum of the absolute values ​​of the I codes and Q codes is greater than the threshold, the number of dual-enabled output units is equal to the sum of the absolute values ​​of the I codes and Q codes minus the threshold; half of the dual-enabled output units are controlled to be driven by the I clock, and the other half are controlled to be driven by the Q clock; the output units controlled by the I clock of the inverter and capacitor array are driven by the I clock; and the output units controlled by the Q clock of the inverter and capacitor array are driven by the Q clock.

[0026] In some aspects, the operation of controlling ScPa includes: implementing an analog slicing scheme based on a set of unit cells with dual enable conditions of a switching capacitor array having truth table logic, wherein the set of unit cells with the dual enable conditions is included in a plurality of unit cells.

[0027] In some aspects, the truth table logic allows the unit cells of the first half of the group with the dual enable condition to be driven by an I clock corresponding to an I code, and allows the unit cells of the second half of the group with the dual enable condition to be driven by a Q clock corresponding to a Q code.

[0028] Those skilled in the art can understand the purposes and advantages associated with the above-mentioned aspects based on the accompanying diagrams and detailed description.

Implementation Method

[0044] Several aspects and embodiments of this disclosure are provided below. Some embodiments can be implemented independently, while others can be combined and implemented by those skilled in the art where readily apparent. The following description is for illustrative purposes only, and specific details are provided to provide a complete understanding of the various aspects of this application. However, it will be apparent that these embodiments are not necessarily to be implemented in such exhaustive detail. The accompanying drawings and description are not intended to limit the scope of the invention.

[0045] The following description is merely illustrative of various aspects and is not intended to limit the scope, application, or setting of this disclosure. Rather, the various aspects of the description will provide a framework for implementation by those skilled in the art. It should be understood that the function and arrangement of the elements may be changed without departing from the scope and spirit of the claims. Overview

[0046] In some aspects of embodiments of the present invention, novel and effective power amplifier (PA) trimming techniques can be provided to reduce and / or minimize distortion or other performance degradation that may be associated with driving the power amplifier beyond its configured output level or other operating regions. In some embodiments, the systems and techniques described in the specification can be used to achieve more efficient PAs by combining the outputs of two or more independent PAs, wherein the independent PAs operate for different regions of the input signal or signal components. In one illustrative example, a switched capacitor power amplifier (ScPa) is used to address challenges and problems that may be encountered when using a digital to analog converter (DAC) because the ScPa is a fully digital power amplifier. Some aspects of the specification include implementations of combining the ScPa with integrated complementary metal-oxide-semiconductor (CMOS) systems.

[0047] In some aspects of embodiments of the present invention, there is a digitally controlled ScPa system for power amplification with improved power efficiency. For example, the digitally controlled ScPa system is capable of combining the outputs of two independent ScPas, at least in part based on the observed output impedance of the ScPa being constant across all gain settings. Preferably, embodiments of this specification can be implemented by configuring and / or reconfiguring elements already present in the ScPa to obtain a combiner for combining the outputs of two independent PAs. Thus, the improved efficiency digitally controlled ScPa system described in this specification can be implemented without adding additional large and / or complex physical circuitry, etc. In some embodiments, some aspects described in the specification include configuring amplifier control during operation in a Cartesian system to combine in-phase (I) and quadrature-phase (Q) signals without experiencing the efficiency degradation typically associated with integrated mixers. Furthermore, this system and technique can be used to modify combiner arrangements to maximize power efficiency at multiple backoff levels, including maximizing efficiency at 12 dB backoff and at 6 dB backoff. Embodiments

[0048] Figure 1 shows a block diagram of an exemplary wireless communication network 100. In some aspects, the wireless communication network 100 may be an example of a Wireless Local Area Network (WLAN). Used here, the WLAN may be a Wi-Fi network. In some examples, the WLAN 100 may be a network implementing at least one of the IEEE 802.11 family of wireless communication protocol standards (e.g., standards defined in the IEEE 802.11-2020 specification or its amendments, including but not limited to 802.11ah, 802.11ay, 802.11ax, 802.11az, 802.11ba, and 802.11be). The WLAN 100 may include at least an access point 102 and a plurality of associated sites 104. For example, site 104 may include a first site 104a, a second site 104b, a third site 104c, a fourth site 104d, etc. Although only one access point 102 is shown in the diagram, WLAN 100 can actually contain multiple access points 102.

[0049] Any of sites 104a to 104d may be referred to as a mobile station (MS), mobile device, mobile handheld device, access terminal (AT), user equipment (UE), subscriber station (SS), and / or subscriber unit, etc. Site 104 may represent various devices, such as mobile phones, handheld devices, laptops, computers, tablets, laptops, display devices (e.g., televisions, computer monitors, navigation systems, etc.), music or other audio or stereo devices, remote control devices ("remote controllers"), printers, kitchen or other household appliances, key rings (e.g., for Passive Keyless Entry and Start (PKES) systems), etc.

[0050] The collection of a single access point 102 and its associated sites 104a to 104d can be collectively referred to as a Basic Service Set (BSS), which is managed by the individual access point 102. Figure 1 further shows an example coverage area 106 of access point 102, which can represent the Basic Service Area (BSA) of WLAN 100. The BSS can be identified by a Service Set Identifier (SSID) for users and by a Basic Service Set Identifier (BSSID) for other devices, which can be the Medium Access Control (MAC) address of access point 102.

[0051] Access point 102 periodically broadcasts beacon frames (“beacons”) containing a BSSID to enable any station within the wireless range of access point 102 (such as one or more, or all, of stations 104a to 104d) to associate with or re-associate with access point 102 to establish individual communication connections (also referred to herein as “Wi-Fi connections”) 108a to 108d. For example, a first station 104a may establish a specific communication connection 108a with access point 102, a second station 104b may establish a specific communication connection 108b with access point 102, a third station 104c may establish a specific communication connection 108c with access point 102, a fourth station 104d may establish a specific communication connection 108d with access point 102, and so on. Sites 104a to 104d can further use beacon frames broadcast by access point 102 to maintain their respective communication links 108a to 108d with access point 102. For example, the beacon may contain identification information of the main channel used by the individual access point 102, as well as a timing synchronization function for establishing or maintaining time synchronization with access point 102. Access point 102 can allow various different sites to access the external network through their respective communication links 108.

[0052] To establish communication links 108a to 108d with access points 102, each of its respective stations 104a to 104d may perform passive or active scanning operations (“scans”) on frequency channels in one or more frequency bands. For example, to perform a passive scan, each of stations 104a to 104d listens for beacons transmitted from access point 102 at periodic time intervals, called Target Beacon Transmission Time (TBTT). TBTT can be measured in Time Units (TU). In some embodiments, TBTT may be a preset value of 1024 microseconds (µs). In some embodiments, TBTT may be a preset value of 102.4 milliseconds (ms). To perform active scanning, each of sites 104a to 104d can generate a probe request and sequentially send the probe request on each channel to be scanned by access point 102, and listen for probe responses sent from access point 102. Each of sites 104a to 104d can be configured to identify or select an access point 102 to be associated with (e.g., based on scan information acquired through passive or active scanning), and perform verification and association operations to establish individual communication connections 108a to 108d with the selected access points 102. In the final step of the association operation, access point 102 assigns an AID to each of sites 104a to 104d, making access point 102 usable for tracking sites 104a to 104d.

[0053] In some cases, one or more of sites 104a to 104d may have the opportunity to select one from multiple BSSs within the site's range, or from multiple access points 102 of an Extended Service Set (ESS) consisting of multiple connected BSSs. The extended network sites associated with WLAN 100 may connect to wired or wireless distributed systems that allow multiple access points 102 to interconnect within the ESS. In some examples, one or more of sites 104a to 104d may be covered by more than one access point 102 and may be associated with different access points 102 at different times for transmission. After being associated with an access point 102, one or more of sites 104a to 104d may also be configured to periodically scan the surrounding signals to search for more suitable access points to associate with. For example, if a particular access point 104a to 104d is moving away from its original associated access point 102, it can perform a "roaming" scan to search for another access point with more suitable network characteristics (e.g., a better Received Signal Strength Indicator (RSSI), reduced traffic, etc.).

[0054] In some cases, stations 104a to 104d may form their own network without access point 102 or other devices not belonging to stations 104a to 104d. Examples of such networks are ad hoc networks. Some examples of ad hoc networks are mesh networks and peer-to-peer (P2P) networks. In some cases, ad hoc networks can be implemented within larger wireless networks. In such implementations, stations 104a to 104d can communicate with each other via access point 102 using their respective wireless connections 108a to 108d, and stations 104a to 104d can also communicate with each other using direct wireless connection 110. In some examples, two stations can communicate via direct wireless connection 110 regardless of whether they are associated with and served by the same access point 120. In the aforementioned arbitrary system, one or more of stations 104a to 104d can assume the role performed by access point 102 in the BSS. Such a station can be called a Group Owner (GO) and can coordinate transmissions within the arbitrary network. Examples of direct wireless connections 110 may include one or more Wi-Fi direct connections, connections established using Wi-Fi Tunneled Direct Link Setup (TDLS), other P2P group connections, etc.

[0055] Access points 102 and stations 104a to 104d can perform functions and communications using their respective communication connections 108a to 108d according to at least one of the IEEE 802.11 wireless communication protocol standards. These standards define WLAN radio and baseband protocols for the physical (PHY) and medium access control (MAC) layers. For example, access points 102 and stations 104a to 104d can wirelessly transmit and receive Physical Layer Protocol Data Units (PPDUs) or Physical Layer Convergence Protocol (PLCP) PDUs from each other. Access points 102 and sites 104a to 104d in WLAN 100 can transmit PPDUs on licensed or unlicensed spectrum, which may be a portion of that spectrum, including bands traditionally used by Wi-Fi technologies, such as the 2.4 GHz band, 5 GHz band, 60 GHz band, 3.6 GHz band, and sub-1 GHz bands. In some embodiments of access points 102 and sites 104a to 104d described herein, other bands may be used for communication, such as the 6 GHz band, which supports both licensed and unlicensed communication. Access points 102 and sites 104a to 104d can also be configured to communicate on other bands, such as sharing licensed bands, allowing multiple operators to have licenses to operate in one or more of the same or overlapping bands.

[0056] Each frequency band can contain multiple sub-bands (frequency channels). For example, PPDUs conforming to the IEEE 802.11 standard and specification can be transmitted over a frequency band divided into multiple 20MHz channels. In these examples, PPDUs are transmitted through a physical channel with a minimum bandwidth of 20MHz, but other channel bandwidths are also possible. In some cases, channel combining can be used to form a larger bandwidth channel, which combines multiple channels with a minimum bandwidth.

[0057] Each PPDU is a composite structure containing a PHY preamble and a payload in the form of a PHY Service Data Unit (PSDU). The information provided in the preamble can be used by the receiving device to decode the data in the PSDU. In the example where PPDUs are transmitted over a combined channel, the preamble field can be copied multiple times and transmitted in each of the multiple component channels. The PHY preamble may include a traditional part (or "traditional preamble") and a non-traditional part (or "non-traditional preamble"). The traditional preamble can be used for packet detection, automatic gain control, channel estimation, and other purposes. The traditional preamble is also typically used to maintain compatibility with traditional devices. The format, encoding, and information provided in the non-traditional part of the preamble are based on the specific IEEE 802.11 protocol used to transmit the payload.

[0058] Figure 2A is a high-order block diagram of an example wireless communication device 200 that can be used to implement a site or access point in some examples. The wireless communication device 200 includes a MAC layer and a PHY layer, and conforms to one or more IEEE 802.11 standards.

[0059] The wireless communication device 200 includes a radio frequency (RF) transmitter module 202, an RF receiver module 204, an antenna unit 206, one or more memory banks 208, an input and output interface 210, and a system bus 212. The RF transmitter module 202 and the RF receiver module 204 include a modulator-demodulator device (modem), which modulates one or more carrier signals to encode digital information for data transmission, and demodulates the signals to reconstruct the original digital information for data reception. As shown, the wireless communication device 200 also includes a MAC processor 214, a PHY processor 216, and a host processor 218. These processors can be any type of integrated circuit (IC), application specific integrated circuit (ASIC), or IC based on a reduced instruction set computer (RISC-V), etc., containing general-purpose processing units.

[0060] Memory 208 stores software and / or computer-readable instructions, including software or computer-readable instructions for implementing at least some functions of the MAC layer. For example, each processor included in the wireless communication device 200 (such as MAC processor 214, PHY processor 216, HOST processor 218, etc.) executes its own software to implement the corresponding communication / application layer functions.

[0061] The PHY processor 216 includes a transmit signal processing unit and a receive signal processing unit (not shown) for managing the interface in conjunction with Wireless Medium-WM. The PHY processor 216 operates PPDUs by exchanging digital samples with a radio module, which includes an RF transmitter 202, an RF receiver 204, an analog-to-digital converter, and a digital filter.

[0062] The MAC processor 214 executes MAC-level instructions and manages the interface between the application software and the WM through the PHY processor 216. The MAC processor 214 is responsible for coordinating access to the WM, enabling efficient communication between the access point and the STAs within its range. The MAC processor 214 adds header bytes and tail bytes to multiple data units and sends them to the PHY layer for transmission; these data units are provided by higher layers. When receiving data from the PHY layer, the reverse processing is performed. If the received frame contains errors, the MAC processor 214 manages the retransmission of this frame.

[0063] The HOST processor 218 interfaces with the MAC layer and is responsible for running the higher-level functions of the wireless communication device.

[0064] The PHY processor 216, MAC processor 214, HOST processor 218, peripheral bus 220, memory 208, and input / output interface 210 communicate with each other via system bus 212. Peripheral bus 220 connects several peripheral devices to support the core functions of the wireless communication device 200, including timers, interrupts, radio / filter / system registers, counters, Universal Asynchronous Receiver Transmitter (UART), and General Purpose Input / Output (GPIO) interfaces. Memory 208 may store the operating system and applications. In some examples, memory 208 stores record information about acquired frames and packets. Input / output interface unit 210 allows information exchange with the user of the wireless communication device 200. Antenna unit 206 may include a single antenna and / or may contain multiple antennas. For example, multiple antennas can be used to implement Multiple Input Multiple Output (MIMO) technology.

[0065] Figure 2B illustrates a schematic block diagram of a receiver data stream architecture 250 that can be used to receive Wi-Fi packets over a network. In an illustrative embodiment, the receiver data stream architecture 250 of Figure 2B corresponds to or is otherwise associated with the wireless communication device 200 of Figure 2A. A receiving antenna 252 receives radio signals via WM and converts them into electrical signals; the receiving antenna 252 may be the same as or similar to the antenna 206 of Figure 2A. Before the received signal is converted to a digital equivalent using an analog-to-digital converter 256, the received signal is conditioned by a series of analog filters 254 (analog RF Rx filters as shown). The sampled signal output of the analog-to-digital converter (ADC) 256 is further conditioned by a filter bank 258 before samples are collected into the asynchronous receiving FIFO data structure 260.

[0066] The samples in the first-in-first-out buffer data structure 260 can be accessed by multiple modules. For example, the samples can be accessed by a packet detection module and a sub-band module, which can be contained within the lower-level PHY portion 262 shown in FIG2B. In some embodiments, the lower-level PHY portion 262 itself is contained within the PHY processor 216 shown in FIG2A.

[0067] The packet detection module in the lower-layer PHY locale 262 may include hardware and / or implement algorithms for analyzing the initial segment of the PPDU in the time domain. Based on the analysis, the packet detection module can be used to identify received frames and synchronize the frequency and timing of the wireless communication device with the received packets. The sub-band module in the lower-layer PHY locale 262 may include hardware and / or implement algorithms for detecting which sub-channel in the currently used configuration frequency band is used to receive packets.

[0068] Once a packet is detected and the associated secondary channel is established, the sample can be forwarded to the upper-layer PHY locale 264. The upper-layer PHY locale 264 can be included within the PHY processor 216 shown in FIG. 2A. In some respects, the upper-layer PHY locale 264 (e.g., with the support of a coprocessor module) can be used to process and decode Orthogonal Frequency Division Multiplexing (OFDM) symbols to reconstruct the complete PPDU. The reconstructed PPDU is output by the upper-layer PHY locale 264 and then processed by the MAC layer processor 266. The MAC layer processor 266 can be used to extract the data payload from the PPDU and provide relevant information to the HOST layer 268 for use.

[0069] In some embodiments, the MAC layer processor 266 shown in FIG2B may be the same as or similar to the MAC processor 214 shown in FIG2A. In some cases, the HOST layer 268 shown in FIG2B may include, or be the same as or similar to the HOST processor 218 shown in FIG2A.

[0070] Figure 2C is a schematic block diagram of a transmitter data stream architecture 280 according to some examples, which can be used to transmit radio frequency signals to a wireless medium. In particular, Figure 2C is a simplified schematic block diagram of a transmitter data stream architecture 280 for transmitting radio signals to a wireless network (WM). Data can be generated from a host or application (APP) module 282 and encapsulated by a MAC management module 284 into a MAC level Protocol Data Unit (MPDU), allowing the MPDU to be routed through the wireless network. A PHY module 286 interfaces with the WM and compiles a PHY preamble and trailer into the MPDU to produce a PHY PPDU. Typically, the MAC module 284 or the PHY module 286 uses a rate control algorithm to establish a modulation coding scheme (MCS) for transmitting packets over the medium. The selected scheme defines the modulation technique and coding rate used for the data to be transmitted to the WM. Based on the selected modulation scheme, such as Quadrature Amplitude Modulation (QAM) 64, the PPDU to be transmitted to the WM is modulated. Encoder module 288 generates a signal corresponding to the points (groups of bits in the PPDU) of the QAM constellation symbol, which can be encoded using polar (r-θ) coordinates and Cartesian (QI) coordinates. Modulation is accomplished by connecting encoder module 288 to a Digital Phase Lock Loop (DPLL) 290. The modulated signal can be filtered by analog filter 292 and transmitted using transmit antenna 294.

[0071] Many modern radio systems use orthogonal frequency division multiplexing (OFDM) schemes with relatively large peak-to-average power ratios (PAPR). For example, a larger (e.g., higher) PAPR value corresponds to a larger difference between the peak RF output power and the average RF output power of the radio system. As previously noted, radio systems typically contain one or more power amplifiers (PAs), which achieve maximum power efficiency when operating at their maximum output power, and whose power efficiency decreases significantly as the output power drops from its maximum value. The higher the PAPR value, the greater the difference between the peak and average power levels, and it is generally undesirable to configure the radio system to allow peak RF output power levels to exceed the maximum output power of the PA (e.g., to avoid distortion). Therefore, the peak power level is typically limited to the maximum output capability of the PA, while the average power level drops below the maximum output of the PA. Accordingly, a high PAPR signal may correspond to the PA operating below its peak output level, where power efficiency is poor.

[0072] Therefore, there is a need for a system and technology that can improve the power efficiency of a PA even when it encounters relatively high or significant power back-off. For example, most Wi-Fi systems (e.g., examples of radio systems using one or more PAs) operate at a PAPR between 8 dB and 12 dB. The average power level of a Wi-Fi system with a PAPR between 8 and 12 dB is approximately 10% of its peak power level; therefore, the power amplifier in a Wi-Fi system operates at suboptimal power efficiency most of the time. The technology proposed in this invention is based on combining the outputs of two independent power amplifiers to maximize the PA's efficiency even with a 6 dB back-off, such that one of the two PAs operates within the required output power range, while the other PA is generally off, acting as a boost amplifier at high power output levels. This combination allows the two PAs to operate for a longer period of time, close to their maximum efficiency, over a wider power range. There is still a need for a system and technology that can be used to apply the above technologies to modern integrated PAs and / or DPAs.

[0073] For example, combining the outputs of two independent PAs (one PA operating within the configured power range, and the other capable of functioning as a boost amplifier at higher power outputs) has always been a challenge for modern integrated PAs. This is at least in part due to the large size of the previously required combiner components and the difficulty in designing a combiner that can consistently match the output impedance of each of the two PAs. For example, the output impedance of each PA typically varies considerably with the total output power.

[0074] In some embodiments, the systems and techniques described above can improve the efficiency of PAs by combining the outputs from two or more independent PAs. In an illustrative example, a switched capacitor power amplifier (ScPa) is used to address challenges and problems that may arise when using a digital-to-analog converter (DAC) because the ScPa is a fully digital power amplifier. Some aspects of this specification include implementations that combine ScPas with integrated complementary metal-oxide-semiconductor (CMOS) systems.

[0075] The systems and techniques described above provide digitally controlled ScPa systems for power amplification with improved power efficiency. For example, a digitally controlled ScPa system can combine two independent ScPas, at least in part, based on the observed output impedance of the ScPa being constant across all gain settings. Advantageously, embodiments of the specification can be implemented by configuring / or reconfiguring existing components in the ScPa to obtain a combiner for combining the outputs of two independent PAs. Thus, the digitally controlled ScPa system for achieving improved efficiency described in the specification does not require additional large and / or complex physical circuitry, etc. In some embodiments, some aspects described in the specification include the ability to configure amplifier control during operation in a Cartesian system to combine in-phase (I) and quadrature (Q) signals without experiencing the efficiency degradation typically associated with integrated mixers. Furthermore, this system and technique can be used to modify combiner arrangements to maximize power efficiency at multiple backoff levels, including maximizing efficiency at 12 dB backoff and at 6 dB backoff.

[0076] In some embodiments, the digitally controlled switching capacitor power amplifier comprises two arrays of CMOS inverters, each inverter driving its own unit capacitor, and each complete capacitor array connected to the primary input of an indictive balun / transformer. For example, a balun / transformer may refer to a transformer or electrical component configured to provide an interface between balanced and unbalanced lines (e.g., balanced to unbalanced, or "balun").

[0077] Figure 3 illustrates a digitally controlled switched capacitor power amplifier (ScPa) architecture 300 configured with two arrays equipped with CMOS inverters. Each array contains multiple capacitors, which may or may not be driven by the corresponding inverters in the array. For example, the ScPa architecture 300 includes a first array 310 of CMOS inverters (also referred to as the first part of the ScPa) and a second array 330 of CMOS inverters (also referred to as the second part of the ScPa). One inverter array is driven by a square wave, and the other inverter array is driven by an anti-phase square wave, where both the square wave and the anti-phase square wave are at the desired RF output frequency of the ScPa architecture 300. For example, the first array 310 of inverters can be driven by a square wave 315, and the second array 330 of inverters can be driven by an anti-phase square wave 335. Each of the square wave 315 and the anti-phase square wave 335 can be associated with the desired (as configured) RF output frequency of the ScPa architecture 300.

[0078] Each of the first array 310 and the second array 330 includes a plurality of inverters (such as CMOS inverters). In each array, some inverters are driven while others remain static. For example, a first subset of the plurality of CMOS inverters in the first array 310 may be driven, while a second subset of the plurality of CMOS inverters in the first array 310 remains static. Similarly, a first subset of the plurality of CMOS inverters in the second array 330 may be driven, while a second subset of the plurality of CMOS inverters in the second array 330 remains static. The ratio of driven or static inverters in a given array of the ScPa architecture 300 (such as in the first array 310 or the second array 330) can be configured according to a digital amplitude control signal, for example, by providing an amplitude code input to the first array 310 and the second array 330. By varying the number of inverters in a given array that are active or static, the array forms a capacitive divider, where the output voltage amplitude is proportional to the number of active inverters. The complete differential inverter-capacitor-inductor circuitry forms a series resonant circuit tuned to the operating frequency required by the ScPa architecture 300, resulting in high current at the desired operating frequency and attenuation of the RF harmonics created by the square wave drive signals 315, 335. As previously described, the first array 310 and the second array 330 can be connected to the main input of the balun (as associated with the main coil), as shown in the example of Figure 3, which includes the balun main coil 342 and the balun secondary coil 346. The high current in the balun main coil 342 is coupled to the balun secondary coil 346, where the current is transformed across the impedance and converted into a single-ended signal that can directly drive the transmitting antenna.

[0079] As previously stated, the inverters in each array of the ScPa can be driven or kept static. The static inverter has the exact same output impedance as the clock inverter, so the impedance and frequency of the resonant circuit (e.g., the resonant circuit formed by the fully differential inverter-inductor-inductor circuit of the ScPa architecture 300) are not affected by the digital code or amplitude control signal used to configure the proportion of drive inverters in the array.

[0080] Static units (e.g., a subset of inverters held static in an array) attenuate the signal by creating capacitive loads on active units (e.g., a subset of driven inverters in an array). Therefore, the power lost in any inactive unit (e.g., each inverter held static) can be determined according to P=fCV, where P represents the dissipated power, f is the inverter's RF output frequency or switching frequency, C is the capacitance, and V is the voltage. Inactive inverter units still absorb power through their capacitive loads, so it can be found that the efficiency of ScPa decreases with the number of inactive units in each array. For example, the larger the proportion of inactive inverter units in the ScPa, the more power dissipated by the inactive inverter units, resulting in a lower overall ScPa power efficiency. Based on the dissipated power of each inactive inverter unit according to P=fCV, it can be seen that the ScPa efficiency is maximized when all inverter units are active (e.g., eliminating the power dissipation / loss associated with held static or inactive inverters).

[0081] Existing ScPa designs utilize differential signals of varying amplitudes from two arrays (e.g., first array 310 and second array 330) of the inverter and capacitors to drive the main coil (e.g., main coil 342) of the balun. The orientation and embodiments of this specification can be used to implement and / or provide baluns / transformers with improved common-mode rejection, thereby eliminating the need for conventional differential drive methods to drive the ScPa. For example, in a balun / transformer with improved common-mode rejection, differential drive of the main coil 342 of the balun is not required; instead, two independent drive signals are applied to both ends of the main coil 342 of the balun, while maintaining the same or similar performance.

[0082] In some aspects, the two inverters and capacitor arrays in the ScPa can be used as independent amplifiers to achieve an improved efficiency scheme, wherein the first PA output can operate within the required power range, while the second PA output can operate as a boost amplifier at a higher power output level. For example, the first inverter and capacitor array 310 can be used as a first independent amplifier to apply a first independent drive signal to a first terminal of the balun main coil 342; the second inverter and capacitor array 330 can be used as a second independent amplifier to apply a second independent drive signal to a second terminal of the balun main coil 342. In some embodiments, the balun main coil 342 can be used to provide the combination of the two inverters and capacitor arrays 310 and 330 required for high efficiency (e.g., the balun main coil 342 can be used as a combiner element in an ScPa configuration that improves efficiency by combining the outputs of two independent PAs operating at different power ranges). The merging function provided by the balun main coil 342 is constant and independent of amplitude code, and the different amplitude outputs from the two inverters and capacitor arrays 310 and 330 are added with good linearity.

[0083] For example, Figure 4 is an example schematic diagram illustrating a merged drive scheme 400 of an ScPa architecture implemented using a non-Cartesian system. The ScPa architecture shown in Figure 4 may be the same as or similar to the example ScPa architecture 300 of Figure 3. In the example non-Cartesian scheme shown in Figure 4, the amplitude code is split into two halves or two parts, with the lower half 402 of the amplitude code representing the range from 0 to n / 2-1, and the upper half 404 representing the range from n / 2 to n.

[0084] In some embodiments, the scheme shown in FIG4 is implemented such that the lower half 402 of the amplitude code is input to the first inverter and capacitor array 410, while the second inverter and capacitor array 430 remain static. The first inverter and capacitor array 410 of FIG4 may be the same as or similar to the first array 310 of FIG3. Similarly, the second inverter and capacitor array 430 of FIG4 may be the same as or similar to the second array 330 of FIG3. The lower half 402 of the amplitude code (from 0 to n / 2-1) is input only to the first array 410, while the second array 430 remains static until the first array 410 is fully driven and thus operates at maximum efficiency. For example, the first array 410 becomes fully driven and operates at the maximum configured output power level, corresponding to the first array 410 operating at its maximum power efficiency. Once the first array 410 is fully driven and operating at maximum power efficiency, the upper half 404 of the amplitude code begins to be input to the second inverter and capacitor array 430, while keeping the first inverter and capacitor array 410 fully driven. In some examples, the drive scheme 400 of the non-Cartesian system shown in Figure 4 may also be referred to as a "combination scheme," for example, based on the combination of using the main coil of a balun to unbalance converter to provide the outputs of the first array 410 and the second array 430.

[0085] As previously described, the combined drive scheme 400 of Figure 4 corresponds to an example of ScPa implemented in a non-Cartesian system. Figure 5 illustrates an example of a combined drive scheme 500 of an ScPa architecture implemented in a Cartesian system, the ScPa architecture comprising a first inverter and capacitor array 510 and a second inverter and capacitor array 530. For example, non-Cartesian systems (such as polar coordinate systems) can use amplitude and phase information to represent RF input signals, while Cartesian systems can use Cartesian coordinates to represent signals, such as using in-phase (I) signal components and quadrature-phase (Q) signal components. In some examples, a Cartesian system can use separate amplification paths for the I and Q signal components, and then re-combine the I and Q signals from their respective separate amplification paths.

[0086] In an example of the combined drive scheme 500 of the Cartesian system, the first inverter and capacitor array 510 of FIG5 may be identical or similar to one or more of the first array 310 of FIG3 and / or the first inverter and capacitor array 410 of FIG4. The second inverter and capacitor array 530 of FIG5 may be identical or similar to one or more of the second array 330 of FIG3 and / or the second inverter and capacitor array 430 of FIG4. The Cartesian system uses two clocks with a 90-degree phase difference, which may also be referred to as I and Q clocks. The I and Q components are coupled through different capacitors of the array according to an encoding circuit that maps the amplitudes of the I and Q components to various different capacitor arrays. Specifically, the amplitudes of the I and Q components are encoded as amplitude codes that are configured to control which capacitors in each array (e.g., the first and second arrays 510 and 530) are driven, rather than remaining static.

[0087] In these embodiments, the systems and techniques described herein can achieve power amplification efficiency improvements (such as boosts, increases, etc.) for Cartesian systems similar to those achieved for non-Cartesian systems as described above. For example, dividing the I-amplitude code and Q-amplitude code into corresponding upper and lower halves, and distributing the upper and lower halves of the I and Q-amplitude codes between the first inverter and capacitor array 510 and the second inverter and capacitor array 530, respectively, can provide the same or similar power efficiency improvements.

[0088] In an illustrative example, a first inverter and capacitor array 510 can be used for input 502, which includes the lower half of an I-amplitude code (e.g., the lower half of an I-amplitude code from 0 to n / 2-1) and the upper half of a Q-amplitude code (e.g., the upper half of a Q-amplitude code from n to n / 2). A second inverter and capacitor array 530 can be used for input 504, which includes the upper half of an I-amplitude code (e.g., the upper half of an I-amplitude code from n / 2 to n) and the lower half of a Q-amplitude code (e.g., the lower half of a Q-amplitude code from n / 2-1 to 0). In this example, the two arrays 510 and 530 are respectively used to process the lower half of a code (e.g., the lower half of an I-code or the lower half of a Q-code) and the upper half of other codes (e.g., the upper half of a Q-code or the upper half of an I-code). Each code is split into two arrays, 510 and 530, and neither array processes only the lower half or the upper half.

[0089] In some embodiments, assigning digital IQ amplitude codes to different branches of the inverter and capacitor array of the amplifier (e.g., assigning corresponding I and Q amplitude codes between the first inverter and capacitor array 510 and the second inverter and capacitor array 530) can be configured to allow the switched capacitor power amplifier to operate at maximum power for the corresponding branch (e.g., the first branch includes / corresponds to the first array 510, the second branch includes / corresponds to the second array 530, etc.) for as long as possible.

[0090] In some embodiments, further enhancements can be achieved by further splitting or dividing the inverter and capacitor array 510 with the first and second branches of the inverter and capacitor array 530. For example, the split in the example of FIG5 corresponds to a split between the first branch of the inverter and capacitor array 510 and the second branch of the inverter and capacitor array 530. In some embodiments, one or more divisions can be applied to split the inverter and capacitor array (such as 510 or 530) in the same branch into two halves, four parts, etc. More divisions allow the ScPa system to operate or drive with more than two independent inverter and capacitor arrays, and these branches can be combined in different combinations.

[0091] In an illustrative example, both branches shown in Figure 5 (e.g., 510 and 530) can be split or divided in half to obtain a total of four independent branches of inverter and capacitor arrays that can be combined. For example, Figure 6 illustrates an example of a combined drive scheme 600 of the ScPa architecture implemented using a Cartesian system and four inverter and capacitor array branches. The I and Q amplitude codes can be split into four parts and distributed in the first branch 610-1 of the inverter and capacitor array, the second branch 610-2 of the inverter and capacitor array, the third branch 630-1 of the inverter and capacitor array, and the fourth branch 630-2 of the inverter and capacitor array.

[0092] For example, the first branch 610-1 of the inverter and capacitor array can be used for I-code from 0 to n / 4-1 and Q-code from n to 3n / 4. The second branch 610-2 of the inverter and capacitor array can be used for I-code from n / 2 to 3n / 4-1 and Q-code from n / 2-1 to n / 4. The third branch 630-1 of the inverter and capacitor array can be used for I-code from 3n / 4 to n and Q-code from n / 4-1 to 0. The fourth branch 630-2 of the inverter and capacitor array can be used for I-code from n / 4 to n / 2-1 and Q-code from 3n / 4-1 to n / 2.

[0093] The balun primary of the balun can be implemented as a series resonant balun primary formed by two closely coupled inductors 642-1 and 642-2. The balun secondary 646 can be the same as or similar to the balun secondary 346 of FIG. 3, etc. Inductor 642-1 can be connected to the output of the second branch of the inverter and capacitor array 610-2 and the third branch of the inverter and capacitor array 630-1. Inductor 642-2 can be connected to the output of the first branch of the inverter and capacitor array 610-1 and the fourth branch of the inverter and capacitor array 630-2. Although the topology of the balun becomes more complex, the overall size of the balun shown in FIG. 6 does not increase significantly.

[0094] Embodiments of the present invention make the Cartesian application of the system more feasible. The concept of the present invention can be extended to multiple branches using multiple coupled transformers (e.g., unbalanced converters) as the main body. If the multiple inputs of the transformers are not perfectly balanced, the above combination will only result in each combined amplifier exhibiting a small difference in linear gain, which is more easily remedied by the complex predistortion techniques required by other integrated amplifier architectures.

[0095] As previously described, the systems and techniques described herein can be used to improve the efficiency of switched capacitor power amplifiers and / or various other digital power amplifiers. Digital power amplifiers not only improve the energy efficiency of RF transceivers but also reduce the required chip area. In the implementation of a ScPa digital power amplifier using a Cartesian system, the I and Q components of the signal are coupled through different capacitor arrays of the ScPa, and encoding circuitry is used to map the individual amplitudes of the I and Q components to different combinations of capacitor arrays. The amplitudes of the I and Q components are encoded as amplitude codes to control or configure which capacitors in each capacitor array are turned on (e.g., not kept static). Various aspects of this specification can be used to address the limitations of prior art digital power amplification, including the performance degradation (e.g., deterioration, degradation, etc.) of conventional digital power amplifiers when the absolute values ​​of the I and Q samples are too large.

[0096] Specifically, when the sum of the absolute values ​​(e.g., amplitudes) of the I and Q components exceeds a certain threshold, the performance of the digital power amplifier degrades to an acceptable level. This threshold for performance degradation can be based on and / or corresponding to the number of bits used to represent the I and Q samples. For example, in a 16-bit DAC used in an RF transceiver, 1 bit represents the sign and 15 bits represent the amplitude; therefore, each I and Q sample is represented by a 15-bit amplitude code. The threshold preventing performance degradation of the digital power amplifier can be determined as the square of the bit length of the I and Q samples. For the example of a 16-bit DAC, where both I and Q samples are 15-bit amplitude codes, the threshold for performance degradation is 2^15 = 32768.

[0097] In other words, when |I| + |Q| > 32768, the digital power amplifier performance degrades, where I represents the sample on the in-phase path and Q represents the sample on the quadrature-phase path. The threshold for digital power amplifier performance degradation can be based on the bit width of the DAC or the number of bits used to represent the amplitude of the I / Q samples, as in the previously described example. In some cases, when the sum of the absolute values ​​of I and Q exceeds the threshold, the digital power amplifier exhibits poor mirroring behavior, which may lead to a degradation in digital power amplifier performance. For example, the ScPa on the I / O samples has a sum of the absolute values ​​of I and Q exceeding the threshold, resulting in mirror distortion. In some examples, these amplitudes and IQ samples exceeding the threshold can be represented by a clipping rhombus superimposed on the IQ constellation diagram. The IQ samples within the clipping rhombus (e.g., enclosed) are IQ samples whose sum of amplitude is less than the digital power amplifier performance degradation threshold. IQ samples outside the cropped rhombus are IQ samples whose total amplitude exceeds the digital power amplifier performance degradation threshold. IQ samples on the cropped rhombus are IQ samples whose total amplitude equals the digital power amplifier performance degradation threshold.

[0098] In an illustrative example, several aspects of embodiments of the present invention can be used to correct mirror image distortion caused by analog circuitry in a digital power amplifier. In a conventional quadrature ScPa system, two sub-ScPas are provided, one dedicated to I signals and the other to Q signals. For each sub-ScPa, the number of switching capacitors between VDD (e.g., positive supply voltage / high voltage rail) and Vground (e.g., low voltage rail / reference ground) is between 0 and 1 / 2 of the total number of capacitors N. Since each sub-ScPa uses at most a portion of the entire array, the total number of capacitors in the dedicated capacitor arrays for I and Q signals exhibits reduced efficiency, and the dedicated IQ array architecture has 3 to 6 dB lower output power and lower drain efficiency compared to an equivalent polarity ScPa. The quadrature IQ shared unit ScPa uses merged unit vectors and flexible vector allocation to increase output power.

[0099] Figure 7 is an IQ constellation diagram 700, showing a clipped diamond 750 corresponding to a performance degradation threshold of the digital power amplifier. For example, the clipped diamond 750 can correspond to a digital power amplifier performance degradation threshold discussed above, 2 num_bits, where the value of num_bits is equal to the bit width of the DAC or the number of bits used to represent the amplitude of the I / Q samples. In some aspects, the clipped diamond 750 contains a set of IQ samples with a configuration threshold of |I|+|Q| (e.g., a set of IQ samples with |I|+|Q| of 2 num_bits). The region in the IQ constellation diagram 700 outside the clipped diamond 750 may be referred to as the clipped region, containing a set of IQ samples with |I|+|Q| greater than the configuration threshold (e.g., a set of IQ samples with |I|+|Q| greater than 2 num_bits).

[0100] In the example of Figure 7, the clipping is performed from the demand point 730 of the I / O samples in the corresponding clipping region (e.g., outside the clipping rhombus 750) to the clipping point 735 on the clipping rhombus 750. Clipping from the demand point 730 to the clipping point 735 can be used to reduce or prevent performance degradation associated with exceeding the configuration threshold of the clipping rhombus 750, and can be used to prevent or mitigate the aforementioned undesirable mirroring behavior, etc. In one illustrative example, according to various embodiments of the invention, the clipping from the demand point 730 to the clipping point 735 can be performed according to an analog clipping scheme of the DPA and / or ScPa system configuration. For example, in some embodiments, the clipping scheme can be performed to clip from various demand points of I / O samples contained within the clipping region (e.g., outside the clipping rhombus 750) to corresponding clipping points located on or within the clipping rhombus 750. In some respects, the corresponding cut point includes the orthogonal projection of any required point within the cut area onto the cut profile given by the cut rhombus 750.

[0101] In some embodiments, the analog clipping scheme can be implemented based on setting two control bits configured to control each output unit of the capacitor array in the IQ shared unit ScPa system, such that the control bits provide priority and / or processing logic for any "double-enabled" unit controlled by both I and Q signals.

[0102] In particular, the trimmed rhombus 750 may correspond to the boundary of the linear operating region of the amplifier, wherein the total number of active units required for the I and Q code combinations (e.g., IQ samples) does not exceed the total available capacity of the number of capacitor units N in the capacitor array of the IQ shared unit ScPa. For example, the number of capacitor units required for the I code is |I|, and the number of capacitor units required for the Q code is |Q|. Corresponding to the descent condition mentioned above, a performance degradation of the digital power amplifier is observed when |I|+|Q| is greater than the threshold. Therefore, it can be seen that the trimmed rhombus 750 represents the threshold given by the number of capacitor units in the shared unit ScPa array. The IQ samples in the trimmed rhombus 750 do not exceed the number of output units in the capacitor array and satisfy |I|+|Q|≤N. The IQ samples outside the trimmed rhombus 750 are combinations of I and Q amplitudes, which require more units than the total number of capacitor units in the capacitor array, i.e., |I|+|Q|>N.

[0103] In the IQ shared unit ScPa, each of the multiple output unit units (N) in the capacitor array can be driven by either the I or Q clock. The output unit units of the capacitor array may be referred to herein as "output units," "capacitor units," and / or "capacitor cells." As previously mentioned, the number of output units driven by the I and Q clocks is limited, depending on the number of output units N in the capacitor array. This limitation occurs when the sum of the number of output units driven or required by the I clock (e.g., |I|) and the number of output units driven or required by the Q clock (e.g., |Q|) exceeds the number of output units N in the shared capacitor array (e.g., |I|+|Q|>N).

[0104] In some embodiments of the IQ shared unit ScPa, each corresponding output unit of the plurality of output unit units (N) in the shared capacitor array can be implemented as two control bits to define the operating state of the corresponding output unit. For example, a first control bit can be used to enable the operation of the I clock and / or the priority of the I clock, and a second control bit can be used to enable the operation of the Q clock and / or the priority of the Q clock. The first control bit may be referred to herein as an "I control unit" or "I clock control bit". The second control bit may be referred to herein as a "Q control unit" or "Q clock control bit". Each control bit can take a low value (e.g., "0") or a high value (e.g., "1").

[0105] For example, when two control bits of a specific output unit in the capacitor array are set to low values ​​(e.g., I control bit is 0, Q control bit is 0), the output unit operation state is set to "off". When one control bit is set to high value and the other control bit is set to low value, the output unit operation state is driven by the control bit with a high value in the I or Q clock. For example, if the I control bit is 1 and the Q control bit is 0, the output unit operation state is driven by the I clock. Similarly, if the I control bit is 0 and the Q control bit is 1, the output unit operation state is driven by the Q clock.

[0106] When ScPa enters the trimmed region (e.g., beyond the trimmed diamond 750 in Figure 7), the number of output units required by I and Q is greater than the number of output units in the capacitor array, |I|+|Q|>N. Within the trimmed region, a portion of the output units in the capacitor array become "dual-enabled" and the I control bit and Q control bit are set to high values. For example, when the I control bit is 1 and the Q control bit is 1, the output units of the capacitor array are dual-enabled. In the IQ shared unit ScPa, the shared unit design in the capacitor array allows sharing of the same capacitor array between I and Q clocks, but individual units / output units in the capacitor array are only driven by the I clock or the Q clock (e.g., individual units / output units cannot share themselves and cannot be driven by I and Q simultaneously). Therefore, the dual-enabled control bit condition with I control bit and Q control bit can cause conflicts on the dual-enabled output units of the capacitor array. A dual-enabled output unit in a shared capacitor array is a subset of units with two control bits set to high values; that is, an output unit that receives both I and Q clocks due to the ScPa entering the cut-off region. In some ScPa designs, dual-enabled output units are simply disabled, kept static, or have their operating state set to "off" because the dual-enabled control bit conditions are incompatible with specific output units in the capacitor array that can only be driven by either the I or Q clock.

[0107] In some respects, when ScPa enters the clipping region, the number of dual-enabled cells is equal to |I|+|Q|-N, or the I and Q in the shared capacitor array exceed the total number of cells required for N. In the example shown in Figure 7, “I code” 760 and “Q code” 770 correspond to the demand point 730 located within the clipping region, which is outside the clipping rhombus 750. The total number of output cells in the capacitor array is N, where the clipping rhombus 750 intersects the I-axis at (i=N, Q=0) and the clipping rhombus 750 intersects the Q-axis at (i=0, Q=N).

[0108] As shown in the figure, the I code 760 is divided into a first I code portion 762, a second I code portion 764, and a third I code portion 766. Similarly, as shown in the figure, the Q code 770 is divided into a first Q code portion 772, a second Q code portion 774, and a third Q code portion 776.

[0109] The second and third I-code portions 764 and 766 and the second and third Q-code portions 774 and 776 are dual-enabled. The number of dual-enabled units is the same as that of I-code 760 and Q-code 770, that is, the number of output units of I-code portions 764 and 766 is equal to the number of output units of Q-code portions 774 and 776. The number of dual-enabled output units corresponding to demand point 730 is equal to |I| + |Q| - N.

[0110] The first I code portion 762 corresponds to a set of output units that are driven by I but not double-enabled (e.g., having I control bits of 1 and Q control bits of 0). The first Q code portion 772 corresponds to a set of output units that are driven by Q but not double-enabled (e.g., having I control bits of 0 and Q control bits of 1).

[0111] Embodiments of the present invention can be used to provide an analog clipping scheme that controls the behavior of the operating states of one or more dual-enabled output units, all of which have multiple control bits set to high values ​​(e.g., I control bit 1, Q control bit 1). The analog clipping scheme can be implemented locally on each corresponding output unit of the shared capacitor array to ensure that if the corresponding output unit becomes dual-enabled, the dual-enabled output unit can determine the appropriate priority for selecting the I or Q control bits. By providing local priority logic for each output unit of the capacitor array, the dual-enabled unit will still contribute to the combined output signal of the IQ shared unit ScPa (e.g., instead of setting its operating state to "off" in response to dual-enabled, as might happen in existing ScPa designs). The analog trimming scheme can be implemented as local analog logic, circuitry, etc. associated with each output unit of the capacitor array, thereby allowing demand points outside the trimming rhombus 750 (e.g., demand point 730) to be automatically trimmed to the vicinity of the trimming rhombus 750, without requiring or using a central trimming module to globally detect trimming conditions and reconfigure ScPa accordingly.

[0112] In some embodiments, analog clipping logic can be locally implemented for each output unit / cell of the shared capacitor array to define the operational state behavior of the output unit / cell when both control bits are set to high. The output unit with both control bits set to high is also referred to as a dual-enabled output unit. In some embodiments, the analog clipping scheme applied to the IQ shared unit ScPa results in the first half of the dual-enabled output unit applying priority logic for operation at the I clock, while the second half applies priority logic for operation at the Q clock. For example, the analog clipping scheme can be locally implemented by assigning or configuring a corresponding priority to each output unit in the plurality of output units N of the shared capacitor array. When (or if) a unit becomes dual-enabled, half of the output units can be configured to operate preferentially from the I clock, and when (or if) a unit becomes dual-enabled, the other half of the output units can be configured to operate preferentially from the Q clock.

[0113] In the example of Figure 7, the local priority logic of the analog trimming scheme allows any demand point 730 to be orthogonally projected from outside the trimming rhombus 750 to a certain position on the trimming rhombus 750. Based on the orthogonal projection of the local priority logic, half of the dual enable bits are preferentially considered to operate from the I clock, and half of the dual enable bits are preferentially considered to operate from the Q clock.

[0114] For example, the cut point 735 in FIG7 corresponds to a valid I code (e.g., a cut I code) corresponding to the first and second I code segments 762 and 764, wherein the third I code segment 766 is removed (e.g., cut). Similarly, the cut point 735 corresponds to a valid Q code (e.g., a cut Q code) corresponding to the first and second Q code segments 772 and 774, wherein the third Q code segment 776 is removed (e.g., cut).

[0115] I segment 764 represents half of the dual-enabled units that operate with priority on the I clock. I segment 766 is cut off and represents half of the dual-enabled units that have I control bits set to high, but are locally configured to prioritize Q control bits regardless of the I control bits.

[0116] Similarly, Q segment 774 represents half of the dual-enabled units that operate preferentially with the Q clock. Q segment 776 is clipped and represents half of the dual-enabled units that have Q control bits set to high, but are locally configured to prioritize I control bits regardless of the Q control bits.

[0117] In some embodiments, an analog shaving scheme is implemented based on different truth tables that can be applied and / or defined as the configuration of alternating output units within the capacitor array. When both I and Q clocks are enabled, half of the dual-enabled output units use the I clock, and simultaneously, when both I and Q clocks are enabled, half of the dual-enabled output units use the Q clock. In some embodiments, for dual-enabled output units, the priority of splitting between the I and Q clocks can be implemented based on ScPa, where ScPa uses different truth tables for even-indexed and odd-indexed output units (e.g., based on half of the ScPa capacitor array output units being even-indexed and half being odd-indexed): Table 1 Truth table of even-indexed output cells Truth table of odd-indexed output cells EN_I EN_Q state EN_I EN_Q state 0 0 open 0 0 close 1 0 I Clockwork 1 0 I Clockwork 0 1 Q clock 0 1 Q clock 1 1 I Clockwork 1 1 Q clock Table 1 illustrates the truth table configuration of the IQ shared unit ScPa. The truth table configuration is for both even-indexed and odd-indexed output units of the capacitor array. "EN_I" corresponds to the I control bit, and "EN_Q" corresponds to the Q control bit, with a value of "0" corresponding to a low value and a value of "1" corresponding to a high value. "Status" represents the operating state of the output unit.

[0118] In the example in Table 1, the even-indexed output units of the truth table configuration capacitor array of the even-indexed output units preferentially execute operations driven by the I clock, such that if they are in dual-enabled state, the even-indexed output units operate with the I clock. The odd-indexed output units of the truth table configuration capacitor array of the odd-indexed output units preferentially execute operations driven by the Q clock, such that if they are in dual-enabled state, the odd-indexed output units operate with the Q clock.

[0119] As shown in Figure 7, instead of using the original Q code 770 and I code 760 corresponding to demand point 730 to drive the output unit N of the capacitor array, the valid Q code and I code clipped to the boundary of the clipped rhombus 750 are used to drive the output unit. The valid Q code (e.g., containing Q code portions 772 and 774) is implemented by assigning multiple output units enabled according to the original Q code as dual-enabled output units, wherein both control bits (EN_I, EN_Q) of the dual-enabled output units are equal to 1. Similarly, the valid I code (e.g., containing I code portions 762 and 764) is implemented by assigning multiple output units enabled according to the original I code as dual-enabled output units, wherein both control bits (EN_I, EN_Q) of the dual-enabled output units are equal to 1. Based on the truth table in Table 1 as described above, the operating state of the output unit (1, 1) with even index double enable is I clock, while the operating state of the output unit (1, 1) with odd index double enable is Q clock.

[0120] For example, the I-code portion 764 corresponds to an even-indexed dual-enabled output unit configured by a truth table, to give priority to the I-code. The truncated I-code portion 766 corresponds to an odd-indexed dual-enabled output unit configured by a truth table, to give priority to the Q-code. Similarly, the Q-code portion 774 corresponds to an odd-indexed dual-enabled output unit configured by a truth table, to give priority to the Q-code (e.g., the dual-enabled output unit used in the valid Q-code and portion 744 may be the same as the truncated dual-enabled output unit when portion 766 is removed from the I-code 760). The Q-code portion 776 corresponds to an even-indexed dual-enabled output unit configured by a truth table, to give priority to the I-code (e.g., the dual-enabled output unit used in the valid I-code and portion 764 may be the same as the truncated dual-enabled output unit when portion 776 is removed from the Q-code 770).

[0121] In other embodiments, even-indexed dual-enabled output units are enabled by the Q clock, while odd-indexed dual-enabled output units are enabled by the I clock. Through this implementation, the number of I-clock-enabled output units is reduced by half the number of dual-enabled output units, and the number of Q-clock-enabled output units is also reduced by half the number of dual-enabled output units, thereby achieving the required trimming behavior from the demand point to the trimming point.

[0122] Figure 8 illustrates an example of capacitor array cell (e.g., output cell) allocation 800 when the IQ shared cell ScPa does not require pruning, and an example of capacitor array cell (e.g., output cell) allocation 850 when the IQ shared cell ScPa requires pruning, according to an embodiment of the present invention. In example allocation 800, pruning is not required when the total number of I and Q enabled output cells is less than the total number of output cells N (e.g., |I|+|Q|<N). In example allocation 800 without pruning, the subset of output cells having a "closed" operating state is N–|I|–|Q|.

[0123] In the example of clipping allocation 850, when the sum of the absolute values ​​of I and Q is greater than the number of output units N (e.g., |I|+|Q|>N), the number of output units is equal to the difference between |I|+|Q| and N, and these output units become dual-enabled output units. The output states of these dual-enabled output units are determined according to the local analog clipping logic described above, for example, locally implemented on each output unit of the capacitor array according to the example truth table in Table 1. In some aspects, the dual-enabled output units have operating states that are set to be interleaved with I clock and Q clock enabled, such that half of the dual-enabled output units have I clock enabled operating states, and the other half of the dual-enabled output units have Q clock enabled operating states.

[0124] In some paradigms, the ScPa output cells of a capacitor array are typically driven by a high-voltage rail (e.g., IO voltage) to maximize power output, while the clock tree and control code tree are run by a low-voltage rail (e.g., core voltage) to maximize speed and minimize gate area and operating current. Therefore, the clock signal driving each output cell is voltage level shifted to control the PMOS switching elements in the output cell. Conventional logic level voltage shifters are relatively large, slow, and extremely power-intensive at faster clock speeds, for example, converters that can be used and / or are suitable for ScPa output cells. Changing (e.g., varying) the voltage on the high-voltage rail provides a simple and effective way to change the peak power output of the ScPa, making systems and techniques for changing the high-voltage rail voltage beneficial. However, in some paradigms, previous (e.g., conventional, existing, etc.) logic level voltage shifters experienced a rapid performance degradation when the voltage on the high-voltage rail decreased.

[0125] In some examples, the ScPa output unit consists of a stack of four core elements (i.e., two switching elements and two cascode elements) because this configuration allows for small, low-resistance switching elements while still limiting the device's Vds and Vgs to safe levels. The Vds and Vgs of the core elements must be kept below the core voltage specified for processing.

[0126] Figure 9 illustrates a schematic diagram of an exemplary ScPa output switching unit 900, comprising a stack of the four core components as described above. For example, the ScPa output switching unit 900 includes two switching elements (a PMOS switch 910 and an NMOS switch 940). The ScPa output switching unit 900 also includes two series elements (a PMOS series connector 920 and an NMOS series connector 930). In some examples, the series elements correspond to common-source transistors fed into common-gate transistors, as well as various other configurations and / or implementations. As shown in the exemplary schematic diagram of the ScPa output switching unit 900 in Figure 9, the input-output (IO) voltage (VDDH) is set to be at most twice the core voltage (VDDL). The IO voltage (VDDH) corresponds to the high-voltage rail driving the ScPa output switching unit 900, and the core voltage (VDDL) corresponds to the low-voltage rail driving the ScPa output switching unit 900.

[0127] In some examples, the required voltage for each device gate in the ScPa output switching unit 900 is as follows: the gate of the NMOS switching element 940 is driven by a clock between 0 and VDDL; the gate of the NMOS series element 930 is driven by VDDL; the gate of the PMOS series element 920 is driven by the difference between the IO voltage and the core voltage (VDDH-VDDL); and the gate of the PMOS switching element 910 is driven by a clock between VDDH-VDDL and VDDH.

[0128] In the illustrative example, according to the embodiment of the invention shown in FIG10, circuit 1000 is used to apply the required voltage to each of the four core elements in the stack of the ScPa output unit. NMOS switching element 1040 (e.g., “Nsw” in FIG10) may be the same as or similar to NMOS switching element 940 in FIG9 and can be directly driven by the core voltage inverter driven by the VDDL rail of circuit 1000. NMOS series element 1030 (e.g., “Ncas” in FIG10) may be the same as or similar to NMOS series gate 930 in FIG9 and can be directly connected to the VDDL rail of circuit 1000.

[0129] The signal voltage conversion required for the PMOS switching element 1010 (e.g., “Psw” in Figure 10, where the PMOS switching element 1010 may be the same as or similar to the PMOS switching element 910 in Figure 9) can be achieved by using a capacitor 1005 (C1) connected between the gate of the NMOS switch 1040 and the gate of the PMOS switch 1010, wherein the capacitor 1005 (C1) is charged to a voltage (VDDH-VDDL) across the capacitor. Since no current is required to maintain the voltage difference across the series capacitor, the power requirement of this level shifter preferably does not exceed the power required to drive a simple core voltage inverter. A very small cross-coupled PMOS element 1007 (P3) may be included in circuit 1000 to periodically replenish any small amount of charge that leaks from the capacitor over time.

[0130] In some embodiments, the PMOS series gate (e.g., the PMOS series element 1020 "Pcas" in Figure 10) is biased below the VDDH rail by a charge pump driven by the VDDL battery clock input, as shown in the example circuit 1100 of Figure 11. In example circuit 1100, the core supply voltage is DC-converted via a series capacitor to produce a rail one core voltage below the VDDH rail. The Vpcas rail of the entire ScPa array consumes very little DC current only due to gate leakage. The embodiment of the charge pump is implemented using a very small switch, so the current required for operation is negligible.

[0131] The advantages of these circuits include separating the speed of the I / O component performance from the speed of the circuit operating at the core component speed. For example, the circuits implemented according to various aspects of the invention described above, because the circuits operate at the core component speed, are not speed-limited by the performance of the I / O devices. They do not draw power from the VDDH rail for signal buffering and battery switching. Because the Vgs of all components remain constant, the switching resistance does not increase when VDDH decreases. Therefore, efficiency does not decrease when reducing output power by lowering the rail voltage. In some embodiments, because the circuits described above allow the gates of the PMOS switch and the PMOS series components to drop to negative voltages below the ground rail, VDDH can be reduced to very low levels (e.g., at least in some cases, VDDH can be reduced below VDDL), while maintaining fast operation, good switching resistance, and efficiency.

[0132] Figure 12 illustrates a computing device architecture 1200 for a computing device that can implement one or more of the technologies described above. In some examples, the computing device may include a mobile device, a wearable device, an augmented reality device (such as a virtual reality (VR), augmented reality (AR), or mixed reality (MR) device), a personal computer, a laptop computer, a video server, a vehicle (or a computing device on a vehicle), or other devices. The components shown in the computing device architecture 1200 communicate electrically with each other using wiring 1205, such as a bus. The computing device architecture 1200 includes a processing unit 1210 and computing device wiring 1205 for coupling various computing device components to the processor 1210, which includes computing device memory 1215, such as read-only memory (ROM) 1220 and random-access memory (RAM) 1225.

[0133] The computing device architecture 1200 may include a cache of high-speed memory that is directly connected to, close to, or integrated into the processor 1210. The computing device architecture 1200 may copy data from memory 1215 and / or storage device 1230 to the cache 1212 for fast access by the processor 1210. In this way, the cache can improve performance and avoid latency for the processor 1210 while waiting for data. These components and other engines can be controlled or configured to control the processor 1210 to perform various operations. Other computing device memories 1215 may also be used. Memory 1215 may contain multiple different types of memory with different performance characteristics. Processor 1210 may include any general-purpose processor and hardware or software services, such as services 1 1232, 2 1234, and 3 1236 stored in storage device 1230, configured to work with a dedicated processor to control processor 1210, with the software instructions incorporated into the processor design. Processor 1210 may be a standalone system, including multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may be symmetric or asymmetric.

[0134] To enable users to interact with the computing device architecture 1200, the input device 1245 can represent any number of input mechanisms, such as a microphone for receiving voice, a touch screen for gesture or graphical input, a keyboard, a mouse, motion input, voice, etc. The output device 1235 can be one or more output mechanisms known to those skilled in the art, such as a monitor, projector, television, speaker device, etc. In some cases, a multi-mode computing device allows users to provide diverse inputs to communicate with the computing device architecture 1200. The communication interface 1240 typically controls and manages the user's inputs and the computing device's outputs. There are no restrictions on operation on any particular hardware configuration, so the basic functions here can be easily replaced with improved hardware or software configurations during development.

[0135] Storage device 1230 is non-volatile memory and may be a hard disk or other type of computer-readable media capable of storing computer-accessible data, such as magnetic tape, flash memory card, solid-state drive, digital multifunction disk, cassette tape, RAM, ROM, and hybrid media thereof. Storage device 1230 may include services 1232, 1234, and 1236 for controlling processor 1210. Furthermore, other hardware or software modules or engines are contemplated. Storage device 1230 may be connected to computing device wiring 1205. In one aspect, a hardware module implementing a specific function may include software or processor-readable code stored in a computer-readable medium to perform those functions in conjunction with necessary hardware such as processor 1210, wiring 1205, output device 1235, etc.

[0136] The terms “device” or “element” are not limited to one or a specific number of physical objects (e.g., a smartphone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that performs at least some of the functions of the invention as disclosed herein.

[0137] Individual aspects of the invention may be described herein as processes or methods, shown as flowcharts or data flow diagrams. While flowcharts may describe operations as sequential processes, multiple operations may be executed in parallel or simultaneously. Furthermore, the order of these operations may be rearranged. The process terminates upon completion of an operation, but may continue with other steps not included in the diagram. A process may correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0138] The technologies described herein can be implemented in electronic hardware, computer software, firmware, or any combination thereof. These technologies can be implemented in any of a variety of devices, such as general-purpose computers, handheld wireless communication devices, or integrated circuits, and have a variety of uses, including applications in handheld wireless communication devices or other devices. Any feature described as a module or component can be implemented together in an integrated circuit device or separately in separate but interoperable logic devices. If implemented in software, these technologies can be implemented at least in part by a computer-readable data storage medium containing program code, which, when the instructions contained in the program code are executed, performs one or more of the methods described above.

[0139] The code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits, field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor may be configured to perform any of the techniques described in the disclosure. A general-purpose processor may be a microprocessor; however, in alternative instances, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices. [Simplified Explanation of the Diagram]

[0029] The following description of the subject matter of this application is provided with reference to the accompanying drawings:

[0030] Figure 1 is a block diagram of an example wireless communication network;

[0031] FIG2A is a block diagram of a wireless communication device that can be implemented as a station (STA) or an access point (AP) according to some embodiments;

[0032] FIG2B is a schematic block diagram of the receiver data stream architecture of the wireless communication device of FIG2A according to some embodiments;

[0033] Figure 2C is a schematic block diagram of a transmitter data stream architecture for transmitting radio frequency (RF) signals in a wireless medium according to some embodiments;

[0034] Figure 3 is an architecture of a digitally controlled switched-capacitor power amplifier (ScPa) according to some embodiments, configured to have two arrays equipped with CMOS inverters, wherein each array contains multiple capacitors that can be driven or not driven by the inverters in the array.

[0035] Figure 4 is an example schematic diagram of a merged drive scheme using a non-Cartesian system implemented ScPa architecture according to some embodiments;

[0036] Figure 5 is an example schematic diagram of a merged driving scheme of the ScPa architecture implemented in a Cartesian system according to some embodiments;

[0037] Figure 6 is an example schematic diagram of a combined drive scheme of the ScPa architecture implemented according to some embodiments using a Cartesian system and four inverter and capacitor array branches;

[0038] Figure 7 is an IQ constellation diagram showing a cut diamond corresponding to the performance degradation threshold of a digital power amplifier according to some embodiments;

[0039] Figure 8 is an example of the allocation of capacitor array units (e.g., output units) when the IQ shared unit ScPa does not need to be trimmed, according to some embodiments, and a schematic diagram of an example of the allocation of capacitor array units when the IQ shared unit ScPa needs to be trimmed.

[0040] Figure 9 is an example schematic diagram of a stacked ScPa output switching unit comprising four core elements according to some embodiments;

[0041] Figure 10 is an example circuit according to some embodiments for applying a desired voltage to each of the stacks of four core elements in the ScPa output unit;

[0042] FIG11 is an example circuit according to some embodiments having a charge pump driven by a VDDL level clock input;

[0043] Figure 12 is a block diagram of a computing system according to some embodiments for illustrating several aspects of implementation.

Claims

1. A switching capacitor power amplifier device, comprising: A switching capacitor array comprising a plurality of unit cells shared between in-phase and quadrature components of an input radio frequency signal, each of the plurality of unit cells comprising a capacitor and an inverter; a corresponding control bit pair associated with each of the plurality of unit cells, wherein the corresponding control bit pair comprises a first control bit and a second control bit, the first control bit being configured to selectively enable or disable the driving of the corresponding unit cell based on the in-phase component, and the second control bit being configured to selectively enable or disable the driving of the corresponding unit cell based on the quadrature component; and truth table logic configuring a first unit cell subset and a second unit cell subset of the plurality of unit cells, wherein the truth table logic responds to a double enable condition of the corresponding control bit pair to drive the first unit cell subset based on the in-phase component, and the truth table logic responds to the double enable condition of the corresponding control bit pair to drive the second unit cell subset based on the quadrature component.

2. The switching capacitor power amplifier device as described in claim 1, wherein, The switched capacitor power amplifier device implements an analog clipping scheme based on a group of unit cells with the dual enable conditions of the switched capacitor array configured by the truth table logic, wherein the group of unit cells with the dual enable conditions is included among the plurality of unit cells.

3. The switching capacitor power amplifier device as described in claim 2, wherein, The analog clipping scheme is implemented using the truth table logic to drive the unit cells of the first half of the group with the dual enable condition at an in-phase clock corresponding to the in-phase component, and to drive the unit cells of the second half of the group with the dual enable condition at a quadrature phase clock corresponding to the quadrature phase component.

4. The switching capacitor power amplifier device as described in claim 3, wherein, The unit cell in the group having the dual-energized condition is equal to the difference between the sum of the amplitudes of the in-phase component and the quadrature phase component and the number of the plurality of unit cells.

5. The switching capacitor power amplifier device as claimed in claim 1, wherein, The dual enable condition corresponds to each bit of the corresponding control bit pair being set to a high value, indicating that the corresponding unit can be driven based on the in-phase component and the corresponding unit can be driven based on the quadrature phase component.

6. The switching capacitor power amplifier device as claimed in claim 1, wherein, The first subset of unit cells includes the first half of the plurality of unit cells, and the second subset of unit cells includes the second half of the plurality of unit cells.

7. The switching capacitor power amplifier device as claimed in claim 1, wherein, The number of units in the first unit subset is equal to the number of units in the second unit subset.

8. The switching capacitor power amplifier device as claimed in claim 1, wherein, One of the first and second unit cell subsets contains even-indexed unit cells of the switched capacitor array, and the other of the first and second unit cell subsets contains odd-indexed unit cells of the switched capacitor array.

9. The switching capacitor power amplifier device as claimed in claim 1, wherein, The truth table logic allows the plurality of unit cells to be driven according to the corresponding control bit pairs in the absence of the dual enable condition.

10. The switching capacitor power amplifier device as claimed in claim 1, wherein, The truth table logic encodes the priority of the I component of the first unit cell subset as higher than the priority of the Q component, and maps the encoding of the priority of the I component as higher than the priority of the Q component to the dual enable condition. The first control bit and the second control bit of the corresponding unit cell in the first unit cell subset are both set to high values. The truth table logic also encodes the priority of the Q component of the second unit cell subset as higher than the priority of the I component, and maps the encoding of the priority of the Q component as higher than the priority of the I component to the dual enable condition. The first control bit and the second control bit of the corresponding unit cell in the second unit cell subset are both set to high values.

11. The switching capacitor power amplifier device as claimed in claim 1, wherein, Each of the plurality of unit cells in the switched capacitor array is switched and coupled to the main input of the inductor transformer or balun in the switched capacitor power amplifier device.

12. The switching capacitor power amplifier device as claimed in claim 1, wherein: The truth table logic enables the switched capacitor power amplifier device to automatically implement an analog clipping scheme for in-phase quadrature phase amplitude codes whose total amplitude is greater than the number of unit cells in the plurality of unit cells; and each unit cell having the dual enable condition implements the analog clipping scheme locally based on the truth table logic configured for each unit cell having the dual enable condition.

13. The switching capacitor power amplifier device as claimed in claim 1, further comprising: The level converter in the output switching unit includes an NMOS switching device gate, an NMOS series gate, a PMOS series gate, and a PMOS switching device gate.

14. The switching capacitor power amplifier device as claimed in claim 13, wherein, The gate of the NMOS switching device is driven by a core voltage inverter driven by the core voltage (VDDL) rail. The NMOS series gate is coupled to the core voltage rail. The PMOS series gate is biased below the fixed voltage of the input-output voltage (VDDH) rail. The PMOS switching device gate is charged to the VDDH-VDDL voltage by signal voltage conversion through the capacitor between the NMOS switching device gate and the PMOS switching device gate.

15. The switching capacitor power amplifier device as claimed in claim 14, wherein, The input-output voltage (VDDH) is set to be at most twice the core voltage (VDDL).

16. The switching capacitor power amplifier device as claimed in claim 14, wherein, The output switching unit also includes cross-coupled PMOS elements for periodically replenishing any small amounts of charge that leaks from the capacitor over time.

17. The switching capacitor power amplifier device as claimed in claim 14, wherein, The PMOS series gate is coupled to a charge pump driven by a core voltage level clock input, and the core power supply voltage of the charge pump is DC-DC converted through a series capacitor to generate a rail that is one core voltage lower than the input and output voltage rails.

18. A method for controlling a switching capacitor power amplifier with adaptive clipping, comprising: Obtain the in-phase code and quadrature-phase code corresponding to the input radio frequency signal; The sum of the absolute values ​​of the in-phase code and the quadrature phase code is compared with a threshold, the threshold corresponding to the number of unit cells in the multiple unit cells of the switching capacitor array of the switching capacitor power amplifier: Based on the in-phase code and the quadrature phase code, each output unit of the inverter and capacitor array in the switching capacitor power amplifier is determined to be an in-phase clock-enabled output unit, a quadrature phase clock-enabled output unit, a dual-enabled output unit, or a deactivated output unit, wherein when the sum of the absolute values ​​of the in-phase code and the quadrature phase code is less than or equal to the threshold, the number of dual-enabled output units is zero, and when the sum of the absolute values ​​of the in-phase code and the quadrature phase code is greater than the threshold, the number of dual-enabled output units is equal to the sum of the absolute values ​​of the in-phase code and the quadrature phase code minus the threshold; Half of the dual-enabled output units are controlled to be driven by the in-phase clock, and the other half of the dual-enabled output units are controlled to be driven by the quadrature phase clock; The output unit that controls the inverter and capacitor array with the in-phase clock enabled is driven by the in-phase clock; and the output unit that controls the inverter and capacitor array with the quadrature clock enabled is driven by the quadrature clock.

19. The method as described in claim 18, wherein, The operation of controlling the switched capacitor power amplifier includes: implementing an analog clipping scheme based on a set of unit cells with dual enable conditions of the switched capacitor array having truth table logic, wherein the set of unit cells with the dual enable conditions is included among the plurality of unit cells.

20. The method as described in claim 19, wherein, The truth table logic causes the unit cells of the first half of the group with the dual enable condition to be driven by the in-phase clock corresponding to the in-phase code, and causes the unit cells of the second half of the group with the dual enable condition to be driven by the quadrature phase clock corresponding to the quadrature phase code.

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