Programmable direct memory access device and method thereof
Patent Information
- Application Number
- TW114133366
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-09-01
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2045-08-31
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Figure TWG2TB001917371_001 
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Figure TWG2TB001917371_003
Abstract
Claims
1. A programmable direct memory access device (PDMA) connected to a plurality of peripheral devices, the PMA comprising: a classification module for classifying the plurality of peripheral devices into an input / output (I / O) type peripheral device or a memory type peripheral device based on data access type; an event triggering module for determining whether a trigger event conforms to a plurality of trigger items, and if the trigger event conforms to any one of the plurality of trigger items, the event triggering module generates a trigger signal; and a control module connected to the classification module and the event triggering module, and performing data access according to the trigger signal, wherein... The control module performs data access based on the type of the peripheral device that serves as the data source and the type of the peripheral device that serves as the data destination.
2. The programmable direct memory access device as described in claim 1, wherein if the data source corresponds to the input / output peripheral device, the control module obtains a source data width and a data source address from the input / output peripheral device; if the data destination corresponds to the input / output peripheral device, the control module obtains a destination data width and a data destination address from the input / output peripheral device; the control module performs data access based on the source data width, the data source address, the destination data width, and the data destination address.
3. The programmable direct memory access device as described in claim 1, wherein if the data source corresponds to the input / output peripheral device, the control module obtains a source data width and a data source address from the input / output peripheral device; if the data destination corresponds to the memory peripheral device, the control module obtains a data destination address from the memory peripheral device; the control module performs data access based on the source data width, the data source address, and the data destination address.
4. The programmable direct memory access device as described in claim 1, wherein if the data source corresponds to the memory-type peripheral device, the control module obtains a data source address from the memory-type peripheral device; if the data destination corresponds to the input / output peripheral device, the control module obtains a data destination address and a destination data width from the input / output peripheral device; the control module performs data access based on the data source address, the destination data width, and the data destination address.
5. The programmable direct memory access device as described in claim 1, wherein if the data source corresponds to the memory-type peripheral device, the control module obtains a data source address from the memory-type peripheral device; if the data destination corresponds to the memory-type peripheral device, the control module obtains a data destination address from the memory-type peripheral device; and the control module performs data access based on the data source address and the data destination address.
6. The programmable direct memory access device as described in claim 1, wherein when one of the data source or the data destination is the memory-type peripheral device, the control module performs data access according to an operating mode set by an access mode module.
7. A programmable direct memory access method, comprising: classifying a plurality of peripheral devices into an input / output peripheral device or a memory peripheral device according to data access type; determining the type of the peripheral device as a data source and the type of the peripheral device as a data destination; obtaining a data source address based on the input / output peripheral device or the memory peripheral device as the data source, and obtaining a data destination address based on the input / output peripheral device or the memory peripheral device as the data destination; and performing data access based on the data source address and the data destination address.
8. The programmable direct memory access method as described in claim 7, wherein when the data source corresponds to the input / output peripheral device, a source data width is further obtained from the input / output peripheral device to perform data access.
9. The programmable direct memory access method as described in claim 7, wherein when the data destination corresponds to the input / output peripheral device, a destination data width is further obtained from the input / output peripheral device to perform data access.
10. The programmable direct memory access method as described in claim 7, wherein if at least one of the peripheral device as the data source and the peripheral device as the data destination is the memory-type peripheral device, data access is further performed according to one of the selected operating modes.
Citation Information
Patent Citations
Cache bank interface unit
TW200527207A
Systems, methods, and devices for memory allocation for a memory device
TW202533057A
Host controller interface descriptor fetching unit
US20020052987A1
General purpose hardware acceleration via deirect memory access
US20100030927A1
Peripheral communication
US20140304439A1
