Electronic circuit and method for stabilizing voltage thereof

Abstract

A method for stabilizing node potentials in an electronic circuit and the electronic circuit thereof are disclosed. The electronic circuit includes a conductive path coupled between a voltage source and a node and having parasitic inductance. The method includes the electronic circuit generating a high-frequency current flowing through the conductive path during high-frequency operation and providing a capacitor connected in parallel with the parasitic inductance to form a low-impedance path for the high-frequency current. By shunting a portion of the high-frequency current through the low-impedance path, the voltage drop caused by the flow through the parasitic inductance can be suppressed, thereby stabilizing the node potential.

Claims

1. A method for stabilizing a node potential in an electronic circuit, the electronic circuit including a conductive path coupled between a voltage source and a node, the conductive path having a parasitic inductance, the method comprising: generating a high-frequency current flowing through the conductive path during a high-frequency operation of the electronic circuit; providing a capacitor connected in parallel with the parasitic inductance to form a low-impedance path for the high-frequency current; and shunting a portion of the high-frequency current through the low-impedance path to suppress a voltage drop caused by the high-frequency current flowing through the parasitic inductance, thereby stabilizing the node potential.

2. The method as described in claim 1, wherein one of the capacitors has a capacitance value greater than or equal to 10 picofarads (pF).

3. The method as described in claim 1, wherein the electronic circuit is a ring oscillator circuit, and the node is a power supply node of the ring oscillator circuit.

4. The method as described in claim 1, wherein the electronic circuit is a magnetoresistive random access memory circuit, and the conductive path includes at least one bit line or at least one source line of the magnetoresistive random access memory circuit.

5. The method as described in claim 1, wherein the electronic circuit is a magnetoresistive random access memory circuit, and the step of shunting the portion of the high-frequency current via the low-impedance path comprises: shunting a portion of the high-frequency current flowing through at least one bit line via a first capacitor connected in parallel to the at least one bit line; and shunting a portion of the high-frequency current flowing through at least one source line via a second capacitor connected in parallel to the at least one source line.

6. The method as claimed in claim 1, wherein the electronic circuit is a ring oscillator circuit, and the step of shunting the portion of the high-frequency current via the low-impedance path comprises: shunting a portion of the high-frequency current originating from the voltage source via the capacitor coupled in parallel to the conductive path to a power node supplied to an oscillation loop of the ring oscillator circuit.

7. A ring oscillator circuit, comprising: an oscillating circuit including a plurality of inverters, the oscillating circuit being coupled to a node; a conductive path coupled between a voltage source and the node, the conductive path having a parasitic inductance; and a capacitor, the two ends of the capacitor being coupled to the voltage source and the node respectively, for parallel connection to the parasitic inductance.

8. The ring oscillator circuit as described in claim 7, wherein one of the capacitors has a capacitance value greater than or equal to 10 picofarads (pF).

9. The ring oscillator circuit as claimed in claim 7, wherein the capacitor is used to stabilize a potential at the node to increase the operating speed of the ring oscillator circuit when the parasitic inductance of the conductive path is greater than 200 nanohenry (nH).

10. The ring oscillator circuit as claimed in claim 7, wherein the oscillation circuit further includes a NAND gate coupled to the inverters.

11. The ring oscillator circuit as claimed in claim 10, wherein the node is coupled to the inverter and the inverters to provide a voltage from the voltage source to the inverter and the inverters.

12. The ring oscillator circuit as described in claim 10, wherein the number of inverters is an even number.

13. The ring oscillator circuit as claimed in claim 10, wherein the inverter comprises: a first input for receiving a uniform energy signal; a second input coupled to an output of one of the inverters; and an output coupled to an input of another of the inverters.

14. A magnetoresistive random access memory (MRAM) circuit, comprising: a memory array including a plurality of memory cells; at least one first conductive path including a portion of at least one bit line coupled to the memory cells, the at least one first conductive path having a first parasitic inductance between two dissimilar first nodes; and at least one second conductive path including a portion of at least one source line coupled to the memory cells, the at least one second conductive path having a second parasitic inductance between two dissimilar second nodes; at least one first capacitor coupled to the two dissimilar first nodes of the at least one first conductive path to be connected in parallel to the first parasitic inductance of the at least one first conductive path; and at least one second capacitor coupled to the two dissimilar second nodes of the at least one second conductive path to be connected in parallel to the second parasitic inductance of the at least one second conductive path.

15. The magnetoresistive random access memory circuit as described in claim 14, wherein the capacitance value of one of the at least first capacitor and the at least second capacitor is greater than or equal to 10 picofarads.

16. The magnetoresistive random access memory circuit as claimed in claim 14, wherein the at least one first capacitor and the at least one second capacitor are used to suppress a voltage drop on the first conductive path and the second conductive path during a write operation to expand one of the write windows of the memory cells.

17. The magnetoresistive random access memory circuit as described in claim 14, wherein the at least one first conductive path comprises a plurality of bit lines, and the plurality of bit lines are commonly coupled to the at least one first capacitor.

18. The magnetoresistive random access memory circuit as claimed in claim 14, wherein the at least one second conductive path includes a plurality of source lines, and the plurality of source lines are commonly coupled to the at least one second capacitor.

19. The magnetoresistive random access memory circuit as described in claim 14, wherein the magnetoresistive random access memory circuit is a spin-transfer torque magnetoresistive random access memory (STT-MRAM), a spin-orbit torque magnetoresistive random access memory (SOT-MRAM), or a voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM).

20. The magnetoresistive random access memory circuit as described in claim 14, wherein the capacitance value of one of the at least one first capacitor is substantially equal to the capacitance value of one of the at least one second capacitor.

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