Package structure and method of fabricating the same
Patent Information
- Application Number
- TW114141460
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2045-10-26
Smart Images

Figure TWG2TB001917459_001 
Figure TWG2TB001917459_002 
Figure TWG2TB001917459_003
Abstract
Claims
1. A packaging structure, comprising: A first intermediary layer and a second intermediary layer; A redistribution layer is located above and electrically connected to the first and second interposers; a wafer is located above and electrically connected to the redistribution layer; a bridging wafer is located below the redistribution layer and between the first and second interposers, and electrically connected to the redistribution layer; an encapsulation material covers the bridging wafer; a first underfill material is located between the redistribution layer and the first interposer; and a second underfill material is located between the redistribution layer and the bridging wafer, wherein the encapsulation material contacts the first underfill material and the second underfill material.
2. The packaging structure as described in claim 1, wherein the redistribution layer is electrically connected to the wafer via a bonding wire.
3. The packaging structure as described in claim 1, wherein the packaging material extends to one side surface of the first interposer and one side surface of the second interposer.
4. The packaging structure as described in claim 1, wherein the bridging chip comprises glass, silicon, or an organic material.
5. A method for manufacturing a packaging structure, comprising: A wafer is bonded to a first side of a redistribution layer and electrically connected to the redistribution layer; A bridging chip is bonded to a second side of the redistribution layer relative to the first side and electrically connected to the redistribution layer; and a first interposer and a second interposer are respectively bonded to the redistribution layer, wherein the redistribution layer is electrically connected to the first interposer and the second interposer.
6. The method of claim 5, wherein bonding the wafer to the first side of the redistribution layer comprises: connecting a bonding pad on a surface of the wafer away from the redistribution layer and the redistribution layer via a bonding wire.
7. The method as described in claim 5 further comprises: after bonding the first interposer and the second interposer to the redistribution layer respectively, forming an encapsulation material to cover the bridging chip.
8. The method as described in claim 7, wherein the encapsulation material fills a gap between the first interposer and the second interposer.
Citation Information
Patent Citations
Stacked type chip packaging structure and packaging method
CN105118823A
Methods and apparatus for wafer-level die bridge
JP2019125779A
Package structure and method for forming the same
US20220246509A1
