Semiconductor device and manufacturing method thereof
Patent Information
- Application Number
- TW114150286
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2045-12-18
Smart Images

Figure TWG2TB001917515_001 
Figure TWG2TB001917515_002 
Figure TWG2TB001917515_003
Abstract
Claims
1. A semiconductor structure, comprising: The substrate includes the device area and the surrounding area; A first isolation structure is embedded in the peripheral region of the substrate; A second isolation structure is embedded in the device region of the substrate; The device includes a character line embedded in the substrate, extending along a first direction and from the peripheral region into the device region, wherein the character line includes: a character line width portion embedded in a wide trench of the substrate located in the peripheral region, wherein the character line width portion extends into the first isolation structure, and the character line width portion includes: a first metal filler layer located in the wide trench; and a conductive nitride layer, wherein the first metal filler layer is located on the conductive nitride layer and the conductive nitride layer is located on the sidewall of the first metal filler layer; and a character line narrow portion connecting the character line width portion and embedded in a narrow trench of the substrate located in the device region, wherein the width of the character line width portion in a second direction is greater than the width of the character line narrow portion, the second direction being perpendicular to the first direction, and the character line narrow portion at least partially extending into the second isolation structure, wherein the character line narrow portion includes: A conductive nitride filling layer, connected to the conductive nitride layer and extending along the first direction; and a cover layer, located on the conductive nitride filling layer, wherein, in a cross-sectional view along the second direction, the center of the bottom surface of the cover layer covers the top of the conductive nitride filling layer.
2. The semiconductor structure as claimed in claim 1, wherein the conductive nitride filling layer comprises the same material as the conductive nitride layer.
3. The semiconductor structure of claim 1, wherein the distance between the top surface of the first metal filling layer and the top surface of the substrate is equal to the distance between the top surface of the conductive nitride filling layer and the top surface of the substrate.
4. The semiconductor structure of claim 1, wherein the distance between the top surface of the first metal filling layer and the top surface of the substrate is not equal to the distance between the top surface of the conductive nitride filling layer and the top surface of the substrate.
5. The semiconductor structure as described in claim 1, further comprising: An insulating liner is located on the sidewalls of the first isolation structure and the second isolation structure.
6. The semiconductor structure as claimed in claim 1, wherein the character linewidth further comprises: A second metal filler layer is located in the wide trench and covers the top surface of the first metal filler layer and the top surface of the conductive nitride layer.
7. The semiconductor structure as claimed in claim 1, wherein the word line narrow portion further comprises: An insulating filler layer is located on the cover layer in the narrow trench, and the cover layer comprises polycrystalline silicon.
8. The semiconductor structure of claim 1, wherein in the cross-sectional view along the second direction of the character linewidth portion, the width of the top surface of the conductive nitride layer located on one side of the first metal filler layer is W1a, the width of the top surface of the first metal filler layer is W1, and W1a:W1 is 1:1 to 1:
4.
9. The semiconductor structure of claim 8, wherein in the cross-sectional view along the second direction at the narrow portion of the character line, the width of the top surface of the conductive nitride filling layer is W3, wherein W3 is twice W1a.
10. The semiconductor structure of claim 1, wherein the semiconductor structure includes a plurality of word lines, and the word line width of a first plurality of word lines is located on one side of the device region, the word line width of a second plurality of word lines is located on the other side of the device region, wherein the first plurality of word lines and the second plurality of word lines are arranged alternately.
11. The semiconductor structure of claim 1, wherein the capping layer covers the entire top surface of the conductive nitride filling layer.
12. The semiconductor structure of claim 1, wherein the narrow trench is filled with the conductive nitride filling layer for less than one-third of its depth at the second isolation structure, and the wide trench is filled with the conductive nitride layer and the first metal filling layer for less than one-third of its depth at the first isolation structure.
13. A method for manufacturing a semiconductor structure, comprising: Wide trenches and narrow trenches are respectively formed in the peripheral area of the substrate and the device area; A conductive nitride material layer is formed in the wide trench and the narrow trench, wherein the conductive nitride material layer fills the narrow trench but not the wide trench; a first metal filler material layer is formed on the conductive nitride material layer, the first metal filler material layer filling the remaining space of the wide trench; a portion of the first metal filler material layer is removed to form a first metal filler layer in the wide trench; a portion of the conductive nitride material layer is removed to form a conductive nitride layer in the wide trench and a conductive nitride filler layer in the narrow trench, the conductive nitride layer being located on the sidewall of the first metal filler layer, the conductive nitride filler layer extending along a first direction and connecting to the conductive nitride layer, wherein the width of the wide trench in a second direction perpendicular to the first direction is greater than that of the narrow trench; And a capping layer is formed on the conductive nitride filler layer.
14. The manufacturing method as described in claim 13, further comprising: A first opening and a second opening are respectively formed in the peripheral region of the substrate and the device region; A first isolation structure is formed in the first opening; A second isolation structure is formed in the second opening; the wide groove is formed in the first isolation structure; and the narrow groove is formed in the second isolation structure.
15. The manufacturing method as described in claim 14, further comprising: An insulating liner is formed on the substrate and in the first opening and the second opening.
16. The manufacturing method as described in claim 13, wherein the character lines comprise: The character line width is embedded in the width trench and includes the first metal filling layer and the conductive nitride layer; And a narrow portion of the character line, which connects to the wide portion of the character line and is embedded in the narrow portion groove, wherein the width of the wide portion of the character line in the second direction is greater than the width of the narrow portion of the character line, wherein the narrow portion of the character line includes the conductive nitride filling layer and the cover layer.
17. The manufacturing method as described in claim 13 further includes: An insulating filler layer is formed on the cover layer in the narrow trench, and the cover layer comprises polycrystalline silicon.
18. The manufacturing method as described in claim 13, further comprising: A second metal filler layer is formed in the wide trench, and the second metal filler layer covers the top surface of the first metal filler layer and the top surface of the conductive nitride layer.
Citation Information
Patent Citations
Semiconductor memory device and forming method thereof
CN115084141A
Preparation method of semiconductor structure
CN119277773A
Method of forming semiconductor structure
CN119855136A
Semiconductor device and method of forming the same
TW202508413A
Semiconductor structure
US20250159866A1
