Semiconductor device structure and methods of forming the same

Abstract

Embodiments of this disclosure provide a semiconductor device structure and a method for forming the same. The semiconductor device structure includes a first transistor disposed above a substrate, a second transistor disposed above the first transistor, and a front-side interconnect structure disposed above the second transistor. The front-side interconnect structure includes a first metal layer and a first capacitor, with the first metal layer electrically coupled to the first capacitor. The semiconductor device structure further includes a back-side interconnect structure disposed below the first transistor, and the back-side interconnect structure includes a second metal layer and a second capacitor. The second metal layer is electrically coupled to the second capacitor, and the first capacitor is electrically coupled to the second capacitor via a conductive path, the conductive path including multiple components of the first transistor and the second transistor.

Claims

1. A method for forming a semiconductor device structure, comprising the following steps: forming an isolation region over a substrate, wherein the isolation region has a dielectric constant of about 3 to about 5; forming a first source / drain region over the substrate; forming a contact etch stop layer over the first source / drain region; forming an interlayer dielectric over the contact etch stop layer, wherein the interlayer dielectric has a dielectric constant of about 3 to about 5, the contact etch stop layer being disposed between the interlayer dielectric and the isolation region, and a dielectric constant of the contact etch stop layer being greater than the dielectric constant of the interlayer dielectric or the dielectric constant of the isolation region; forming a first gate structure adjacent to the first source / drain region; forming a dielectric material to separate the first gate structure into two segments; forming a first conductive feature in the dielectric material; and recessing the first conductive feature to form a recess. A cover layer is formed in the recess; and a second conductive feature is formed, wherein the second conductive feature is electrically coupled to the first source / drain region and the first conductive feature.

2. The method for forming a semiconductor device structure as described in claim 1 further includes the following steps: forming a second source / drain region, wherein the second source / drain region is disposed below the first source / drain region, and the first gate structure is adjacent to the second source / drain region.

3. The method for forming a semiconductor device structure as described in claim 2 further includes the step of forming a third conductive feature below the second source / drain region.

4. A method for forming a semiconductor device structure as described in claim 3, wherein the third conductive feature is electrically coupled to the first conductive feature.

5. The method for forming a semiconductor device structure as described in claim 4 further includes the steps of: forming a front-side interconnect structure on a front side of the substrate and forming a back-side interconnect structure on a back side of the substrate.

6. A method for forming a semiconductor device structure as described in claim 5, wherein the front interconnect structure includes a first metal layer and the back interconnect structure includes a second metal layer.

7. A method for forming a semiconductor device structure as described in claim 6, wherein the first metal layer is electrically coupled to the second conductive feature, and the second metal layer is electrically coupled to the third conductive feature.

8. The method of forming a semiconductor device structure as described in claim 7 further includes the step of: forming a first capacitor in the front interconnect structure, wherein the first capacitor is electrically coupled to the first metal layer.

9. A method of forming a semiconductor device structure, comprising the steps of: forming a gate spacer over a multilayer stack; forming a source / drain recess in the multilayer stack; forming a first source / drain region and a second source / drain region in the source / drain recess, wherein the first source / drain region is disposed above the second source / drain region; forming a contact etch stop layer over the first source / drain region, wherein the contact etch stop layer extends along a first sidewall of the gate spacer and interfaces with the first sidewall; forming a gate structure adjacent to the gate spacer, wherein the gate structure includes a gate dielectric layer, the gate spacer has a second sidewall interfacing with the gate dielectric layer, the first sidewall of the gate spacer is opposite to the gate structure, and a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer or a dielectric constant of the contact etch stop layer; A first conductive feature is formed above the first source / drain region, wherein the first conductive feature is electrically coupled to the first source / drain region and the second source / drain region; a front interconnect structure is formed above the first conductive feature, wherein the front interconnect structure includes a first capacitor electrically coupled to a first metal layer, and the first metal layer is electrically coupled to the first conductive feature; a second conductive feature is formed below the second source / drain region, wherein the second conductive feature is electrically coupled to the second source / drain region; and a back interconnect structure is formed below the second conductive feature, wherein the back interconnect structure includes a second capacitor electrically coupled to a second metal layer, and the second metal layer is electrically coupled to the second conductive feature.

10. A semiconductor device structure comprising: a first transistor disposed above a substrate; a second transistor disposed above the first transistor; a front interconnect structure disposed above the second transistor, wherein the front interconnect structure includes a first metal layer and a first capacitor, and the first metal layer is electrically coupled to the first capacitor; and a back interconnect structure disposed below the first transistor, wherein the back interconnect structure includes a second metal layer and a second capacitor, and the second metal layer is electrically coupled to the second capacitor, wherein the first capacitor is electrically coupled to the second capacitor via a conductive path, and the conductive path includes a plurality of components of the first transistor and the second transistor.

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