Semiconductor device

Abstract

Provided a semiconductor device including a substrate with a first conductivity type, a first electrostatic discharge protection polysilicon layer, a second electrostatic discharge protection polysilicon layer and a first metal layer. The substrate defines a pad area, and includes a first area and a second area, wherein the first area surrounds the second area, and the pad area is at least partially overlapped with the second area. The first electrostatic discharge protection polysilicon layer is disposed on the substrate in the first area and is electrically isolated from the substrate. The second electrostatic discharge protection polysilicon layer is disposed on the substrate in the second area and a portion thereof is in physical contact with the substrate. The first metal layer is disposed above and electrically connected to the first electrostatic discharge protection polysilicon layer and the second electrostatic discharge protection polysilicon layer.

Description

[Technical Field] This invention relates to a semiconductor device, and more particularly to a semiconductor device having electrostatic discharge protection elements between the gate and source and between the gate and drain. [Previous Technology] Electrostatic discharge (ESD) protection components are widely used in the semiconductor industry. An ideal ESD protection component must have characteristics such as a high current withstand limit, small layout area, high turn-on speed, and an appropriate safe operating area to ensure that the ESD protection component can provide good instantaneous current withstand capability under limited area resources. Conventional techniques place electrostatic discharge (ESD) protection components around the gate electrode. The advantage is that in the event of an ESD incident, the discharge can be eliminated at the gate without the need for peripheral circuitry, resulting in a faster response time and simpler component design. However, because conventional techniques typically place ESD protection components between the gate and source, they cannot eliminate ESD between the gate and drain, leaving no ESD protection between the gate and drain. Furthermore, placing ESD protection components between the gate and drain requires additional space and fabrication processes.

New content

Implementation Method

Claims

1. A semiconductor device, comprising: A substrate having a first conductivity type defines a padding region and has a first region and a second region, the first region surrounding the second region and the padding region at least partially overlapping the second region; a first electrostatic discharge (ESD) protected polycrystalline silicon layer is located on the substrate in the first region and is electrically insulated from the substrate; a second ESD protected polycrystalline silicon layer is located on the substrate in the second region, wherein a portion of the second ESD protected polycrystalline silicon layer is in contact with the substrate solid. And a first metal layer, disposed above the first electrostatic discharge protection polycrystalline silicon layer and the second electrostatic discharge protection polycrystalline silicon layer, and electrically connected to the first electrostatic discharge protection polycrystalline silicon layer and the second electrostatic discharge protection polycrystalline silicon layer.

2. The semiconductor device as described in claim 1 further includes: A main body region having a second conductivity type is disposed in the substrate of the second region.

3. The semiconductor device as described in claim 1, wherein the second electrostatic discharge protected polycrystalline silicon layer comprises: A first doped layer having a first conductivity type is disposed on the substrate in the central region of the second region; A plurality of second doped layers having a second conductivity type and a plurality of third doped layers having a first conductivity type are alternately disposed on the substrate in the peripheral region of the second region, wherein the first doped layer is in contact with the substrate entity.

4. The semiconductor device as described in claim 1 further includes an insulating layer disposed between the substrate and the first electrostatic discharge protected polycrystalline silicon layer.

5. The semiconductor device as claimed in claim 1, wherein the first electrostatic discharge protected polycrystalline silicon layer and the second electrostatic discharge protected polycrystalline silicon layer share a common doped layer having the first conductivity type.

6. The semiconductor device as claimed in claim 5, wherein the first metal layer is electrically connected to the common doped layer through at least one first contact.

7. The semiconductor device as described in claim 1, wherein the first metal layer is electrically connected to the first electrostatic discharge protected polysilicon layer and the second electrostatic discharge protected polysilicon layer through a plurality of first contacts.

8. The semiconductor device as claimed in claim 1, wherein the substrate comprises a base layer and an epitaxial layer located on the base layer, and a portion of the second electrostatic discharge protected polycrystalline silicon layer is in solid contact with the epitaxial layer.

9. The semiconductor device as claimed in claim 1, wherein the reverse breakdown voltage of the second electrostatic discharge protected polycrystalline silicon layer is greater than the reverse breakdown voltage of the first electrostatic discharge protected polycrystalline silicon layer.

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