Active gate driver for switching device

Abstract

This invention provides an active gate driver suitable for switching elements, comprising an adjustment circuit, a first control circuit, a PWM control circuit, and a second control circuit. When both the first and second control signals received by the first and second control circuits are at a low level, the switching voltage is at a low potential. When the first and second control signals are at a low level and a high level, respectively, the switching voltage is at a first high potential. When the first control signal is at a high level, the switching voltage is at a second high potential. The first high potential is lower than the second high potential. When the second control signal is at a high level, and the first control signal is in PWM mode switching between high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in PWM mode.

Description

Active gate driver for switching elements ACTIVE GATE DRIVER FOR SWITCHING DEVICE Technical Field

[0001] This case relates to an active gate driver, and more particularly to an active gate driver suitable for switching elements. Prior Technology

[0002] With the rapid development of power semiconductor technology, the use of SiC (silicon carbide) power devices in existing gate drivers suitable for switching elements has become an important trend for achieving high-efficiency power conversion. SiC power devices have characteristics such as high breakdown voltage, low on-resistance, and the ability to operate under high temperature and high frequency conditions, enabling switching elements to operate at higher switching speeds while reducing switching losses, thereby improving overall efficiency and power density.

[0003] However, the high slew rate will lead to an increase in EMI (electromagnetic interference) noise and increase the risk of mis-passing, thus affecting system stability.

[0004] Therefore, developing an active gate driver that can improve upon the aforementioned conventional technology is an urgent need at present. Summary of the Invention

[0005] The purpose of this invention is to provide an active gate driver for switching elements that can achieve a balance between maintaining switching losses and reducing EMI noise and the risk of false circuits by controlling the switching rate of the switching elements, thereby improving system stability while maintaining high efficiency.

[0006] To achieve the above objectives, this invention provides an active gate driver suitable for switching elements, comprising an adjustment circuit, a first control circuit, a PWM control circuit, and a second control circuit. The adjustment circuit is configured to output a switching voltage to the switching element. The first control circuit is electrically connected to the adjustment circuit. The PWM control circuit is electrically connected to the first control circuit and is configured to provide a first control signal to the first control circuit. The second control circuit is electrically connected to the first control circuit and is configured to receive a second control signal. When both the first and second control signals are low, the switching voltage is at a low potential. When the first control signal is low and the second control signal is high, the switching voltage is at a first high potential. When the first control signal is high, the switching voltage is at a second high potential. The low potential is lower than the first high potential, and the first high potential is lower than the second high potential. When the second control signal is high and the first control signal is in PWM mode switching between high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in PWM mode.

[0007] To achieve the above objectives, this invention also provides an active gate driver suitable for switching elements, comprising an adjustment circuit, a first control circuit, a PWM control circuit, and a second control circuit. The adjustment circuit is configured to output a switching voltage to the switching element. The first control circuit is electrically connected to the adjustment circuit. The PWM control circuit is electrically connected to the first control circuit and is configured to provide a first control signal to the first control circuit. The second control circuit is electrically connected to the first control circuit and is configured to receive the second control signal. When the first control signal is low and the second control signal is high, the switching voltage is at a low potential. When both the first and second control signals are low, the switching voltage is at a first high potential. When the first control signal is high, the switching voltage is at a second high potential. The low potential is lower than the first high potential, and the first high potential is lower than the second high potential. When the second control signal is low and the first control signal is in PWM mode switching between high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in PWM mode.

[0008] To achieve the above objectives, this invention also provides an active gate driver suitable for switching elements, comprising an adjustment circuit, a first control circuit, a PWM control circuit, and a second control circuit. The adjustment circuit is configured to output a switching voltage to the switching element. The first control circuit is electrically connected to the adjustment circuit. The PWM control circuit is electrically connected to the first control circuit and is configured to provide a first control signal to the first control circuit. The second control circuit is electrically connected to the first control circuit and is configured to receive the second control signal. When the first control signal is high and the second control signal is low, the switching voltage is at a low potential. When both the first and second control signals are high, the switching voltage is at a first high potential. When the first control signal is low, the switching voltage is at a second high potential. The low potential is lower than the first high potential, and the first high potential is lower than the second high potential. When the second control signal is high and the first control signal is in PWM mode switching between high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in PWM mode.

[0009] To achieve the above objectives, this invention also provides an active gate driver suitable for switching elements, comprising an adjustment circuit, a first control circuit, a PWM control circuit, and a second control circuit. The adjustment circuit is configured to output a switching voltage to the switching element. The first control circuit is electrically connected to the adjustment circuit. The PWM control circuit is electrically connected to the first control circuit and is configured to provide a first control signal to the first control circuit. The second control circuit is electrically connected to the first control circuit and is configured to receive a second control signal. When both the first and second control signals are high, the switching voltage is at a low potential. When the first control signal is high and the second control signal is low, the switching voltage is at a first high potential. When the first control signal is low, the switching voltage is at a second high potential. The low potential is lower than the first high potential, and the first high potential is lower than the second high potential. When the second control signal is low and the first control signal is in PWM mode switching between high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in PWM mode. Simple Explanation of the Diagram

[0010] Figure 1 is a schematic diagram of the architecture of an active gate driver and its applicable switching elements according to an embodiment of this invention.

[0011] Figure 2 illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the first embodiment of this case.

[0012] Figure 3A illustrates the waveforms of the first control signal, the second control signal, and the drive voltage in the active gate driver under the first control mode, according to the first embodiment of this case.

[0013] Figure 3B illustrates the waveforms of the first control signal, the second control signal, and the drive voltage in the active gate driver under the second control mode, according to the first embodiment of this case.

[0014] Figures 4, 5, and 6 are schematic diagrams of the operating waveforms of the active gate driver and its applicable switching elements during actual testing in the first embodiment.

[0015] Figure 7 illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the second embodiment of this case.

[0016] Figure 8 illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the third embodiment of this case.

[0017] Figure 9 illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the fourth embodiment of this case. Implementation

[0018] Some typical embodiments that embody the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various variations in different forms, all of which do not depart from the scope of this case, and the descriptions and illustrations therein are essentially for illustrative purposes and not for limiting this case.

[0019] Please refer to Figure 1, which is a schematic diagram of the architecture of an active gate driver and its applicable switching element according to an embodiment of this invention. As shown in Figure 1, the active gate driver 1 is applied to the switching element 2. Specifically, the active gate driver 1 is electrically connected to the switching element 2 and is used to drive the operation of the switching element 2. The active gate driver 1 includes a first control circuit 11, a second control circuit 12, a PWM (pulse width modulation) control circuit 13, and an adjustment circuit 14.

[0020] The PWM control circuit 13 is configured to provide a first control signal Sc1 to a first control circuit, wherein the first control signal Sc1 can be at a high level or a low level. Furthermore, the first control signal Sc1 can switch between high and low levels in a PWM state, and the PWM control circuit 13 can adjust the duty cycle of the first control signal Sc1 in the PWM state as needed. In some embodiments, when the first control signal Sc1 is in the PWM state, it switches between high and low levels at a switching frequency on the order of MHz. The specific implementation of the PWM control circuit 13 is not limited in this application, and any suitable circuit topology can be adopted according to actual needs.

[0021] The first control circuit 11 is electrically connected to the PWM control circuit 13 to receive a first control signal Sc1, wherein the first control signal Sc1 is used to control the operation of the first control circuit 11. The second control circuit 12 is electrically connected to the first control circuit 11 and is configured to receive a second control signal Sc2, wherein the second control signal Sc2 is used to control the operation of the second control circuit 12. The second control signal Sc2 can be at a high or low level, and the source of the second control signal Sc2 is not limited in this invention and can be, for example, but not limited to, a microcontroller or a digital signal processor. The input and output terminals of the adjustment circuit 14 are electrically connected to the first control circuit 11 and the switching element 2, respectively. The adjustment circuit 14 is configured to adjust the received drive voltage Vdr to a switching voltage Vsw and then provide it to the switching element 2, wherein the switching voltage Vsw is used to control the operation of the switching element 2.

[0022] The first control signal Sc1 and the second control signal Sc2 are used to control the operation of the first control circuit 11 and the second control circuit 12, respectively. The operating state of the first control circuit 11 and the second control circuit 12 will affect the potential of the drive voltage Vdr, and the potential of the drive voltage Vdr corresponds to the potential of the switching voltage Vsw.

[0023] According to the first embodiment of this case, when both the first control signal Sc1 and the second control signal Sc2 are at a low level, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the first potential, thereby making the switching voltage Vsw at a low potential. When the first control signal Sc1 is at a low level and the second control signal Sc2 is at a high level, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the second potential, thereby making the switching voltage Vsw at the first high potential. When the first control signal Sc1 is at a high level, regardless of whether the second control signal Sc2 is at a high or low level, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via the first control circuit 11, so that the driving voltage Vdr is at the third potential, thereby making the switching voltage Vsw at the second high potential.

[0024] Since the first potential point P1, the second potential point P2, and the third potential point P3 have different potential magnitudes, the potentials of the driving voltage Vdr and the switching voltage Vsw will change accordingly when the input terminal of the adjusting circuit 14 is electrically connected to different potential points. For example, the first potential is lower than the second potential, and the second potential is lower than the third potential. Correspondingly, the low potential is lower than the first high potential, and the first high potential is lower than the second high potential. Furthermore, the specific magnitudes of the first, second, and third potentials can be determined according to the characteristics of the switching element 2, and the potentials of the first potential point P1, the second potential point P2, and the third potential point P3 can be set accordingly.

[0025] Furthermore, when the second control signal Sc2 is high and the first control signal Sc1 is in PWM mode switching between high and low levels, the drive voltage Vdr rises, thereby causing the switching voltage Vsw to rise. The rate at which the switching voltage Vsw rises depends on the duty cycle of the first control signal Sc1 in PWM mode. By controlling the duty cycle of the first control signal Sc1 in PWM mode, the rate of change of the switching voltage Vsw can be controlled, thereby controlling the switching rate of the switching element 2. This achieves a balance between maintaining switching losses and reducing EMI noise and the risk of false switching, thus improving system stability while maintaining high efficiency. In addition, in some embodiments, the first control signal Sc1 has different duty cycles in different time periods in PWM mode, resulting in different rates of change of the switching voltage Vsw in the different time periods. This allows for more flexible control of the change of the switching voltage Vsw.

[0026] Please refer to Figure 2, which illustrates an embodiment of the active gate driver and switching element shown in Figure 1 according to the first embodiment of this invention. In Figure 2, elements with similar functions and structures to those in Figure 1 are indicated by the same reference numerals and will not be described again here. As shown in Figure 2, the first control circuit 11 includes an isolation unit 111, a drive unit 112, a drive unit 113, a switch Q11, and a switch Q12. The isolation unit 111 is electrically connected to the PWM control circuit 13 to receive a first control signal Sc1, and the isolation unit 111 converts the first control signal Sc1 into a first drive signal, achieving electrical isolation while performing signal conversion. The specific implementation of the isolation unit 111 is not limited in this invention; it may include, for example, a digital isolation integrated circuit, but is not limited thereto. The drive unit 112 is electrically connected between the isolation unit 111 and the switch Q11, and is configured to receive the first drive signal provided by the isolation unit 111, and drive the switch Q11 according to the first drive signal. In some embodiments, the drive unit 112 is configured to adjust the voltage level of the first drive signal to the drive voltage range applicable to the switch Q11. The drive unit 113 is electrically connected between the isolation unit 111 and the switch Q12, and is configured to receive the first drive signal provided by the isolation unit 111, and drive the switch Q12 according to the first drive signal. In some embodiments, the drive unit 113 is configured to adjust the voltage level of the first drive signal to the drive voltage range applicable to the switch Q12. Furthermore, in some embodiments, the isolation unit 111, drive unit 112, and drive unit 113 have operating frequencies in the MHz range.

[0027] In this embodiment, the driving unit 112 includes a buffer electrically connected between the isolation unit 111 and the switch Q11. The first driving signal is provided to the switch Q11 after being buffered by the buffer. The switch Q11 is configured to turn on when the voltage of the first driving signal it receives is higher than a preset voltage (e.g., a preset threshold voltage). The switch Q11 may be, for example, but not limited to, an NMOS (N-metal-oxide-semiconductor). The driving unit 113 includes an inverter electrically connected between the isolation unit 111 and the switch Q12. The first driving signal is provided to the switch Q12 after being inverted by the inverter. The switch Q12 is configured to turn on when the voltage of the first driving signal it receives is higher than a preset voltage (e.g., a preset threshold voltage). The switch Q12 may be, for example, but not limited to, an NMOS.

[0028] Similarly, the second control circuit 12 includes an isolation unit 121, a drive unit 122, a drive unit 123, a switch Q21, and a switch Q22. The isolation unit 121 receives the second control signal Sc2 and converts it into a second drive signal, achieving electrical isolation during signal conversion. The specific implementation of the isolation unit 121 is not limited in this invention; it may include, for example, a digital isolation integrated circuit, but is not limited thereto. The drive unit 122 is electrically connected between the isolation unit 121 and the switch Q21, and is configured to receive the second drive signal provided by the isolation unit 121 and drive the switch Q21 according to the second drive signal. In some embodiments, the drive unit 122 is configured to adjust the voltage level of the second drive signal to a drive voltage range applicable to the switch Q21. The drive unit 123 is electrically connected between the isolation unit 121 and the switch Q22, and is configured to receive the second drive signal provided by the isolation unit 121 and drive the switch Q22 according to the second drive signal. In some embodiments, the drive unit 123 is configured to adjust the voltage level of the second drive signal to the drive voltage range applicable to the switch Q22.

[0029] Furthermore, in this embodiment, the driving unit 122 includes a buffer electrically connected between the isolation unit 121 and the switch Q21. The second driving signal is provided to the switch Q21 after being buffered by the buffer. The switch Q21 is configured to turn on when the voltage of the second driving signal it receives is higher than a preset voltage (e.g., a preset threshold voltage). The switch Q21 may be, for example, but is not limited to, an NMOS transistor. The driving unit 123 includes an inverter electrically connected between the isolation unit 121 and the switch Q22. The second driving signal is provided to the switch Q22 after being inverted by the inverter. The switch Q22 is configured to turn on when the voltage of the second driving signal it receives is higher than a preset voltage (e.g., a preset threshold voltage). The switch Q22 may be, for example, but is not limited to, an NMOS transistor.

[0030] Furthermore, switches Q21 and Q22 are connected in series between the second potential point P2 and the first potential point P1, with switches Q21 and Q22 respectively coupled to the second potential point P2 and the first potential point P1. When the second control signal Sc2 is high, switch Q21 is turned on and switch Q22 is turned off; when the second control signal Sc2 is low, switch Q21 is turned off and switch Q22 is turned on. Switches Q11 and Q12 are connected in series between the third potential point P3 and the connection point of switches Q21 and Q22, with switch Q11 coupled to the third potential point P3 and switch Q12 coupled to the connection point of switches Q21 and Q22. Moreover, the connection point of switches Q11 and Q12 is electrically connected to the input terminal of the adjustment circuit 14. When the first control signal Sc1 is high, switch Q11 is turned on and switch Q12 is turned off; when the first control signal Sc1 is low, switch Q11 is turned off and switch Q12 is turned on.

[0031] Accordingly, when both the first control signal Sc1 and the second control signal Sc2 are at a low level, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via switches Q12 and Q22. When the first control signal Sc1 is at a low level and the second control signal Sc2 is at a high level, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via switches Q12 and Q21. When the first control signal Sc1 is at a high level, regardless of whether the second control signal Sc2 is at a high or low level, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via switch Q11.

[0032] The adjustment circuit 14 includes a resistor R and a capacitor C. The first end of the resistor R is electrically connected to the connection point of switches Q11 and Q12 in the first control circuit 11, the second end of the resistor R is electrically connected to the first end of the capacitor C, and the second end of the capacitor C is grounded.

[0033] It should be noted that, provided that the aforementioned functions can be achieved, the specific implementation of the first control circuit 11, the second control circuit 12, and the adjustment circuit 14 is not limited in this case, and can be adjusted according to actual needs, without being limited to the implementation shown in Figure 2.

[0034] Specifically, in the first control circuit 11, the drive unit 112 and the switch Q11 may implement the same control logic in different embodiments. For example, in some embodiments, the drive unit 112 includes an inverter (not shown) electrically connected between the isolation unit 111 and the switch Q11. The switch Q11 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage (e.g., a preset threshold voltage). The switch Q11 may, for example but not limited to, use a PMOS (P-metal-oxide-semiconductor) (not shown). Furthermore, the drive unit 113 and the switch Q12 may also implement the same control logic in different embodiments. For example, in some embodiments, the drive unit 113 includes a buffer (not shown) electrically connected between the isolation unit 111 and the switch Q12. The switch Q12 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage (e.g., a preset threshold voltage). The switch Q11 may, for example but not limited to, use a PMOS (not shown).

[0035] Similarly, in the second control circuit 12, the drive unit 122 and the switch Q21 may implement the same control logic in different embodiments. For example, in some embodiments, the drive unit 122 includes an inverter (not shown) electrically connected between the isolation unit 121 and the switch Q21, and the switch Q21 is configured to turn on when the voltage of the second drive signal it receives is lower than a preset voltage (e.g., a preset threshold voltage). The switch Q21 may, for example, but not limited to, use a PMOS (not shown). Furthermore, the drive unit 123 and the switch Q22 may also implement the same control logic in different embodiments. For example, in some embodiments, the drive unit 123 includes a buffer (not shown) electrically connected between the isolation unit 121 and the switch Q22, and the switch Q22 is configured to turn on when the voltage of the second drive signal it receives is lower than a preset voltage (e.g., a preset threshold voltage). The switch Q22 may, for example, but not limited to, use a PMOS (not shown).

[0036] In this embodiment, the switching element 2 is a MOSFET (metal-oxide-semiconductor field-effect transistor), such as a SiC (silicon carbide) MOSFET. The gate of the switching element 2 is electrically connected to the second terminal of the resistor R in the adjustment circuit 14, the source of the switching element 2 is grounded, and the switching voltage Vsw is the gate-source voltage of the switching element 2. Furthermore, in the figure, Ids represents the drain-source current of the switching element 2, and Vds represents the drain-source voltage of the switching element 2. It should be noted that the switching element 2 is not limited to a MOSFET; for example, the switching element 2 can also be an IGBT (insulated-gate bipolar transistor).

[0037] Please refer to Figure 3A and Figure 2. Figure 3A illustrates the waveforms of the first control signal, the second control signal, and the drive voltage in the active gate driver under the first control mode according to the first embodiment of this invention, wherein the first control signal does not have a PWM state. In this embodiment, the switching element 2 is switched from the off state to the on state, and the first control signal Sc1 does not have a PWM state during this switching process. As shown in Figure 3A, firstly, both the first control signal Sc1 and the second control signal Sc2 are at a low level, so the drive voltage Vdr is at the first potential V1. Then, the first control signal Sc1 is at a low level, and the second control signal Sc2 is at a high level, so the drive voltage Vdr is at the second potential V2. Finally, both the first control signal Sc1 and the second control signal Sc2 are at a high level, so the drive voltage Vdr is at the third potential V3. It can be seen that the drive voltage Vdr first rises from the first potential V1 to the second potential V2, and then rises to the third potential V3. Compared to the direct rise of the driving voltage Vdr from the first potential V1 to the third potential V3, introducing the second potential V2 can change the rising slope of the switching voltage Vsw, thereby altering the switching rate of the switching element 2. The switching rate includes the rate of change of the drain-source current Ids and the drain-source voltage Vds of the switching element 2. However, since the second potential V2 is a fixed value, it is difficult to achieve more precise control over the rising slope of the switching voltage Vsw and even the switching rate of the switching element 2.

[0038] Please refer to Figure 3B in conjunction with Figure 2. Figure 3B illustrates the waveforms of the first control signal, the second control signal, and the drive voltage in the active gate driver under the second control mode according to the first embodiment of this invention, wherein the first control signal has a PWM state. In this embodiment, the switching element 2 is switched from the off state to the on state, and the first control signal Sc1 has a PWM state during this switching process. As shown in Figure 3B, firstly, both the first control signal Sc1 and the second control signal Sc2 are at a low level, so the drive voltage Vdr corresponds to the first potential V1. Then, the first control signal Sc1 is in a PWM state and switches between a low level and a high level, while the second control signal Sc2 is at a high level, so the drive voltage Vdr corresponds to the switching between the second potential V2 and the third potential V3. Finally, both the first control signal Sc1 and the second control signal Sc2 are at a high level, so the drive voltage Vdr corresponds to the third potential V3.

[0039] When the drive voltage Vdr switches between the second potential V2 and the third potential V3, the drive voltage Vdr can be equivalent to the equivalent potential Veq. The magnitude of the equivalent potential Veq will affect the rising slope of the switching voltage Vsw, and thus affect the switching rate of the switching element 2. Since the magnitude of the equivalent potential Veq is determined by the duty cycle of the first control signal Sc1 in the PWM state, the rising slope of the switching voltage Vsw and the switching rate of the switching element 2 can be adjusted by controlling the duty cycle of the first control signal Sc1 in the PWM state. Furthermore, as mentioned above, in some embodiments, the first control signal Sc1 can be controlled to have different duty cycles at different times in the PWM state, thereby allowing for more flexible control of the changes in the switching voltage Vsw and the switching rate of the switching element 2. In this way, flexible control of the rising slope of the switching voltage Vsw and the switching rate of the switching element 2 can be achieved, so as to achieve a balance between maintaining switching losses and reducing EMI noise and the risk of false turn-on, thereby improving system stability while maintaining high efficiency.

[0040] Please refer to Figures 4 and 5, along with Figure 2. Figures 4 and 5 are schematic diagrams of the operating waveforms of the active gate driver and its applicable switching element during actual testing in the first embodiment. In Figures 4 and 5, the switching element 2 is switched from the off state to the on state, and the operating waveforms of the active gate driver 1 and its applicable switching element 2 in three operating modes are represented by three different line shapes. In the first operating mode, the drive voltage Vdr rises directly from the first potential V1 (0V) to the third potential V3 (18V), and the corresponding operating waveform is represented by a solid line. In the second operating mode, the first control method shown in Figure 3A is used to cause the drive voltage Vdr to rise from the first potential V1 (0V) to the second potential V2 (13V), and then to the third potential V3 (18V), and the corresponding operating waveform is represented by a dotted chain line. In the third working mode, the second control method shown in Figure 3B is adopted, so that the driving voltage Vdr rises from the first potential V1 (0V), then switches between the second potential V2 (13V) and the third potential V3 (18V), and finally maintains at the third potential V3 (18V). The corresponding working waveform is represented by a dashed line.

[0041] In the embodiment shown in Figure 4, capacitor C is not included in the adjustment circuit 14. As shown in Figure 4, the waveform of the switching voltage Vsw in the third operating mode is between the waveforms of the switching voltage Vsw in the first and second operating modes, so that the waveform of the drain-source voltage Vds in the third operating mode is between the waveforms of the drain-source voltage Vds in the first and second operating modes, and the waveform of the drain-source current Ids in the third operating mode is also between the waveforms of the drain-source current Ids in the first and second operating modes. Therefore, it can be seen that the second control method based on PWM can indeed add an additional slew rate level to achieve flexible control of the slew rate.

[0042] In the embodiment shown in Figure 5, the adjustment circuit 14 includes a resistor R and a capacitor C, i.e., it adopts the topology shown in Figure 2. Compared to the waveform shown in Figure 4, as shown in Figure 5, the presence of capacitor C can enhance the effect of the second control method when the drain-source current Ids is small.

[0043] Please refer to Figure 6 in conjunction with Figure 2. Figure 6 is a schematic diagram of the operating waveforms of the active gate driver and its applicable switching element during actual testing in the first embodiment. Figure 6 illustrates the operating waveforms of the active gate driver 1 and its applicable switching element 2 when using the second control mode shown in Figure 3B and when the first control signal Sc1 has different duty cycles. Specifically, the solid line represents the operating waveform when the duty cycle of the first control signal Sc1 in PWM state is 0.75, the dotted chain line represents the operating waveform when the duty cycle of the first control signal Sc1 in PWM state is 0.5, and the dashed line represents the operating waveform when the duty cycle of the first control signal Sc1 in PWM state is 0.25. As can be seen from Figure 6, if the duty cycle of the first control signal Sc1 in PWM state is different, the switching voltage Vsw, drain-source voltage Vds, and drain-source current Ids will also be different. In other words, when using the second control method shown in Figure 3B, if the duty cycle of the first control signal Sc1 changes in the PWM state, it will indeed cause a corresponding change in the switching voltage Vsw and the switching rate of the switching element 2.

[0044] It should be noted that in this case, when the first control circuit 11 and the second control circuit 12 adopt circuit structures different from those in the aforementioned embodiments, the relationship between the levels of the first control signal Sc1 and the second control signal Sc2 and the potentials of the driving voltage Vdr and the switching voltage Vsw may change accordingly, but the same technical effect can still be achieved using the same principle. Several embodiments will be illustrated below.

[0045] Please refer to Figure 1 again. According to the second embodiment of this case, when the first control signal Sc1 is at a low level and the second control signal Sc2 is at a high level, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the first potential, thereby making the switching voltage Vsw at a low potential. When both the first control signal Sc1 and the second control signal Sc2 are at a low level, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the second potential, thereby making the switching voltage Vsw at the first high potential. When the first control signal Sc1 is at a high level, regardless of whether the second control signal Sc2 is at a high or low level, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via the first control circuit 11, so that the driving voltage Vdr is at the third potential, thereby making the switching voltage Vsw at the second high potential. Furthermore, when the second control signal Sc2 is low and the first control signal Sc1 is in PWM mode switching between high and low levels, the drive voltage Vdr rises, which in turn causes the switching voltage Vsw to rise.

[0046] Please refer to Figure 7, which illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the second embodiment of this invention. In Figure 7, elements with similar functions and structures to those in Figure 2 are indicated by the same reference numerals and will not be described again here. However, in this embodiment, as shown in Figure 7, the drive unit 122a includes an inverter electrically connected between the isolation unit 121 and the switch Q21, and the drive unit 123a includes a buffer electrically connected between the isolation unit 121 and the switch Q22. Accordingly, when the second control signal Sc2 is high, switch Q21 is off and switch Q22 is on; when the second control signal Sc2 is low, switch Q21 is on and switch Q22 is off.

[0047] Therefore, when the first control signal Sc1 is low and the second control signal Sc2 is high, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via switches Q12 and Q22. When both the first control signal Sc1 and the second control signal Sc2 are low, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via switches Q12 and Q21. When the first control signal Sc1 is high, regardless of whether the second control signal Sc2 is high or low, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via switch Q11.

[0048] Furthermore, the drive unit 122a and switch Q21 may implement the same control logic in different embodiments. For example, in some embodiments, drive unit 122a includes a buffer (not shown) electrically connected between isolation unit 121 and switch Q21, and switch Q21 is configured to turn on when the voltage of the second drive signal it receives is lower than a preset voltage. Switch Q21 may, for example, but not limited to, use a PMOS (not shown). Additionally, drive unit 123a and switch Q22 may also implement the same control logic in different embodiments. For example, in some embodiments, drive unit 123a includes an inverter (not shown) electrically connected between isolation unit 121 and switch Q22, and switch Q22 is configured to turn on when the voltage of the second drive signal it receives is lower than a preset voltage. Switch Q22 may, for example, but not limited to, use a PMOS (not shown).

[0049] Please refer to Figure 1 again. According to the third embodiment of this case, when the first control signal Sc1 is at a high level and the second control signal Sc2 is at a low level, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the first potential, thereby making the switching voltage Vsw at a low potential. When both the first control signal Sc1 and the second control signal Sc2 are at a high level, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the second potential, thereby making the switching voltage Vsw at the first high potential. When the first control signal Sc1 is at a low level, regardless of whether the second control signal Sc2 is at a high level or a low level, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via the first control circuit 11, so that the driving voltage Vdr is at the third potential, thereby making the switching voltage Vsw at the second high potential. Furthermore, when the second control signal Sc2 is high and the first control signal Sc1 is in PWM mode switching between high and low levels, the drive voltage Vdr rises, which in turn causes the switching voltage Vsw to rise.

[0050] Please refer to Figure 8, which illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the third embodiment of this invention. In Figure 8, elements with similar functions and structures to those in Figure 2 are indicated by the same reference numerals and will not be described again here. However, in this embodiment, as shown in Figure 8, the drive unit 112a includes an inverter electrically connected between the isolation unit 111 and the switch Q11, and the drive unit 113a includes a buffer electrically connected between the isolation unit 111 and the switch Q12. Accordingly, when the first control signal Sc1 is high, switch Q11 is off and switch Q12 is on; when the first control signal Sc1 is low, switch Q11 is on and switch Q12 is off.

[0051] Therefore, when the first control signal Sc1 is high and the second control signal Sc2 is low, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via switches Q12 and Q22. When both the first control signal Sc1 and the second control signal Sc2 are high, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via switches Q12 and Q21. When the first control signal Sc1 is low, regardless of whether the second control signal Sc2 is high or low, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via switch Q11.

[0052] Furthermore, the drive unit 112a and switch Q11 may implement the same control logic in different embodiments. For example, in some embodiments, drive unit 112a includes a buffer (not shown) electrically connected between isolation unit 111 and switch Q11, and switch Q11 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage. Switch Q11 may, for example, but not limited to, use a PMOS (not shown). Additionally, drive unit 113a and switch Q12 may also implement the same control logic in different embodiments. For example, in some embodiments, drive unit 113a includes an inverter (not shown) electrically connected between isolation unit 111 and switch Q12, and switch Q12 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage. Switch Q12 may, for example, but not limited to, use a PMOS (not shown).

[0053] Please refer to Figure 1 again. According to the fourth embodiment of this case, when both the first control signal Sc1 and the second control signal Sc2 are at a high level, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the first potential, and thus the switching voltage Vsw is at a low potential. When the first control signal Sc1 is at a high level and the second control signal Sc2 is at a low level, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via the first control circuit 11 and the second control circuit 12, so that the driving voltage Vdr is at the second potential, and thus the switching voltage Vsw is at the first high potential. When the first control signal Sc1 is at a low level, regardless of whether the second control signal Sc2 is at a high level or a low level, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via the first control circuit 11, so that the driving voltage Vdr is at the third potential, and thus the switching voltage Vsw is at the second high potential. Furthermore, when the second control signal Sc2 is low and the first control signal Sc1 is in PWM mode switching between high and low levels, the drive voltage Vdr rises, which in turn causes the switching voltage Vsw to rise.

[0054] Please refer to Figure 9, which illustrates one embodiment of the active gate driver and switching element shown in Figure 1 according to the third embodiment of this invention. In Figure 8, elements with similar functions and structures to those in Figure 2 are indicated by the same reference numerals and will not be described again here. However, in this embodiment, as shown in Figure 9, drive unit 112a includes an inverter electrically connected between isolation unit 111 and switch Q11, and drive unit 113a includes a buffer electrically connected between isolation unit 111 and switch Q12. Accordingly, when the first control signal Sc1 is high, switch Q11 is off and switch Q12 is on; when the first control signal Sc1 is low, switch Q11 is on and switch Q12 is off. Drive unit 122a includes an inverter electrically connected between isolation unit 121 and switch Q21, and drive unit 123a includes a buffer electrically connected between isolation unit 121 and switch Q22. Therefore, when the second control signal Sc2 is at a high level, switch Q21 is turned off and switch Q22 is turned on; when the second control signal Sc2 is at a low level, switch Q21 is turned on and switch Q22 is turned off.

[0055] Therefore, when both the first control signal Sc1 and the second control signal Sc2 are at a high level, the input terminal of the adjustment circuit 14 is electrically connected to the first potential point P1 via switches Q12 and Q22. When the first control signal Sc1 is at a high level and the second control signal Sc2 is at a low level, the input terminal of the adjustment circuit 14 is electrically connected to the second potential point P2 via switches Q12 and Q21. When the first control signal Sc1 is at a low level, regardless of whether the second control signal Sc2 is at a high or low level, the input terminal of the adjustment circuit 14 is electrically connected to the third potential point P3 via switch Q11.

[0056] Furthermore, the drive unit 112a and switch Q11 may implement the same control logic in different embodiments. For example, in some embodiments, drive unit 112a includes a buffer (not shown) electrically connected between isolation unit 111 and switch Q11, and switch Q11 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage. Switch Q11 may, for example, but not limited to, use a PMOS (not shown). Additionally, drive unit 113a and switch Q12 may also implement the same control logic in different embodiments. For example, in some embodiments, drive unit 113a includes an inverter (not shown) electrically connected between isolation unit 111 and switch Q12, and switch Q12 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage. Switch Q12 may, for example, but not limited to, use a PMOS (not shown).

[0057] Similarly, drive unit 122a and switch Q21 may implement the same control logic in different embodiments. For example, in some embodiments, drive unit 122a includes a buffer (not shown) electrically connected between isolation unit 121 and switch Q21, and switch Q21 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage. Switch Q21 may, for example, but not limited to, use a PMOS (not shown). Furthermore, drive unit 123a and switch Q22 may also implement the same control logic in different embodiments. For example, in some embodiments, drive unit 123a includes an inverter (not shown) electrically connected between isolation unit 121 and switch Q22, and switch Q22 is configured to turn on when the voltage of the first drive signal it receives is lower than a preset voltage. Switch Q22 may, for example, but not limited to, use a PMOS (not shown).

[0058] It should be noted that the above are merely preferred embodiments for illustrative purposes, and the scope of this application is not limited to the described embodiments. The scope of this application is determined by the claims of the appended patent application. Furthermore, this application may be modified in various ways by those skilled in the art, but all such modifications shall not depart from the protection sought by the claims of the appended patent application.

[0059] 1: Active gate driver 2: Switching elements 11: First control circuit 12: Second control circuit 13: PWM control circuit 14: Adjusting the circuit Sc1: First control signal Sc2: Second control signal Vdr: Drive voltage Vsw: Switching voltage P1: First potential point P2: Second potential point P3: Third potential point 111: Isolation Unit 112, 113: Drive Unit Q11, Q12: Switches 121: Isolation Unit 122, 123: Drive Unit Q21, Q22: Switches R: Resistance C: Capacitor Ids: Drain-Source Current Vds: Drain-Source Voltage V1: First potential V2: Second potential V3: Third potential Veq: Equivalent potential 112a, 113a: Drive unit 122a, 123a: Drive units

Claims

1. An active gate driver suitable for a switching element, comprising: an adjustment circuit configured to output a switching voltage to the switching element; a first control circuit electrically connected to the adjustment circuit; a PWM control circuit electrically connected to the first control circuit and configured to provide a first control signal to the first control circuit; and a second control circuit electrically connected to the first control circuit and configured to receive a second control signal, wherein... When both the first control signal and the second control signal are low, the switching voltage is at a low potential; when the first control signal is low and the second control signal is high, the switching voltage is at a first high potential; when the first control signal is high, the switching voltage is at a second high potential, wherein the low potential is less than the first high potential, and the first high potential is less than the second high potential; when the second control signal is high and the first control signal is in PWM mode switching between the high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in the PWM mode.

2. The active gate driver as claimed in claim 1, wherein the adjustment circuitry is configured to adjust a drive voltage received at its input terminal to the switching voltage; when both the first control signal and the second control signal are at the low level, the input terminal is electrically connected to a first potential point via the first control circuit and the second control circuit, so that the drive voltage is at the first potential; when the first control signal is at the low level and the second control signal is at the high level, the input terminal is electrically connected to a second potential point via the first control circuit and the second control circuit, so that the drive voltage is at the second potential; when the first control signal is at the high level, the input terminal is electrically connected to a third potential point via the first control circuit, so that the drive voltage is at the third potential; the first potential is less than the second potential, and the second potential is less than the third potential.

3. The active gate driver as claimed in claim 2, wherein the first control circuit includes a first switch and a second switch, and the second control circuit includes a third switch and a fourth switch; the third switch and the fourth switch are connected in series between the second potential point and the first potential point; when the second control signal is at the high level, the third switch and the fourth switch are turned on and off respectively, and when the second control signal is at the low level, the third switch and the fourth switch are turned off and on respectively; the first switch and the second switch are connected in series between the third potential point and the connection point of the third switch and the fourth switch; when the first control signal is at the high level, the first switch and the second switch are turned on and off respectively, and when the first control signal is at the low level, the first switch and the second switch are turned off and on respectively.

4. An active gate driver suitable for a switching element, comprising: an adjustment circuit configured to output a switching voltage to the switching element; a first control circuit electrically connected to the adjustment circuit; a PWM control circuit electrically connected to the first control circuit and configured to provide a first control signal to the first control circuit; and a second control circuit electrically connected to the first control circuit and configured to receive a second control signal, wherein... When the first control signal is low and the second control signal is high, the switching voltage is at a low potential; when both the first and second control signals are low, the switching voltage is at a first high potential; when the first control signal is high, the switching voltage is at a second high potential, wherein the low potential is less than the first high potential, and the first high potential is less than the second high potential; when the second control signal is low and the first control signal is in PWM mode switching between the high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in the PWM mode.

5. The active gate driver as claimed in claim 4, wherein the adjustment circuitry is configured to adjust a drive voltage received at its input terminal to the switching voltage; when the first control signal is at the low level and the second control signal is at the high level, the input terminal is electrically connected to a first potential point via the first control circuit and the second control circuit, so that the drive voltage is at the first potential; when both the first control signal and the second control signal are at the low level, the input terminal is electrically connected to a second potential point via the first control circuit and the second control circuit, so that the drive voltage is at the second potential; when the first control signal is at the high level, the input terminal is electrically connected to a third potential point via the first control circuit, so that the drive voltage is at the third potential; the first potential is less than the second potential, and the second potential is less than the third potential.

6. The active gate driver as claimed in claim 5, wherein the first control circuit includes a first switch and a second switch, and the second control circuit includes a third switch and a fourth switch; the third switch and the fourth switch are connected in series between the second potential point and the first potential point, and when the second control signal is at the high level, the third switch and the fourth switch are respectively turned off and turned on, and when the second control signal is at the low level, the third switch and the fourth switch are respectively turned on and turned off; the first switch and the second switch are connected in series between the third potential point and the connection point of the third switch and the fourth switch, and when the first control signal is at the high level, the first switch and the second switch are respectively turned on and turned off, and when the first control signal is at the low level, the first switch and the second switch are respectively turned off and turned on.

7. An active gate driver suitable for a switching element, comprising: an adjustment circuit configured to output a switching voltage to the switching element; a first control circuit electrically connected to the adjustment circuit; a PWM control circuit electrically connected to the first control circuit and configured to provide a first control signal to the first control circuit; and a second control circuit electrically connected to the first control circuit and configured to receive a second control signal, wherein... When the first control signal is high and the second control signal is low, the switching voltage is at a low potential; when both the first and second control signals are high, the switching voltage is at a first high potential; when the first control signal is low, the switching voltage is at a second high potential, wherein the low potential is less than the first high potential, and the first high potential is less than the second high potential; when the second control signal is high and the first control signal is in PWM mode switching between the high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in the PWM mode.

8. The active gate driver as claimed in claim 7, wherein the adjustment circuitry is configured to adjust a drive voltage received at its input to the switching voltage; when the first control signal is at the high level and the second control signal is at the low level, the input is electrically connected to a first potential point via the first control circuit and the second control circuit, so that the drive voltage is at the first potential; when both the first control signal and the second control signal are at the high level, the input is electrically connected to a second potential point via the first control circuit and the second control circuit, so that the drive voltage is at the second potential; when the first control signal is at the low level, the input is electrically connected to a third potential point via the first control circuit, so that the drive voltage is at the third potential; the first potential is less than the second potential, and the second potential is less than the third potential.

9. The active gate driver as claimed in claim 8, wherein the first control circuit includes a first switch and a second switch, and the second control circuit includes a third switch and a fourth switch; the third switch and the fourth switch are connected in series between the second potential point and the first potential point, and when the second control signal is at the high level, the third switch and the fourth switch are turned on and off respectively, and when the second control signal is at the low level, the third switch and the fourth switch are turned off and on respectively; the first switch and the second switch are connected in series between the third potential point and the connection point of the third switch and the fourth switch, and when the first control signal is at the high level, the first switch and the second switch are turned off and on respectively, and when the first control signal is at the low level, the first switch and the second switch are turned on and off respectively.

10. An active gate driver suitable for a switching element, comprising: an adjustment circuit configured to output a switching voltage to the switching element; a first control circuit electrically connected to the adjustment circuit; a PWM control circuit electrically connected to the first control circuit and configured to provide a first control signal to the first control circuit; and a second control circuit electrically connected to the first control circuit and configured to receive a second control signal, wherein... When both the first control signal and the second control signal are high, the switching voltage is low; when the first control signal is high and the second control signal is low, the switching voltage is first high; when the first control signal is low, the switching voltage is second high, wherein the low potential is less than the first high potential and the first high potential is less than the second high potential; when the second control signal is low and the first control signal is in PWM mode switching between the high and low levels, the switching voltage rises, wherein the rate of rise of the switching voltage depends on the duty cycle of the first control signal in the PWM mode.

11. The active gate driver as claimed in claim 10, wherein the adjustment circuitry is configured to adjust a drive voltage received at its input to the switching voltage; when both the first control signal and the second control signal are at the high level, the input is electrically connected to a first potential point via the first control circuit and the second control circuit, such that the drive voltage is at the first potential; when the first control signal is at the high level and the second control signal is at the low level, the input is electrically connected to a second potential point via the first control circuit and the second control circuit, such that the drive voltage is at the second potential; when the first control signal is at the low level, the input is electrically connected to a third potential point via the first control circuit, such that the drive voltage is at the third potential; the first potential is less than the second potential, and the second potential is less than the third potential.

12. The active gate driver as claimed in claim 11, wherein the first control circuit includes a first switch and a second switch, and the second control circuit includes a third switch and a fourth switch; the third switch and the fourth switch are connected in series between the second potential point and the first potential point, wherein when the second control signal is at the high level, the third switch and the fourth switch are respectively turned off and turned on, and when the second control signal is at the low level, the third switch and the fourth switch are respectively turned on and turned off; the first switch and the second switch are connected in series between the third potential point and the connection point of the third switch and the fourth switch, wherein when the first control signal is at the high level, the first switch and the second switch are respectively turned off and turned on, and when the first control signal is at the low level, the first switch and the second switch are respectively turned on and turned off.

13. The active gate driver as described in claim 1, 4, 7 or 10, wherein the first control signal has a switching frequency in the MHz range when in the PWM state.

14. The active gate driver as claimed in claims 3, 6, 9 or 12, wherein the first control circuit includes an isolation unit, a first drive unit and a second drive unit, the isolation unit receiving the first control signal and converting the first control signal into a drive signal, the first drive unit being electrically connected between the isolation unit and the first switch and configured to receive the drive signal and drive the first switch according to the drive signal, and the second drive unit being electrically connected between the isolation unit and the second switch and configured to receive the drive signal and drive the second switch according to the drive signal.

15. The active gate driver as claimed in claim 14, wherein the isolation unit, the first drive unit, and the second drive unit have operating frequencies in the MHz range.

16. The active gate driver as claimed in claim 14, wherein the first drive unit includes a buffer or an inverter electrically connected between the isolation unit and the first switch, and the second drive unit includes a buffer or an inverter electrically connected between the isolation unit and the second switch.

17. The active gate driver as claimed in claims 3, 6, 9 or 12, wherein the second control circuit includes an isolation unit, a first drive unit and a second drive unit, the isolation unit receiving the second control signal and converting the second control signal into a drive signal, the first drive unit being electrically connected between the isolation unit and the third switch and configured to receive the drive signal and drive the third switch according to the drive signal, and the second drive unit being electrically connected between the isolation unit and the fourth switch and configured to receive the drive signal and drive the fourth switch according to the drive signal.

18. The active gate driver as claimed in claim 17, wherein the first drive unit includes a buffer or an inverter electrically connected between the isolation unit and the third switch, and the second drive unit includes a buffer or an inverter electrically connected between the isolation unit and the fourth switch.

19. The active gate driver as described in claim 1, 4, 7 or 10, wherein the first control signal has different duty cycles at different time periods in the PWM state.

20. The active gate driver as claimed in claim 1, 4, 7 or 10, wherein the switching element comprises a silicon carbide metal oxide semiconductor field-effect transistor, and the switching voltage is the gate-source voltage of the switching element.

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