Expandable load board
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- ADVANCED SEMICON ENG INC
- Filing Date
- 2026-01-09
- Publication Date
- 2026-08-01
Smart Images

Figure TWG2TB001904365_001 
Figure TWG2TB001904365_002 
Figure TWG2TB001904365_003
Abstract
Claims
1. An expandable test carrier board, comprising: a printed circuit board motherboard having an integrated circuit module area and a peripheral area surrounding the integrated circuit module area; a first printed circuit board daughterboard having a first internal area and a first external area adjacent to the first internal area, and including a plurality of first connectors located in the first external area; and a plurality of first electrical connections located between the printed circuit board motherboard and the first printed circuit board daughterboard, wherein the peripheral area partially overlaps the first internal area, wherein the first connectors electrically connect the first printed circuit board daughterboard and the printed circuit board motherboard via the first electrical connections.
2. The expandable test carrier as described in claim 1, wherein each of the first electrical connections is a pogo block.
3. The expandable test substrate as described in claim 1, wherein each of the first electrical connections is a conductive adhesive.
4. The expandable test substrate as described in claim 1, wherein the first connectors are arranged in an array and the number of the first connectors is 6 to 18.
5. The expandable test substrate as described in claim 1, wherein three of the first connectors are electrically connected to one of the first electrical connections.
6. The expandable test substrate as described in claim 1, wherein the first electrical connections are secured between the printed circuit motherboard and the first printed circuit daughterboard by a plurality of fasteners.
7. The expandable test substrate as claimed in claim 1 further comprises: a second printed circuit board having a second internal region and a second external region adjacent to the second internal region, wherein the second printed circuit board is separate from the first printed circuit board, the second printed circuit board including a plurality of second connectors located in the second external region; and a plurality of second electrical connections located between the printed circuit motherboard and the second printed circuit board, with the peripheral region partially overlapping the second internal region, wherein the second connectors are electrically connected to the second printed circuit board and the printed circuit motherboard via the second electrical connections.
8. The expandable test substrate as claimed in claim 7 further comprises: a third printed circuit board having a third internal region and a third external region adjacent to the third internal region, wherein the third printed circuit board is separate from the first printed circuit board and the second printed circuit board, the third printed circuit board including a plurality of third connectors located in the third external region; and a plurality of third electrical connections located between the printed circuit motherboard and the third printed circuit board, with the peripheral region partially overlapping the third internal region, wherein the third connectors are electrically connected to the third printed circuit board and the printed circuit motherboard via the third electrical connections.
9. The expandable test substrate as claimed in claim 8 further comprises: a fourth printed circuit board having a fourth internal region and a fourth external region adjacent to the fourth internal region, wherein the fourth printed circuit board is separate from the first printed circuit board, the second printed circuit board and the third printed circuit board, the fourth printed circuit board including a plurality of fourth connectors located in the fourth external region; and a plurality of fourth electrical connections located between the printed circuit motherboard and the fourth printed circuit board, with the peripheral region partially overlapping the fourth internal region, wherein the fourth connectors are electrically connected to the fourth printed circuit board and the printed circuit motherboard via the fourth electrical connections.
10. The expandable test substrate as claimed in claim 9, wherein the peripheral region of the printed circuit board has a first side, a second side, a third side and a fourth side, the first side being opposite to the third side and the second side being opposite to the fourth side; and wherein the first printed circuit sub-board is located on the first side, the second printed circuit sub-board is located on the second side, the third printed circuit sub-board is located on the third side, and the fourth printed circuit sub-board is located on the fourth side.