Semiconductor package structure

Abstract

A semiconductor package structure includes a substrate, electronic components, a heat dissipation channel, a computing module, and a heat sink. The substrate has a planar surface. The electronic components are embedded in the substrate. The heat dissipation channel is embedded in the substrate and thermally coupled to the electronic components. The computing module is stacked above the substrate along the normal direction of the planar surface. The heat sink is stacked above the substrate along the normal direction and is separated from the computing module, wherein the heat dissipation channel extends to the upper surface of the substrate and is thermally coupled to the heat sink.

Claims

1. A semiconductor package structure comprising: a substrate having a planar surface; an electronic component embedded in the substrate; a heat dissipation channel embedded in the substrate and thermally coupled to the electronic component; a computing module stacked above the substrate along a normal direction of the planar surface; and a heat sink stacked above the substrate along the normal direction and separated from the computing module, wherein the heat dissipation channel extends to an upper surface of the substrate and thermally coupled to the heat sink.

2. The semiconductor package structure as described in claim 1, wherein the heat sink has an H-type, Y-type, or I-type cross-section.

3. The semiconductor package structure as described in claim 1, wherein the heat sink extends along the plane.

4. The semiconductor package structure as described in claim 1 further includes: an upper redistribution layer disposed between the substrate and the computing module, and electrically connecting the electronic component and the computing module, wherein the heat dissipation channel extends into the upper redistribution layer.

5. The semiconductor package structure as described in claim 4, wherein a portion of the heat sink is embedded in the upper redistribution layer, and another portion of the heat sink protrudes from an upper surface of the upper redistribution layer.

6. The semiconductor package structure as described in claim 1, wherein a portion of the heat dissipation channel is located below the heat sink.

7. The semiconductor package structure as described in claim 1 further includes: a heat sink disposed on the computing module and thermally coupled to the computing module.

8. The semiconductor package structure as described in claim 7, wherein the heat sink includes a lateral extension and a longitudinal extension connected to the lateral extension, the lateral extension being thermally coupled to the computing module, and the longitudinal extension being thermally coupled to the heat sink.

9. The semiconductor package structure as claimed in claim 7, wherein a distance from a lower surface of the substrate to an upper surface of the heat sink is greater than a distance from the lower surface of the substrate to an upper surface of the heat sink.

10. The semiconductor package structure as claimed in claim 1, further comprising: a lower redistribution layer stacked below the substrate along the normal direction and electrically connected to the electronic component and the computing module; a plurality of solders stacked below the lower redistribution layer along the normal direction and electrically connected to the lower redistribution layer; and a circuit board stacked below the solders along the normal direction and electrically connected to the solders.

11. The semiconductor package structure as described in claim 1, wherein the electronic component is a capacitor.

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