Semiconductor packaging

Abstract

A semiconductor package includes a circuit component and a molding compound. The molding compound encapsulates the circuit component and has a top surface corresponding to the height direction of the circuit component and a plurality of side surfaces surrounding the top surface. The surface roughness of the top surface, at least in a localized area, is greater than the surface roughness of the side surfaces. This semiconductor package, by balancing the flow rate difference of the colloid between the upper and lower surfaces, achieves a lower rate of void formation, thereby improving the overall reliability and heat dissipation performance of the semiconductor package.

Claims

1. A semiconductor package, comprising: A circuit component; And a molding part covering the circuit assembly, the molding part having a top surface corresponding to the height direction of the circuit assembly and a plurality of side surfaces surrounding the top surface, wherein the surface roughness of at least a local area of ​​the top surface is greater than the surface roughness of the plurality of side surfaces.

2. The semiconductor package as described in claim 1, wherein the surface roughness of different regions of the top surface has a phased variation.

3. The semiconductor package as claimed in claim 2, wherein the surface roughness of different regions of the top surface corresponds to the distance from the upper surface of the circuit assembly to the top surface.

4. The semiconductor package as claimed in claim 3, wherein a region having the maximum distance from the upper surface of the circuit assembly to the top surface has the maximum surface roughness.

5. The semiconductor package as claimed in claim 1, wherein the local region corresponds to a boundary where the distance from the upper surface of the circuit assembly to the top surface changes.

6. The semiconductor package as claimed in claim 1, wherein the surface roughness of the upper surface with the highest height of the circuit assembly is greater than the surface roughness of the remaining upper surfaces.

7. The semiconductor package as claimed in claim 1, wherein the circuit assembly includes: a substrate, at least one semiconductor wafer and at least one wire, the at least one semiconductor wafer being disposed on the substrate and the at least one wire connecting the at least one semiconductor wafer and the substrate.

8. The semiconductor package as described in claim 7, wherein the wire diameter is greater than or equal to 14 metric wires.

9. The semiconductor package as described in claim 7, wherein the substrate is a ceramic substrate.

10. The semiconductor package as claimed in claim 1 further includes a printed circuit board and a bonding layer disposed on the top surface to connect the molded part and the printed circuit board.

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