M.2 interface solid-state drive
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- SILICON POWER
- Filing Date
- 2026-03-27
- Publication Date
- 2026-08-01
Smart Images

Figure TWG2TB001904492_001 
Figure TWG2TB001904492_002
Abstract
Claims
1. An M.2 interface solid-state drive, comprising: a gold finger connector for inserting into an M.2 slot on a motherboard, and including a plurality of gold finger pins, the gold finger pins including at least one undefined pin; a controller electrically connected to the gold finger connector and configured to communicate with a host via the M.2 slot; a non-volatile memory module electrically connected to the controller; and a management circuit structure electrically connected between the at least one undefined pin of the gold finger connector and a general-purpose input / output contact of the controller, and configured to, when the undefined pin presents a predetermined electrical state, trigger the controller to enter a management mode via the general-purpose input / output contact to change the access control logic of the controller for the non-volatile memory module.
2. The M.2 interface solid-state drive as described in claim 1, wherein, The management state is a write-protected state, and in this write-protected state, the controller is configured to prohibit actual writing to the non-volatile memory module.
3. The M.2 interface solid-state drive as described in claim 2, wherein in the write-protected state, the controller is configured to respond to a write command completion signal from the host.
4. An M.2 interface solid-state drive as described in claim 2, wherein the write protection state is triggered when the predetermined electrical state is grounded.
5. The M.2 interface solid-state drive as described in claim 4, wherein the predetermined electrical state is generated by an external control component by making the undefined pin connected (short-circuited) to a ground pin among the gold finger pins.
6. The M.2 interface solid-state drive as described in claim 2, wherein the undefined pin is pin 48 of the M.2 interface.
7. The M.2 interface solid-state drive as described in claim 1, wherein the management state is a data clearing state, and in the data clearing state, the controller is configured to perform a data clearing operation on the non-volatile memory module.
8. The M.2 interface solid-state drive as described in claim 7, wherein the management circuitry includes a delay circuit or timing element such that the data clearing state is initiated only when the undefined pin is maintained in the predetermined electrical state for a predetermined time.
9. An M.2 interface solid-state drive as described in claim 7, wherein the data clearing state is triggered when the predetermined electrical state is grounded (GND).
10. The M.2 interface solid-state drive as described in claim 9, wherein the predetermined electrical state is generated by an external control component by making the undefined pin connected (short-circuited) to a ground pin among the gold finger pins.
11. The M.2 interface solid-state drive as described in claim 7, wherein the undefined pin is pin 46 of the M.2 interface.
12. The M.2 interface solid-state drive as described in claim 1, wherein the management state is a monitoring state, and in the monitoring state, the controller is configured to provide a monitoring interface for outputting the controller's operating status information via the undefined pin.
13. An M.2 interface solid-state drive as described in claim 12, wherein the monitoring interface is a serial communication interface (such as UART) independent of the PCIe bus.
14. The M.2 interface solid-state drive as described in claim 12, wherein the undefined pin is pin 24 of the M.2 interface.
15. The M.2 interface solid-state drive as described in claim 12, wherein the monitoring interface is further configured to receive control commands from the host via another undefined pin, the control commands including reboot commands, firmware update commands, system parameter adjustment commands, or combinations thereof.
16. The M.2 interface solid-state drive as described in claim 15, wherein the other undefined pin is pin 26 of the M.2 interface.
17. The M.2 interface solid-state drive as described in claim 1, wherein the management circuitry includes at least one impedance element disposed between the gold finger pin and the controller.