Integrated circuit board device with computing and memory expansion capabilities

Abstract

This invention discloses an integrated circuit board device with computing and memory expansion functions, including a circuit board with PCIe gold finger connections, a control chip, an arithmetic chip, a compute high-speed link (CXL) chip, and at least one memory module disposed on the circuit board. The control chip is electrically connected to both the arithmetic chip and the CXL chip, and the CXL chip is further electrically connected to the memory module. A data transmission loop is formed through internal wiring on the circuit board, allowing the arithmetic chip to directly access data from the memory module via the control chip and the CXL chip. This integrates computing and memory resources on a single circuit board, reducing data transmission latency, improving bandwidth utilization, and enhancing system expansion flexibility.

Claims

1. An integrated circuit board device with computing and memory expansion functions, comprising: A circuit board having a gold finger connector that conforms to the PCIe (Peripheral Component Interconnect) specification; A control chip is disposed on the circuit board, the control chip having a first port and a plurality of second ports, the first port being electrically connected to the gold finger connector; a computing chip is disposed on the circuit board and electrically connected to one of the second ports of the control chip; a compute high-speed link (CXL) chip is disposed on the circuit board and electrically connected to another second port of the control chip; and at least one memory module is disposed on the circuit board and electrically connected to the compute high-speed link (CXL) chip; wherein the control chip, the computing chip, and the compute high-speed link (CXL) chip form a data transmission loop through internal wiring of the circuit board.

2. The integrated circuit board device as described in claim 1, wherein the computing chip is a graphics processing unit (GPU).

3. The integrated circuit board device as described in claim 1, wherein the Computational High-Speed ​​Link (CXL) chip is a CXL Type 3 memory expansion controller.

4. The integrated circuit board device as claimed in claim 1, wherein the control chip is a PCIe switch that supports the CXL protocol, and the control chip splits the PCIe lanes (Lanes) input from the first port into a plurality of sub-lane groups and allocates them to the computing chip and the computing high-speed link (CXL) chip respectively via the second ports.

5. The integrated circuit board device as claimed in claim 4, wherein the control chip has a peer-to-peer circuit structure that allows data signals between the computing chip and the computing high-speed link (CXL) chip to be exchanged directly without passing through the first port.

6. The integrated circuit board device as claimed in claim 4, wherein the control chip splits the PCIe channel into at least two sub-channel groups, one sub-channel group being allocated to the computing chip and the other sub-channel group being allocated to the computing high-speed link (CXL) chip.

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