Chip bridge package structure

Abstract

A chip bridging package structure includes a substrate, a first circuit layer, an inorganic insulating plate, a first protective layer, a second circuit layer, a second protective layer, a third circuit layer, and two chips. The substrate defines a positioning region and a peripheral region. The inorganic insulating plate is located at least in the positioning region. The second circuit layer includes bridging lines whose vertical projection corresponds to a portion of the inorganic insulating plate. The third circuit layer includes a first connection portion and a second connection portion. The first connection portion includes a plurality of first connection pads, and the second connection portion includes a plurality of second connection pads. A first spacing between the first connection pads is greater than a second spacing between the second connection pads. Two of the second connection pads are electrically connected to two other second connection pads via the bridging lines. The two chips are electrically connected to each other via the bridging lines.

Claims

1. A chip bridging package structure, comprising: a substrate defining a positioning region and a peripheral region, the peripheral region surrounding the positioning region; a first circuit layer located on an upper surface of the substrate, the first circuit layer including a positioning circuit portion, at least a portion of the positioning circuit portion being located in the positioning region; an inorganic insulating plate located at least in the positioning region, and at least a portion of the inorganic insulating plate being located on the positioning circuit portion; a first protective layer covering the inorganic insulating plate, including a plurality of first through holes, the vertical projection of each first through hole being located in the peripheral region, exposing a portion of the first circuit layer; a second circuit layer located on the first protective layer, including a bridging circuit portion and a serial circuit portion, a portion of the serial circuit portion being filled into the first through hole and connected to the first circuit layer, the vertical projection of the bridging circuit portion corresponding to a portion of the inorganic insulating plate; A second protective layer is located on the second circuit layer and has a plurality of second through holes and a plurality of third through holes. The vertical projection of each second through hole is located in the peripheral area, exposing a portion of the serial circuit portion. The vertical projection of the third through holes is located in the positioning area, exposing a portion of the bridging circuit portion. The diameter of the third through holes is smaller than the diameter of the second through holes. A third circuit layer, located on the second protective layer, includes a first connection portion and a second connection portion. The first connection portion includes a plurality of first connection pads and is connected to the serial circuit portion through a plurality of first metal pillars filled in the second vias. The second connection portion includes a plurality of second connection pads and is connected to the bridging circuit portion through a plurality of second metal pillars filled in the third vias. A first spacing between the first connection pads is greater than a second spacing between the second connection pads. Two of the second connection pads are electrically connected to two other second connection pads through the bridging circuit portion. The second circuit layer also includes two chips, each chip including a plurality of first solder pads and a plurality of second solder pads. The first solder pads are connected to a portion of the first connection pads, and the second solder pads are connected to a portion of the second connection pads. The two chips are electrically connected to each other through the bridging circuit portion.

2. The chip bridging package structure as described in claim 1, wherein the first protective layer includes a first cover layer and a second cover layer, the bridging circuit portion further includes a first bridging channel line, a plurality of first bridging pads and a second bridging channel line, the first cover layer covers the inorganic insulating plate, the first bridging channel line is located on a portion of the first cover layer and its vertical projection corresponds to a portion of the inorganic insulating plate, the second cover layer covers the first bridging channel line and the first cover layer, and has a plurality of fourth vias to expose a portion of the first bridging channel line, the first bridging pads and the second bridging channel line are located on the second cover layer, at least two of the first bridging pads are filled into the fourth vias and electrically connected to each other through the first bridging channel line, and at least two of the second connecting pads are electrically connected to each other through the second bridging channel line in the third vias.

3. The chip bridging package structure as described in claim 1 further includes a bridging element comprising a bridging body, a first bridging metal segment, a second bridging metal segment, a plurality of bridging vias, and a plurality of second bridging pads. The first bridging metal segment and the second bridging metal segment are located in the bridging body and are not connected to each other. The bridging vias extend from a surface of the bridging body to the first bridging metal segment or the second bridging metal segment. The second bridging pads are located on the surface of the bridging body, and at least two of the second bridging pads are filled into the bridging vias and connected to the first bridging metal segment. At least two other second bridging pads are filled into the bridging vias and connected to the second bridging metal segment. The first protective layer further includes a plurality of fifth vias, each of the fifth vias corresponding to one of the second bridging pads. A portion of the bridging circuit portion is filled into the fifth via and connected to the second bridging pads.

4. The chip bridging package structure as described in claim 3, wherein the bridging element is disposed on the inorganic insulating board and is covered by the first protective layer.

5. The wafer bridging package structure as described in claim 3, wherein the inorganic insulating plate further includes a positioning groove in which the bridging element is mounted.

6. The chip bridging package structure as described in either claim 4 or claim 5, wherein the inorganic insulating plate has a plurality of sixth through holes in a portion of the positioning region and the peripheral region, the sixth through holes corresponding to the first through holes respectively, and the second circuit layer is filled in the sixth through holes.

7. The chip bridging package structure as described in claim 6, wherein the peripheral region of the substrate is further provided with a plurality of substrate vias, the substrate vias respectively corresponding to the sixth vias, and the chip bridging package structure further includes a redistribution circuit layer, the redistribution circuit layer being filled in the substrate vias and electrically connected to the second circuit layer.

8. The chip bridging package structure as claimed in claim 1, wherein the peripheral region of the substrate is further provided with a plurality of substrate vias, the substrate vias respectively corresponding to the first vias, and the chip bridging package structure further includes a redistribution circuit layer, the redistribution circuit layer being filled in the substrate vias and electrically connected to the second circuit layer.

9. The chip bridging package structure as described in claim 8, wherein the redistribution line layer includes a connection channel portion such that two of the first connection pads are electrically connected to each other.

10. The chip bridging package structure as described in claim 1, wherein the width of the first connection pads is greater than the width of the second connection pads.

11. The wafer bridging package structure as claimed in claim 1, wherein the width of the first connection pads is from 5 μm to 50 μm and the width of the second connection pads is from 0.5 μm to 20 μm.

12. The wafer bridging package structure as described in claim 11, wherein the width of the first connection pads is 8 μm to 20 μm and the width of the second connection pads is 1 μm to 5 μm.

13. The wafer bridging package structure as described in claim 1, wherein the first pitch ranges from 5 μm to 50 μm and the second pitch ranges from 0.5 μm to 20 μm.

14. The wafer bridging package structure as described in claim 13, wherein the first pitch ranges from 8 μm to 20 μm and the second pitch ranges from 1 μm to 5 μm.

15. The chip bridging package structure as claimed in claim 1, wherein a solder resist layer is provided between the first connection pads, between the second connection pads, and between the first connection pads and the second connection pads.

16. The chip bridging package structure as described in claim 1, wherein the inorganic insulating plate is selected from the group consisting of a ceramic plate, a glass plate, and a quartz plate.

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