Substrate with via stub

TWM686878UActive Publication Date: 2026-09-01IND TECH RES INST
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Patent Information

Application Number
TW114213078
Authority / Receiving Office
TW · TW
Patent Type
Utility models
Current Assignee / Owner
Filing Date
2025-12-09
Publication Date
2026-09-01
Estimated Expiration
2035-12-08

Smart Images

  • Figure TWG2TB001909155_001
    Figure TWG2TB001909155_001
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    Figure TWG2TB001909155_002
  • Figure TWG2TB001909155_003
    Figure TWG2TB001909155_003
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Abstract

A substrate with via fragments includes a first trace, a second trace, a through-hole, and a third trace. The first trace is located on a first layer of the substrate. The second trace is located on a second layer of the substrate. The through-hole penetrates the substrate and includes interconnected via fragments and transmission portions. Signals are transmitted from the first trace to the second trace via the transmission portion. The third trace is electrically connected to the through-hole, and the signal generated by the third trace cancels out the signal generated by the via fragments.
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Claims

1. A substrate having at least one via fragment, comprising: at least one first trace located on a first layer of the substrate; at least one second trace located on a second layer of the substrate; at least one via penetrating the substrate and including the at least one via fragment and at least one transmission portion interconnected therewith, a signal being transmitted from the at least one first trace through the at least one transmission portion to the at least one second trace; and at least one third trace electrically connected to the at least one via fragment, wherein the signal generated by the at least one third trace cancels out the signal generated by the at least one via fragment.

2. The substrate as claimed in claim 1, wherein the at least one via is two vias, the at least one third trace is two third traces, and the two third traces are symmetrically arranged with respect to each other.

3. The substrate as claimed in claim 1, wherein the at least one third trace is an open circuit structure.

4. The substrate as claimed in claim 1, wherein the at least one third trace is one of a single-ended transmission line, a differential transmission line, a single-ended coupled line, or a multi-segment cascaded transmission line.

5. The substrate as claimed in claim 1, wherein the at least one third trace is parallel to the at least one first trace and the at least one second trace.

6. The substrate as claimed in claim 5, wherein the at least one third trace and the at least one first trace are both located in the first layer.

7. The substrate as claimed in claim 5, wherein the at least one third trace is located in a third layer of the substrate, and the third layer is located in a different layer from the first layer and the second layer.

8. The substrate as claimed in claim 1, wherein the at least one third trace is in one of the following shapes: L-shaped, T-shaped, fan-shaped, circular, conical, trapezoidal, curved, or serrated.

9. The substrate as claimed in claim 1, wherein the at least one third trace has a first segment, a second segment, a third segment and a fourth segment connected in sequence, the two ends of the first segment being connected to the through hole and the second segment respectively, the first segment and the second segment being connected in parallel, the second segment being connected perpendicularly to the third segment, and the third segment being connected perpendicularly to the fourth segment, so that the third trace is U-shaped.

10. The substrate of claim 1, wherein the at least one third trace has a first segment, a second segment, a third segment and a fourth segment connected in sequence, the two ends of the first segment being connected to the through hole and the second segment respectively, the first segment and the second segment being vertically connected, the second segment being vertically connected to the third segment, and the third segment being vertically connected to the fourth segment, so that the third trace is hook-shaped.

11. The substrate as claimed in claim 1, wherein the length of the at least one third trace is less than the length of the at least one via fragment.

12. The substrate as claimed in claim 1, wherein the signal generated by the at least one third trace relates to the length of the at least one third trace and the width of the at least one third trace.

13. The substrate as claimed in claim 12, wherein the length of the at least one third trace is related to a length of the at least one via fragment, an operating frequency, a dielectric constant of the substrate, an admittance value of the at least one via fragment, and an admittance value of the at least one third trace.

14. The substrate as claimed in claim 12, wherein the width of the at least one third trace is related to an admittance value of the at least one via fragment and an admittance value of the at least one third trace.

15. The substrate as claimed in claim 1, wherein the at least one first trace, the at least one second trace, the at least one third trace, and the at least one via form an equalizer.

16. The substrate as claimed in claim 1, further comprising an empty solder pad, wherein the signal generated by the empty solder pad and the signal generated by the at least one third trace cancel each other out.