LED display driver IC

Abstract

A display light-emitting diode (LED) driver chip, particularly a control circuit for operating a display device with an LED matrix, includes a scan driver and a data driver, and operates synchronously with a pulse width modulation (PWM) clock. The control circuit employs a dual phase-locked loop (PLL) architecture to pre-configure the PWM clock corresponding to the subsequent display frame during the current display frame, thereby achieving lock-out delay-free clock switching during frame transitions and improving display stability.

Claims

1. A display light-emitting diode driving chip, comprising: A scan driver, coupled to a light-emitting diode (LED) array, is configured to provide multiple scan line signals to multiple columns of the LED array, wherein the scan line signals are used to select one column of the LED array to be activated; a data driver, coupled to the LED array, is configured to provide multiple current control data signals to multiple rows of the LED array, wherein the current control data signals provide pulse-width modulated (PWM) current outputs to control the brightness of the LED array; and a clock management module, coupled to the scan driver and the data driver, the clock management module including a first clock generator and a second clock generator, the first clock generator and the second clock generator respectively including a first phase-locked loop (PLL) and a second PLL, wherein the first clock generator is used to configure the PWM clock frequency of a current display screen, and the second clock generator is used to pre-configure the PWM clock frequency of a subsequent display screen.

2. A display light-emitting diode driving chip, comprising: A scan driver coupled to a light-emitting diode (LED) array, the scan driver being configured to provide multiple scan line signals to multiple columns of the LED array, wherein the scan line signals are used to select one column of the LED array to be activated; and a data driver coupled to the LED array, the data driver being configured to provide multiple current control data signals to multiple rows of the LED array, wherein the current control data signals provide pulse-width modulated current outputs to control the brightness of the LED array; and a clock management module coupled to the scan driver and the data driver, the clock management module including a first clock generator and a second clock generator, the first clock generator and the second clock generator respectively including a first phase-locked loop (PLL) and a second PLL; During the (n)th display screen, one of the first phase-locked loop and the second phase-locked loop is configured to generate the (n+1)th PWM clock frequency allocated to the (n+1)th display screen, while the other is configured to generate the (n)th PWM clock frequency allocated to the (n)th display screen.

3. The driver chip as claimed in claim 1 or 2, wherein the light-emitting diode array comprises a plurality of pixels consisting of a plurality of columns and a plurality of rows, and each pixel comprises a light-emitting element.

4. The driver chip as described in claim 1 or 2, wherein the scan driver and the data driver are both configured to operate synchronously with the frequency of the (n)th PWM clock provided by the first clock generator during the (n)th display screen.

5. The driver chip as described in claim 1, wherein the second clock generator pre-configures the PWM clock frequency of the subsequent display screen before the subsequent display screen, so that the pre-configured PWM clock frequency can be used when switching to the subsequent display screen without causing a frequency switching delay.

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