Memory module layout

Abstract

A partially laid-out memory module includes: a circuit board having multiple sub-channels and a plurality of memory chip mounting areas; a plurality of memory chips disposed in a first portion of the chip mounting areas, and a second portion of the chip mounting areas without memory chips; and a sequence presence detection device storing a physical component location identification code to indicate the first portion of the chip mounting areas containing memory chips, allowing the host to read and identify the sub-channels corresponding to the first portion as valid sub-channels, and avoiding memory mapping for the sub-channels corresponding to the second portion. Thus, the partially laid-out memory module can maintain the use of existing circuit board designs while configuring a smaller number of memory chips and can maintain normal operation under different mechanisms in different platform environments.

Claims

1. A memory module with a partial layout, comprising: a circuit board having multiple sub-channels and a plurality of chip mounting areas, wherein the plurality of sub-channels of the multiple sub-channels correspond one-to-one with the plurality of chip mounting areas; a plurality of memory chips disposed in a first portion of the plurality of chip mounting areas, wherein a second portion of the plurality of chip mounting areas is free of the memory chips, and the first portion and the second portion do not overlap; and a sequence presence detection device disposed on the circuit board, the sequence presence detection device storing a physical component position identification code, the physical component position identification code being used to indicate the first portion of the plurality of chip mounting areas containing the plurality of memory chips, for a host to read and identify at least one sub-channel corresponding to the first portion of the plurality of chip mounting areas as a valid sub-channel, and to avoid performing memory mapping for at least one sub-channel corresponding to the second portion of the plurality of chip mounting areas.

2. The memory module with partial layout as requested in claim 1, wherein the multiple sub-channels are dual sub-channels and have two sub-channels, and a plurality of memory chips are disposed in one of the chip mounting areas, while the other chip mounting area is without memory chips.

3. A memory module with a partial layout as described in claim 1, wherein the multiple subchannels have at least three of the subchannels, and at least one of the first portion and the second portion corresponds to at least two of the subchannels.

4. The memory module with partial layout as requested in Request 1, wherein the physical component location identification code is used by the host to disable the sub-channel interleaved access function.

5. The memory module with partial layout as requested in Request 1, wherein the physical component location identification code is used by the host to dynamically load corresponding asymmetric signal training parameters based on the chip mounting area having a plurality of memory chips.

6. The memory module with a partial layout as described in Request 2, wherein the plurality of memory chips is four memory chips and each memory chip has a bit width of eight bits.

7. The memory module with partial layout as requested in Request 1, wherein the sequence exists and the detection device instructs the host to read the memory reference code corresponding to the physical component location identification code, so that the host can perform dynamic signal compensation on the multi-sub-channel when performing memory training.

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