Low-latency transaction risk control system with hardware and software co-correction

Abstract

This invention provides a low-latency transaction risk control system with hardware and software co-correction, installed in at least one electronic device and electrically connected to a brokerage host and a stock exchange server host. It includes an FPGA transaction verification module and an RM synchronization correction module. The FPGA transaction verification module is electrically connected to the RM synchronization correction module and receives an order message from the brokerage host. It performs a preliminary verification based on at least one verification condition and generates a preliminary verification message. The RM synchronization correction module receives the preliminary verification message and multiple transaction-related data, calculates a deductible order amount based on at least one limit condition and a cross-matrix limit calculation model, and generates a review judgment result. When the review judgment result is inconsistent with the preliminary verification message, it generates correction data and transmits it to the FPGA transaction verification module to update the verification status and determine the processing action for the order message.

Claims

1. A low-latency trading risk control system with hardware and software co-correction, installed in at least one electronic device and electrically connected to a brokerage host and a stock exchange server, for performing risk checks and control on at least one order message before execution of a transaction, comprising: an FPGA (Field Programmable Gate Array) trading check module, equipped with at least one check condition, for checking the order message according to the check condition when receiving the at least one order message from the brokerage host during securities trading hours, and generating a corresponding preliminary check message; and an RM (Risk Management Unit). The risk management synchronous correction module is equipped with at least one limit condition and a cross-matrix limit calculation model, and is electrically connected to the FPGA transaction verification module to receive the preliminary verification message. Before the securities trading session, the RM synchronous correction module receives multiple transaction-related data from the brokerage host, and during the securities trading session, it synchronously receives the order message, uses the transaction-related data to execute the cross-matrix limit calculation model to calculate the deductible order limit for the corresponding order message, and determines the review judgment result for the corresponding order message based on the deductible order limit and the limit condition. When the review judgment result is inconsistent with the preliminary verification message, the RM synchronous correction module generates correction data and transmits it to the FPGA transaction verification module, so that the FPGA transaction verification module dynamically updates its internal verification status and determines the subsequent handling action of the order message, such as sending the order message to the stock exchange server host, or issuing a warning, rejecting, filtering, or deleting the order message.

2. The low-latency transaction risk control system as described in claim 1, wherein, The transaction-related data includes at least one account limit data, one inventory data, one buy order data, one sell order data, one completed buy data, and one completed sell data. The inventory data includes yesterday's remaining inventory data and one available-for-sale inventory data. The cross-matrix limit calculation model uses a multi-dimensional offset logic to cross-compare the order positions of the buy order data and the sell order data, the transaction positions of the completed buy data and the completed sell data, and one offset inventory position defined by yesterday's remaining inventory data and the available-for-sale inventory data. The model then sums up the risk exposure values ​​of completed but unoffset and unexecuted orders in the transaction positions of the completed sell data in real time to determine the deductible order limit.

3. The low-latency transaction risk control system as described in claim 1, wherein, The verification criteria include at least one of the following: whitelist of order accounts, blacklist and whitelist of trading targets, whether market orders are allowed, control over order frequency, control over single transaction amount, control over entrusted amount, control over sellable inventory, and control over firewall whitelist. The preliminary verification information includes at least one of the following: verification record, error code, order record, and transaction record. The limit conditions include at least one of the following: single order amount limit, single order number limit, entrusted limit, related account combined limit, available credit limit, and profit and loss warning threshold.

4. The low-latency transaction risk control system as described in claim 3, wherein, When the order message is a modification message, the RM synchronous correction module compares the corresponding deductible order amount before and after the modification, and generates correction data when there is a difference between the two and transmits it to the FPGA transaction verification module to correct subsequent processing actions.

5. The low-latency transaction risk control system as described in claim 3, wherein, The FPGA transaction verification module and the RM synchronization correction module exchange data bidirectionally through a PCIe (Peripheral Component Interconnect Express) interface. The FPGA transaction verification module transmits order data, order confirmation data, transaction confirmation data, firewall check records, risk check records, or error codes to the RM synchronization correction module through the PCIe interface, and the RM synchronization correction module transmits a control command to the FPGA transaction verification module through the PCIe interface to perform order filtering, order deletion, or other risk control actions.

6. The low-latency transaction risk control system as described in claim 1, wherein, The RM synchronization correction module targets one of the trading accounts corresponding to the order message and at least one associated account. It counts the number of orders, the number of order cancellations, the transaction amount, the amount of unexecuted orders, the amount of buy orders, the number of completed transactions, or the number of error codes in multiple time windows. The module then compares these counts with the preset upper limit values ​​corresponding to each time window to generate the review and judgment result. The associated account refers to a trading account that is merged with the trading account for risk control based on a pre-established account association relationship.

7. The low-latency transaction risk control system as described in claim 5, wherein, When the RM synchronization correction module determines that a filtering action should be performed, it sends a control command as a yellow light instruction to the FPGA transaction check module, so that the FPGA transaction check module only allows the order message that is a deletion order to pass through; and if the order message that is not a deletion order is still received after a set number of seconds after sending the yellow light instruction, the RM synchronization correction module sends a control command as a red light instruction to the FPGA transaction check module, so that the FPGA transaction check module blocks all order messages corresponding to that transaction account.

8. The low-latency transaction risk control system as described in claim 7, wherein, When the RM synchronization correction module sends the red light command, and after a red light observation period of one second, it still receives order return data or transaction return data from the FPGA transaction verification module, the RM synchronization correction module automatically starts the disable switch ports operation.

9. The low-latency transaction risk control system as described in claim 1, wherein, The order flow per second between the FPGA transaction verification module and the stock exchange server is limited to a first limit, and the order flow per second between the brokerage server and the FPGA transaction verification module is limited to a second limit. When the FPGA transaction verification module performs flow control and causes the order message to remain in the hardware buffer for more than a certain number of seconds, the FPGA transaction verification module actively replies with a rejection message and does not transmit the order message to the stock exchange server.

10. The low-latency transaction risk control system as described in claim 1, wherein, After the securities trading session, the RM synchronization correction module receives the final processing actions generated by the FPGA transaction verification module for each order message during the securities trading session, and compares each processing action with the review judgment results generated by the RM synchronization correction module for each order message to perform post-market audit.

Images