Fan-out chip packaging module
Patent Information
- Application Number
- TW115201919
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- Filing Date
- 2026-03-05
- Publication Date
- 2026-09-11
- Estimated Expiration
- 2036-03-04
Smart Images

Figure 00000000_0000_ABST
Abstract
Claims
1. A fan-out chip packaging module, comprising: a reinforcement unit including a reinforcement layer having a plurality of through vias; an adhesive layer disposed on a surface of the reinforcement layer; a redistribution layer unit bonded to the adhesive layer and including a redistribution stack and a plurality of solder pads, wherein the side of the redistribution stack bonded to the adhesive layer is electrically connected to the reinforcement unit, and the solder pads are disposed on the side of the redistribution stack facing away from the adhesive layer; a first electronic component bonded to a first portion of the solder pads; an underfill covering a bottom of the first electronic component and the first portion of the solder pads; and an encapsulating adhesive covering the redistribution layer unit to encapsulate the first electronic component and the underfill, the encapsulating adhesive including a groove recessed from the side of the encapsulating adhesive away from the solder pads toward a second portion of the solder pads and exposing the second portion of the solder pads.
2. The fan-out wafer package module as described in claim 1, wherein, The area of the reinforcement layer is equal to the area of the redistribution stack.
3. The fan-out wafer package module as described in claim 1, wherein, The area of the reinforcement layer is larger than the area of the redistribution overlay.
4. The fan-out wafer package module as described in claim 3, wherein, The area of the adhesive layer is larger than the area of the rewiring overlay.
5. The fan-out wafer package module as described in claim 1, wherein, The area of the rewiring overlay is larger than the area of the reinforcement layer.
6. The fan-out wafer package module as described in claim 5, wherein, The area of the adhesive layer is larger than the area of the reinforcing layer.
7. The fan-out wafer package module as claimed in claim 5 further includes a circuit board located on the side of the reinforcement layer opposite to the redistribution stack and bonded to the reinforcement unit, and the area of the circuit board is larger than the area of the redistribution stack.
8. The fan-out wafer package module as claimed in claim 7 further includes a second electronic component located below the redistribution stack, and at least a portion of the second electronic component does not overlap with the redistribution stack in the vertical direction.
9. The fan-out wafer package module as described in claim 1, wherein, The sealing adhesive also recesses from the side away from the first electronic component toward the first electronic component to expose the second portion of the solder block within the groove.
10. The fan-out wafer package module as described in claim 1, wherein, The first electronic component is selected from a system-on-a-chip (SoC) or an application-specific integrated circuit (ASIC) chip.