wafer carrier

Abstract

A wafer carrier includes a loading area and a peripheral area. The loading area includes a plurality of wafer loading sections arranged in an array, each wafer loading section including a plurality of copper pillars with a height of 90 to 200 μm and an allowable height difference of 8 to 20 μm between the copper pillars. The peripheral area is located at the periphery of the loading area and includes a plurality of copper auxiliary components, each copper auxiliary component being adjacent to the side edge of one of the wafer loading sections located in a corner of the loading area. By using a dry film design during electroplating to simultaneously form copper auxiliary components at the periphery of the wafer loading sections located in the corners of the loading area, it helps to uniformize the current density of the wafer loading sections, thereby maintaining the uniformity of the height difference of the copper pillars inside as their height increases, thus avoiding problems such as open solder joints during packaging.

Claims

1. A wafer carrier comprising: a loading region including a plurality of wafer loading portions arranged in an array, wherein each wafer loading portion includes a plurality of copper pillars, wherein the height of the copper pillars is 90 to 200 μm and the allowable height difference between the copper pillars is 8 to 20 μm; and a peripheral region located at the periphery of the loading region, including a plurality of copper auxiliary members, each copper auxiliary member being adjacent to a side edge of one of the wafer loading portions located at a corner of the loading region.

2. The wafer carrier as claimed in claim 1, wherein the distance from the loading area to an edge of the peripheral area is a first distance, and the distance from the copper auxiliary component to the edge of the peripheral area is a second distance, the second distance being 70% to 85% of the first distance.

3. The wafer carrier as described in claim 2, wherein the second distance is 75% to 82% of the first distance.

4. The wafer carrier as described in claim 1, wherein the copper auxiliary components surround the loading area.

5. The wafer carrier as described in claim 1, wherein each of the copper auxiliary components is a continuous pattern.

6. The wafer substrate as claimed in claim 1, wherein each of the copper auxiliary components is a discontinuous pattern, and each of the copper auxiliary components is formed by arranging a plurality of copper blocks.

7. The wafer carrier as described in claim 1, wherein the height of the copper pillars is 100 to 150 μm.

8. The wafer carrier as described in claim 7, wherein the permissible height difference between the copper pillars is 10 to 15 μm.

9. The wafer substrate as claimed in claim 1, wherein the peripheral region includes a plurality of vacant patterns, at least a portion of the copper auxiliary elements being formed on a portion of the vacant patterns.

10. The wafer carrier as described in claim 1, wherein the height of each of the copper auxiliary components is approximately the same as the height of the copper pillars.

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