Chip structure and multi-chip integrated structure

Abstract

This invention relates to a single-chip, multi-chip integration, fabrication method, chip structure, and chip, belonging to the field of chip technology. It involves fabricating a first set of chip stack structures and a second set of chip stack structures, each set including a first heat sink and a plurality of bare chips fixed to the first heat sink with their backs facing down; fabricating a substrate, the first substrate having a first surface and a second surface, each having connection points and being opposite to each other; and bonding the front connection points of the bare chips in the corresponding chip stack structures to the connection points of the corresponding surfaces of the first substrate, thereby mounting the first set of chip stack structures and the second set of chip stack structures onto the first surface and the second surface respectively to form a multi-chip integrated structure. Embodiments of this invention enable each chip stack structure to dissipate heat through its built-in first heat sink, meeting the heat dissipation requirements of high-performance, high-power, and high-frequency integrated chips.

Claims

1. A wafer structure, comprising: At least two bare wafers, wherein the front side of the bare wafers has a third set of bumps and a fourth set of bumps with a height less than the third set of bumps, and the back side of the bare wafers has a second metal plating layer; a second heat sink, the surface of which has a wafer fixing area formed by a second interface heat dissipation material layer, wherein the at least two bare wafers are fixed in the wafer fixing area with their back sides facing down by bonding through the second interface heat dissipation material layer, wherein the second heat sink is a planar heat sink or a heat sink with grooves, and the surface of the planar heat sink or the surface of the groove is provided with a second metal plating layer, and a wafer fixing area formed by the second interface heat dissipation material layer is provided on the second metal plating layer for each bare wafer; a second connecting wafer, which, after the bare wafers are fixed in the wafer fixing area, flip-bonds the fourth set of bumps of the at least two bare wafers to form a first wafer frame; the height of the second connecting wafer is less than the height difference of the fourth set of bumps of the third set of bumps; a first bottom filling structure formed by bottom filling the first wafer frame; the first bottom filling structure covers the fourth set of bumps. A second substrate, wherein, for the first wafer frame after underfilling, the third set of bumps is flip-chip bonded to the upper surface of the second substrate to form a second wafer frame; a second underfill structure is formed by underfilling the second wafer frame; a first portion of the second underfill structure covers the third set of bumps, and a second portion of the second underfill structure covers the second heat sink and the second substrate; and a contact array package, wherein, for the second wafer frame after underfilling, the contact array package is fabricated on the lower surface of the second substrate.

2. The wafer structure as described in claim 1, wherein, Each chip mounting area has a unique label to identify the coordinates of that chip mounting area on the second heat sink.

3. The wafer structure as described in claim 1, wherein, The second interface heat dissipation material layer is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum, and silver; an alloy of any one of nickel, tin, copper, gold, aluminum, and silver; and graphene.

4. The wafer structure as described in claim 1, wherein, The contact array package includes a ball grid array package (BGA), a planar grid array package (LGA), or a pin grid array package (PGA).

5. A wafer structure corresponding to at least two single wafer products fixed to the same third heat sink, and comprising: A third heat sink, wherein a wafer fixing area is formed on the surface of the third heat sink through a third interface heat dissipation material layer, wherein the third heat sink is a planar heat sink or a heat sink with grooves, and a second metal plating layer is provided on the surface of the planar heat sink or the surface of the grooves, and a wafer fixing area formed by the third interface heat dissipation material layer is provided on the second metal plating layer for each bare wafer; at least two sets of wafer units, each set of wafer units including at least two bare wafers, and each set of wafer units corresponding to a single wafer product, wherein all bare wafers included in each set of wafer units are back-side down to be fixed to the wafer fixing area on the surface of the third heat sink through the third interface heat dissipation material layer; and a wafer packaging structure formed for the bare wafers after the bare wafers are fixed to the third heat sink.

6. The wafer structure as described in claim 5, wherein, The third interface heat dissipation material layer is a material layer formed based on any of the following heat dissipation materials: any one of nickel, tin, copper, gold, aluminum and silver; an alloy of any one of nickel, tin, copper, gold, aluminum and silver.

7. The wafer structure as described in claim 5, wherein, The third heat sink is either round or square.

8. The wafer structure as described in claim 5, wherein, For each group of wafer units, the front side of the bare wafer has a fifth group of bumps and a sixth group of bumps, wherein the height of the sixth group of bumps is smaller than that of the fifth group of bumps, and the height difference between the two groups of bumps can accommodate the third connecting wafer of the sixth group of bumps used for bonding different bare wafers.

9. The wafer structure as described in claim 8, wherein, The wafer packaging structure includes: a third connecting wafer for bonding the sixth set of bumps of each bare wafer in each set of wafer units; a second mold layer structure formed by sequentially underfilling and molding the bonded bumps, the second mold layer structure being able to expose the fifth set of bumps; and a third solder ball added to the exposed fifth set of bumps.

10. The wafer structure as described in claim 9, wherein, The wafer packaging structure further includes a second conductor redistribution layer (RDL) disposed on the fifth set of bumps before the third solder ball is added.

11. A multi-chip integrated structure, comprising: A third substrate with a hollow middle section, the third substrate having opposing first and second surfaces, and the first surface having a connection point; A first group of bare dies and a second group of bare dies, wherein a portion of the front-side connections of each die in the first group are flip-chip bonded to the first surface of the third substrate with the other portion of the front-side connections facing downwards, and the other portion of the front-side connections are suspended in the cavity; the second group of bare dies is placed in the cavity, and the front-side connections of each die are flip-chip bonded to the suspended connection portions of each die in the first group of bare dies in a face-to-face direct interconnection manner; a heat sink is mounted on the back side of each die in the first group of bare dies and the second group of bare dies; And a fourth solder ball prepared on the second surface of the third substrate.

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