Packaging structure

TWM688440UActive Publication Date: 2026-10-11ADVANCED SEMICON ENG INC
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
TW115204405
Authority / Receiving Office
TW · TW
Patent Type
Utility models
Current Assignee / Owner
Filing Date
2026-05-15
Publication Date
2026-10-11
Estimated Expiration
2036-05-14

Smart Images

  • Figure TWG2TB001916031_001
    Figure TWG2TB001916031_001
  • Figure TWG2TB001916031_002
    Figure TWG2TB001916031_002
  • Figure TWG2TB001916031_003
    Figure TWG2TB001916031_003
Patent Text Reader

Abstract

A packaging structure includes a substrate, an interposer, a redistribution layer, and a wafer layer. The substrate includes a first surface. The interposer is disposed on the first surface of the substrate along a vertical direction and includes a plurality of spaced-apart first copper pillars and a main molded portion covering the first copper pillars. The first copper pillars are electrically connected to the substrate. The main molded portion has a first layer and a second layer disposed along the vertical direction. The coefficient of thermal expansion of the second layer is different from that of the first layer. The redistribution layer is disposed on the interposer along the vertical direction and is electrically connected to the first copper pillars. The wafer layer is disposed on the redistribution layer along the vertical direction. The interposer is located between the substrate and the wafer layer in the vertical direction. The wafer layer includes at least one wafer electrically connected to the redistribution layer.
Need to check novelty before this filing date? Find Prior Art

Claims

1. A packaging structure comprising: a substrate including a first surface; an interposer disposed on the first surface of the substrate along a vertical direction and including a plurality of spaced-apart first copper pillars, and a main molded portion covering the first copper pillars, the first copper pillars being electrically connected to the substrate, the main molded portion having a first layer and a second layer disposed along the vertical direction, the coefficient of thermal expansion of the second layer being different from that of the first layer; a redistribution layer disposed along the vertical direction in the interposer and electrically connected to the first copper pillars; and a wafer layer disposed along the vertical direction in the redistribution layer, the interposer being located between the substrate and the wafer layer in the vertical direction, the wafer layer including at least one wafer electrically connected to the redistribution layer.

2. The encapsulation structure as described in claim 1, wherein, The first layer of the main mold sealing part directly contacts the first surface of the substrate, and the coefficient of thermal expansion of the first layer of the main mold sealing part is greater than that of the second layer.

3. The encapsulation structure as described in claim 2, wherein, The main mold sealing part also has a third layer disposed along the vertical direction on the second layer, and the coefficient of thermal expansion of the second layer of the main mold sealing part is greater than that of the third layer.

4. The encapsulation structure as described in claim 1, wherein, The interposer layer also includes a plurality of second copper pillars covered by the main mold sealing portion. The length of the second copper pillars in the vertical direction is shorter than the length of the first copper pillars in the vertical direction. The second copper pillars are not electrically connected to the redistribution layer or the substrate.

5. The encapsulation structure as described in claim 4, wherein, The second copper pillars are connected to each other in a horizontal direction perpendicular to the vertical direction.

6. The encapsulation structure as described in claim 1, wherein, The wafer layer also includes a side molded portion that surrounds and covers the periphery of the at least one wafer.

7. The encapsulation structure as described in claim 1, wherein, The first surface of the substrate has a downwardly recessed portion, and the interlayer is disposed in the recess.

8. The encapsulation structure as described in claim 7, wherein, The interlayer is flush with the first surface of the substrate.

9. The encapsulation structure as described in claim 1, wherein, The wafer layer also includes a plurality of bumps that electrically connect the wafer to the redistribution layer, and a filler material that fills the space between the at least one wafer and the redistribution layer and covers the bumps.

10. The encapsulation structure as described in claim 1, wherein, The wafer layer has a plurality of wafers, which are spaced apart in a horizontal direction perpendicular to the vertical direction.