Digital isolator and isolation capacitor structure
Patent Information
- Application Number
- TW115207075
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- Filing Date
- 2026-07-27
- Publication Date
- 2026-10-11
- Estimated Expiration
- 2036-07-26
Smart Images
Figure 00000000_0000_ABST
Abstract
Claims
1. An isolation capacitor structure, comprising: One plate; And an upper electrode plate is disposed above the lower electrode plate. The peripheral edge region of the upper electrode plate has a stepped structure. The distance between the upper electrode plate and the lower electrode plate in the peripheral edge region of the upper electrode plate is greater than the distance between the central region of the upper electrode plate and the lower electrode plate.
2. The isolation capacitor structure as claimed in claim 1, wherein the stepped structure is formed by at least two metal layers and at least one through-hole.
3. The isolation capacitor structure as claimed in claim 1, wherein the stepped structure is formed by a metal layer that has been stepped etched.
4. The isolation capacitor structure as claimed in claim 1, wherein the peripheral edge region of the lower electrode plate has another stepped structure, and the distance between the stepped structure of the peripheral edge region of the upper electrode plate and the other stepped structure of the lower electrode plate is greater than the distance between the central region of the upper electrode plate and the central region of the lower electrode plate.
5. The isolation capacitor structure as claimed in claim 4, wherein the other stepped structure of the lower electrode is formed by at least two metal layers and at least one through hole.
6. A digital isolator, comprising: Send a chip; One receiving chip; And an isolation capacitor structure coupled between the transmitting chip and the receiving chip, wherein the isolation capacitor structure includes: a lower electrode plate; And an upper electrode plate is disposed above the lower electrode plate. The peripheral edge region of the upper electrode plate has a stepped structure. The distance between the upper electrode plate and the lower electrode plate in the peripheral edge region of the upper electrode plate is greater than the distance between the central region of the upper electrode plate and the lower electrode plate.
7. The digital isolator as claimed in claim 6, wherein the stepped structure is formed by at least two metal layers and at least one through-hole.
8. The digital isolator as claimed in claim 6, wherein the stepped structure is formed of a metal layer that has been stepped etched.
9. The digital isolator as claimed in claim 6, wherein the peripheral edge region of the lower electrode plate has another stepped structure, and the distance between the stepped structure of the peripheral edge region of the upper electrode plate and the other stepped structure of the lower electrode plate is greater than the distance between the central region of the upper electrode plate and the central region of the lower electrode plate.
10. The digital isolator as claimed in claim 9, wherein the other stepped structure of the lower electrode is formed by at least two metal layers and at least one through hole.