Package structure
Patent Information
- Application Number
- TW115204347
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- Filing Date
- 2026-05-14
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2036-05-13
Smart Images

Figure TWG2TB001917713_001 
Figure TWG2TB001917713_002 
Figure TWG2TB001917713_003
Abstract
Claims
1. A packaging structure, comprising: Circuit layer; A first electronic component layer is disposed on the circuit layer and includes a plurality of first electronic components, wherein the plurality of first electronic components are stacked along a stacking direction perpendicular to the circuit layer, and adjacent first electronic components in the plurality of first electronic components are staggered along the stacking direction and offset towards a first direction parallel to the circuit layer and a second direction relative to the first direction, respectively; a second electronic component layer is disposed on the first electronic component layer and includes second electronic components; and a plurality of electrical connectors are disposed in the first electronic component layer and electrically connect the plurality of first electronic components, the second electronic components and the circuit layer.
2. The packaging structure as described in claim 1, wherein the first electronic component layer and the second electronic component layer are electrically connected by hybrid bonding.
3. The packaging structure as described in claim 1, wherein the plurality of first electronic components are electrically connected by hybrid bonding.
4. The packaging structure as described in claim 1, wherein the plurality of first electronic components offset toward the first direction overlap each other in the vertical projection of the circuit layer.
5. The packaging structure as described in claim 1, wherein the plurality of first electronic components offset toward the second direction overlap each other in the vertical projection of the circuit layer.
6. The packaging structure as described in claim 1 further includes a packaging material layer, wherein the packaging material layer encapsulates the first electronic component layer, and the side surface of the second electronic component is substantially coplanar with the side surface of the packaging material layer.
7. The packaging structure as described in claim 6, wherein the plurality of electrical connectors are disposed in the packaging material layer and are substantially coplanar with the planes on which each of the plurality of first electronic components is located.
8. The packaging structure as described in claim 7, wherein the upper surfaces of the plurality of electrical connectors are substantially coplanar with the upper surfaces of the corresponding plurality of first electronic components.
9. The packaging structure as described in claim 1 further includes a plurality of second electrical connectors, wherein the plurality of second electrical connectors are disposed below the circuit layer and electrically connected to the circuit layer.
10. The packaging structure as described in claim 1 further includes a redistribution layer disposed between the plurality of first electronic components, electrically connecting the plurality of first electronic components and the plurality of electrical connectors.
11. The packaging structure as described in claim 1, wherein the plurality of first electronic components are divided into plurality of groups, and the groups are arranged adjacent to each other with a gap.
12. The packaging structure as described in claim 11, wherein each of the plurality of first electronic elements in each of the plurality of arrays is electrically connected by hybrid bonding.
13. The encapsulation structure as described in claim 11, wherein the plurality of electrical connectors are disposed between the plurality of arrays.
14. The packaging structure as described in claim 11, wherein the plurality of first electronic components offset toward the first direction in each of the plurality of arrays overlap each other in the vertical projection of the circuit layer.
15. The packaging structure as described in claim 11, wherein the plurality of first electronic components offset toward the second direction in each of the plurality of arrays overlap each other in the vertical projection of the circuit layer.
16. The packaging structure as described in claim 11, wherein the first electronic elements in each of the complex arrays that are closest to the second electronic element are substantially coplanar.
17. The packaging structure as claimed in claim 1, wherein the second electronic component comprises a plurality of small wafers arranged in a horizontal direction, and the plurality of electrical connectors electrically connect the plurality of small wafers, the plurality of first electronic components, and the circuit layer.
18. The packaging structure as described in claim 17, wherein the plurality of small wafers and the first electronic component layer are electrically connected by hybrid bonding.
19. The packaging structure as described in claim 1, wherein the plurality of first electronic elements are memory elements and the second electronic element is a logic element.
20. The packaging structure as described in claim 19, wherein the memory element is DRAM.
