Wire bonding directly on exposed conductive vias and interconnects and related systems and methods
By laser-drilling and filling conductive vias and interconnects for direct wirebonding in semiconductor devices, the issues of corrosion and space occupancy in bond fingers are addressed, resulting in smaller, faster, and more reliable semiconductor devices.
US20260215309A1Pending Publication Date: 2026-07-23MICRON TECHNOLOGY INC
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Patent Information
- Authority / Receiving Office
- US · United States
- Patent Type
- Applications(United States)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2026-03-16
- Publication Date
- 2026-07-23
AI Technical Summary
Technical Problem
Existing stacked semiconductor devices face issues with bond fingers and bond pads corroding and occupying valuable space, leading to potential damage and increased size due to the need for additional routing structures.
Method used
The solution involves forming a package substrate with conductive vias and interconnects that are laser-drilled and filled with conductive material, allowing direct wirebonding to the upper surface without bond fingers, and incorporating redistribution layers to optimize signal routing and reduce corrosion risk.
Benefits of technology
This approach reduces corrosion risk, minimizes signal travel length, and conserves space on the package substrate, enabling smaller device sizes and faster signal transmission.
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Smart Images
Figure US20260215309A1-D00000_ABST
Abstract
Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
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