Power semiconductor module

Description

[0001] FIG. 1 is a front, left, and bottom side perspective view of a first embodiment of a power semiconductor module, showing our new design;

[0002] FIG. 2 is a front, right, and top side perspective view of FIG. 1;

[0003] FIG. 3 is a front view of FIG. 1;

[0004] FIG. 4 is a rear view of FIG. 1;

[0005] FIG. 5 is a left side view of FIG. 1;

[0006] FIG. 6 is a right side view of FIG. 1;

[0007] FIG. 7 is a top view of FIG. 1;

[0008] FIG. 8 is a bottom view of FIG. 1;

[0009] FIG. 9 is an exploded view of FIG. 1;

[0010] FIG. 10 is a front, left, and bottom side perspective view of the terminal module in FIG. 9, with the broken lines of the cover and the case body not shown for ease of illustration;

[0011] FIG. 11 is a rear, right, and top side perspective view of FIG. 9;

[0012] FIG. 12 is a front view of FIG. 9;

[0013] FIG. 13 is a rear view of FIG. 9;

[0014] FIG. 14 is a left side view of FIG. 9;

[0015] FIG. 15 is a right side view of FIG. 9;

[0016] FIG. 16 is a top view of FIG. 9;

[0017] FIG. 17 is a bottom view of FIG. 9;

[0018] FIG. 18 is a front, left, bottom exploded perspective view of FIG. 10;

[0019] FIG. 19 is a rear, right, and top exploded perspective view of FIG. 18;

[0020] FIG. 20 is a front, left, and bottom side perspective view of the first terminal part of the terminal module in FIG. 18, shown separately for ease of illustration;

[0021] FIG. 21 is a rear, right, and top side perspective view of FIG. 20;

[0022] FIG. 22 is a front view of FIG. 20;

[0023] FIG. 23 is a rear view of FIG. 20;

[0024] FIG. 24 is a left side view of FIG. 20;

[0025] FIG. 25 is a right side view of FIG. 20;

[0026] FIG. 26 is a top view of FIG. 20;

[0027] FIG. 27 is a bottom view of FIG. 20;

[0028] FIG. 28 is a front, left, and bottom side perspective view of the second terminal part of the terminal module in FIG. 18, shown separately for ease of illustration;

[0029] FIG. 29 is a rear, right, and top side perspective view of FIG. 28;

[0030] FIG. 30 is a front view of FIG. 28;

[0031] FIG. 31 is a rear view of FIG. 28;

[0032] FIG. 32 is a left side view of FIG. 28;

[0033] FIG. 33 is a right side view of FIG. 28;

[0034] FIG. 34 is a top view of FIG. 28;

[0035] FIG. 35 is a bottom view of FIG. 28;

[0036] FIG. 36 is a front, left, and bottom exploded perspective view of a second embodiment of a power semiconductor module, showing our new design;

[0037] FIG. 37 is a rear, right and top exploded perspective view of FIG. 36;

[0038] FIG. 38 is a front, left, and bottom side perspective view of the first terminal part of the terminal module in FIG. 36, shown separately for ease of illustration;

[0039] FIG. 39 is a bottom view of FIG. 38;

[0040] FIG. 40 is a rear, right, and top side perspective view of the second terminal part of the terminal module in FIG. 36, shown separately for ease of illustration;

[0041] FIG. 41 is a front view of FIG. 40;

[0042] FIG. 42 is a rear view of FIG. 40;

[0043] FIG. 43 is a left side view of FIG. 40;

[0044] FIG. 44 is a right side view of FIG. 40;

[0045] FIG. 45 is a top view of FIG. 40;

[0046] FIG. 46 is a front, left, and bottom side perspective view of a third embodiment of a power semiconductor module, showing our new design;

[0047] FIG. 47 is a front, right, and top side perspective view of FIG. 46;

[0048] FIG. 48 is a front view of FIG. 46;

[0049] FIG. 49 is an exploded perspective view of FIG. 46;

[0050] FIG. 50 is a front, left, and bottom side perspective view of the terminal module in FIG. 46, with the broken lines of the cover and case body not shown for ease of illustration;

[0051] FIG. 51 is a rear, right, and top side perspective view of FIG. 50;

[0052] FIG. 52 is a front view of FIG. 50;

[0053] FIG. 53 is a rear view of FIG. 50;

[0054] FIG. 54 is a left side view of FIG. 50;

[0055] FIG. 55 is a right side view of FIG. 50;

[0056] FIG. 56 is a top view of FIG. 50; and,

[0057] FIG. 57 is a bottom view of FIG. 50.

[0058] The broken lines in the figures illustrate the portions of the design that form no part of the claimed design.

Claims

The ornamental design for a power semiconductor module as shown and described.

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