Display background and display background control methods, and display devices

Abstract

The invention relates to a display platform and a method of controlling a display platform, and a display device. The display platform (100) consists of pixel units (20) and pixel circuits (30). The pixel units (20) are divided into groups, and each pixel circuit (30) is used to control the corresponding group of pixel units (20). Each pixel circuit (30) consists of a control circuit (31), a data recording circuit (32), a storage circuit (33), a sensing circuit (34), and a light-emitting control circuit (35). The light-emitting control circuit (35) is connected to each light-emitting element of the corresponding group of pixel units (20), and the light-emitting control circuit (35) is configured to, in response to at least two light-emitting control signals, supply control current to the light-emitting elements of the pixel units (20) in the corresponding group of pixel units (20) at different times.The pixel circuits (30) in the display background (100) achieve capacitive multiplexing, which can increase the area of ​​the capacitor and facilitate the maintenance of the capacitor voltage.

Description

Display substrate, driving method thereof, and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a driving method thereof, and a display device. Background Art

[0002] With the rise of smart wearables, virtual reality, augmented reality, and other devices, consumers are increasingly demanding the performance of small-sized display panels on these devices, with requirements for indicators such as brightness, size, and power consumption constantly increasing. MicroLED technology is a new type of display technology that uses micro-processing technology to thin-film and miniaturize the light-emitting diode (LED) structure on a substrate. Each LED unit is approximately 1 to 10 microns in size. The arrayed LED units are then transferred in batches to a circuit board using mass transfer technology. The positive and negative poles of the LED units are connected by vertically staggered positive and negative grid electrodes. After power is applied in sequence, the LED units are illuminated and imaged through scanning, enabling each pixel to be individually addressed and driven to emit light. With advancements in product technology and cost optimization, energy-saving, efficient, stable, and compact MicroLEDs can be expanded to applications such as ultra-high-resolution large-screen displays and automobiles.

[0003] Silicon-based organic light-emitting diode (OLED) microdisplay technology, also known as miniaturized OLED technology, maintains its fundamental principle of luminescence driven by carrier injection and recombination, retaining OLED's characteristics of low power consumption, fast response, wide viewing angle, and high resolution. Furthermore, silicon-based OLED utilizes the single-crystal silicon substrate process of liquid crystal on silicon (LCOS), achieving higher light utilization efficiency than glass substrates, exceeding 40%. Using this miniaturized process, silicon-based OLED display panels achieve high pixel density (PPI), compact size, and portability.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate; a plurality of pixel units arranged on the base substrate; and a plurality of pixel circuits arranged on the base substrate; wherein the plurality of pixel units are arranged in a plurality of rows and columns, the plurality of pixel units are divided into a plurality of groups, each group of pixel units includes at least two pixel units, and each pixel unit includes a light-emitting element; each pixel circuit is used to drive a corresponding group of pixel units, and each pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, a sensing circuit and a light-emitting control circuit; the driving circuit is respectively connected to the data writing circuit, the storage circuit, the sensing circuit and the light-emitting control circuit, and is configured to control a driving current the size of the pixel unit; the data writing circuit is configured to write the data signal into the driving circuit in response to a first scanning signal; the storage circuit is configured to store the data signal written by the data writing circuit; the sensing circuit is configured to connect the driving circuit to the sensing signal line in response to a second scanning signal; the light emitting control circuit is connected to the driving circuit and is respectively connected to at least two light emitting elements of at least two pixel units of a corresponding group of pixel units, and the light emitting control circuit is configured to apply the driving current to the light emitting elements of each pixel unit in the group of pixel units at different times in response to at least two light emitting control signals; the light emitting element is configured to emit light according to the received driving current.

[0006] For example, in a display substrate provided in an embodiment of the present disclosure, the number of pixel units included in each group of pixel units is N, where N is a positive integer, the light-emitting control circuit includes N light-emitting control sub-circuits, the at least two light-emitting control signals include N light-emitting control signals, each light-emitting control sub-circuit is connected to the light-emitting element of a pixel unit in a corresponding group of pixel units, each light-emitting control sub-circuit receives one of the N light-emitting control signals, different light-emitting control sub-circuits are connected to the light-emitting elements of different pixel units in a corresponding group of pixel units, and different light-emitting control sub-circuits receive different light-emitting control signals.

[0007] For example, in a display substrate provided in an embodiment of the present disclosure, the driving circuit includes a control end, a first end, and a second end. The first end of the driving circuit receives a first voltage from a first voltage end. The data writing circuit is connected to the control end of the driving circuit. The first end of the storage circuit is connected to the control end of the driving circuit. The second end of the storage circuit is connected to the first end of the driving circuit. The sensing circuit is connected to the second end of the driving circuit. The light-emitting control circuit is connected to the second end of the driving circuit. The first end of the light-emitting element is connected to the light-emitting control circuit. The second end of the light-emitting element receives the second voltage from the second voltage end.

[0008] For example, in a display substrate provided in an embodiment of the present disclosure, the data writing circuit includes a first transistor, the sensing circuit includes a second transistor, the driving circuit includes a third transistor, and the storage circuit includes a storage capacitor; the gate of the third transistor serves as the control end of the driving circuit, the first electrode of the third transistor serves as the first end of the driving circuit, and the second electrode of the third transistor serves as the second end of the driving circuit; the gate of the first transistor is connected to the first scan line to receive the first scan signal, the first electrode of the first transistor is connected to the data line to receive the data signal, and the second electrode of the first transistor is connected to the gate of the third transistor; the gate of the second transistor is connected to the second scan line to receive the second scan signal, the first electrode of the second transistor is connected to the second electrode of the third transistor, and the second electrode of the second transistor is connected to the sensing signal line; the first electrode of the storage capacitor serves as the first end of the storage circuit, and the second electrode of the storage capacitor serves as the second end of the storage circuit.

[0009] For example, in the display substrate provided in one embodiment of the present disclosure, each light-emitting control subcircuit includes a light-emitting control transistor, a gate of the light-emitting control transistor is connected to a corresponding light-emitting control signal line to receive a corresponding light-emitting control signal, a first electrode of the light-emitting control transistor is connected to a second electrode of the third transistor, and a second electrode of the light-emitting control transistor is connected to a corresponding light-emitting element.

[0010] For example, in a display substrate provided in an embodiment of the present disclosure, the storage capacitor includes two stacked capacitor plates, one of the two capacitor plates serves as the first electrode of the storage capacitor, and the other of the two capacitor plates serves as the second electrode of the storage capacitor; the orthographic projection of at least one of the two capacitor plates on the base substrate at least partially covers the orthographic projection of the first transistor on the base substrate and at least partially covers the orthographic projection of the second transistor on the base substrate.

[0011] For example, in the display substrate provided in one embodiment of the present disclosure, the orthographic projection of the first transistor on the base substrate includes at least the orthographic projection of the active layer of the first transistor on the base substrate, and the orthographic projection of the second transistor on the base substrate includes at least the orthographic projection of the active layer of the second transistor on the base substrate.

[0012] For example, in the display substrate provided in an embodiment of the present disclosure, the orthographic projection of at least one of the two capacitor plates on the base substrate at least partially covers the orthographic projection of the third transistor on the base substrate.

[0013] For example, in a display substrate provided by an embodiment of the present disclosure, the orthographic projection of the first transistor on the base substrate and the orthographic projection of the second transistor on the base substrate are located on both sides of the orthographic projection of the third transistor on the base substrate.

[0014] For example, in the display substrate provided in an embodiment of the present disclosure, the orthographic projection of at least one of the two capacitor plates on the base substrate at least partially covers the orthographic projection of the light emitting control transistor on the base substrate.

[0015] For example, in the display substrate provided in an embodiment of the present disclosure, the two capacitor plates include a first capacitor plate and a second capacitor plate, the orthographic projection of the second capacitor plate on the base substrate covers the orthographic projection of the first capacitor plate on the base substrate; the first capacitor plate is connected to the first transfer electrode through a first group of vias, and the orthographic projection of the first transfer electrode on the base substrate and the orthographic projection of the first group of vias on the base substrate are both located within the orthographic projection of the first capacitor plate on the base substrate; the second capacitor plate is connected to the second transfer electrode through a second group of vias, and the orthographic projection of the second transfer electrode on the base substrate and the orthographic projection of the second group of vias on the base substrate are both located within the orthographic projection of the second capacitor plate on the base substrate, and neither overlaps with the orthographic projection of the first capacitor plate on the base substrate.

[0016] For example, in the display substrate provided in an embodiment of the present disclosure, there is a gap between the orthographic projection of the second switching electrode on the base substrate and the orthographic projection of the first capacitor plate on the base substrate.

[0017] For example, in a display substrate provided in an embodiment of the present disclosure, the N light-emitting control subcircuits include a first light-emitting control subcircuit, a second light-emitting control subcircuit, a third light-emitting control subcircuit and a fourth light-emitting control subcircuit, the first light-emitting control subcircuit includes a first light-emitting control transistor, the second light-emitting control subcircuit includes a second light-emitting control transistor, the third light-emitting control subcircuit includes a third light-emitting control transistor, and the fourth light-emitting control subcircuit includes a fourth light-emitting control transistor. The first light-emitting control transistor, the second light-emitting control transistor, the third light-emitting control transistor and the fourth light-emitting control transistor are distributed along a first direction, and a first via connected to the gate of the first light-emitting control transistor, a second via connected to the gate of the second light-emitting control transistor, a third via connected to the gate of the third light-emitting control transistor and a fourth via connected to the gate of the fourth light-emitting control transistor are not located on the same straight line extending along the first direction.

[0018] For example, in the display substrate provided in one embodiment of the present disclosure, the first electrode and the second electrode of the first light-emitting control transistor, the first electrode and the second electrode of the second light-emitting control transistor, the first electrode and the second electrode of the third light-emitting control transistor, and the first electrode and the second electrode of the fourth light-emitting control transistor are all located on the same extension line extending along the first direction, and the first via hole, the second via hole, the third via hole and the fourth via hole are alternately located on both sides of the extension line.

[0019] For example, in a display substrate provided in an embodiment of the present disclosure, the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are located on the same distribution line extending along the first direction, and the distribution line and the extension line are parallel to each other and have a gap.

[0020] For example, in the display substrate provided in one embodiment of the present disclosure, the data line and the sensing signal line are spaced apart from each other and extend along a second direction on the base substrate, where the second direction is perpendicular to the first direction, and the orthographic projection of the data line on the base substrate and the orthographic projection of the sensing signal line on the base substrate are located on both sides of the orthographic projection of the third transistor on the base substrate.

[0021] For example, in the display substrate provided in one embodiment of the present disclosure, the orthographic projection of the data line on the base substrate is located between the orthographic projection of the first transistor on the base substrate and the orthographic projection of the third transistor on the base substrate, and the orthographic projection of the sensing signal line on the base substrate is located between the orthographic projection of the second transistor on the base substrate and the orthographic projection of the third transistor on the base substrate.

[0022] For example, in the display substrate provided in one embodiment of the present disclosure, the length of the current flow path between the second light-emitting control transistor and the third light-emitting control transistor and the corresponding light-emitting elements is greater than the length of the current flow path between the first light-emitting control transistor and the fourth light-emitting control transistor and the corresponding light-emitting elements.

[0023] For example, in a display substrate provided in one embodiment of the present disclosure, the first light-emitting control transistor is connected to the corresponding light-emitting element through a first transfer line, the second light-emitting control transistor is connected to the corresponding light-emitting element through a second transfer line, the third light-emitting control transistor is connected to the corresponding light-emitting element through a third transfer line, and the fourth light-emitting control transistor is connected to the corresponding light-emitting element through a fourth transfer line. The first transfer line and the fourth transfer line are axially symmetrically distributed, and the second transfer line and the third transfer line are axially symmetrically distributed.

[0024] For example, in the display substrate provided in an embodiment of the present disclosure, the first adapter line, the second adapter line, the third adapter line, and the fourth adapter line are all L-shaped lines.

[0025] For example, in a display substrate provided in an embodiment of the present disclosure, the L-shaped trace includes a first segment extending along the first direction and a second segment extending along the second direction, the second direction is perpendicular to the first direction, the orthographic projection of the first segment on the base substrate does not overlap with the orthographic projection of the capacitor plate on the base substrate, and the orthographic projection of the second segment on the base substrate overlaps with the orthographic projection of the capacitor plate on the base substrate.

[0026] For example, in the display substrate provided in one embodiment of the present disclosure, the first adapter wire is connected to the corresponding light-emitting element through a fifth via hole, and the fifth via hole is located in the first section of the first adapter wire; the second adapter wire is connected to the corresponding light-emitting element through a sixth via hole, and the sixth via hole is located in the first section of the second adapter wire; the third adapter wire is connected to the corresponding light-emitting element through a seventh via hole, and the seventh via hole is located in the first section of the third adapter wire; the fourth adapter wire is connected to the corresponding light-emitting element through an eighth via hole, and the eighth via hole is located in the first section of the fourth adapter wire.

[0027] For example, in the display substrate provided in one embodiment of the present disclosure, the lengths of the first segment of the second adapter line and the first segment of the third adapter line are equal and are both the first length, the lengths of the first segment of the first adapter line and the first segment of the fourth adapter line are equal and are both the second length, and the first length is greater than the second length.

[0028] For example, in a display substrate provided by an embodiment of the present disclosure, pixel units of the same group are located in the same row and are arranged adjacent to each other in sequence.

[0029] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate includes a silicon-based organic light emitting diode display substrate.

[0030] At least one embodiment of the present disclosure further provides a display device, comprising a display substrate as provided in any embodiment of the present disclosure.

[0031] At least one embodiment of the present disclosure further provides a driving method for a display substrate provided by any embodiment of the present disclosure, wherein the at least two pixel units included in each group of pixel units include 1st to Nth pixel units, the at least two light-emitting control signals include 1st to Nth light-emitting control signals, and a frame display stage includes 1st to Nth stages, N is a positive integer, and the method includes: in the Pth stage of the display stage, providing a first scanning signal that is shifted in sequence to multiple rows of pixel units of the display substrate, and making the Pth light-emitting control signal of each row of pixel units a working level, and making the light-emitting control signals of the at least two light-emitting control signals of each row of pixel units other than the Pth light-emitting control signal a non-working level, so as to realize row-by-row scanning of the Pth pixel unit in each group of pixel units in the Pth stage, wherein 1≤P≤N and P is an integer.

[0032] For example, in the method provided in one embodiment of the present disclosure, in each stage from the first stage to the Nth stage, the first scanning signal corresponding to the same row of pixel units has a pulse waveform with the working level, and in the display stage, the number of the pulse waveforms of the first scanning signal corresponding to the same row of pixel units is N.

[0033] For example, the method provided by an embodiment of the present disclosure also includes: in the blanking stage, making at least two light-emitting control signals of each row of pixel units at non-working levels, and making the first scanning signal and the second scanning signal of the target row of pixel units at working levels, wherein the target row of pixel units are pixel units that need to be detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0035] FIG1 is a schematic diagram of a pixel circuit;

[0036] FIG2 is a schematic diagram of a layout of a display substrate provided in some embodiments of the present disclosure;

[0037] FIG3A is a schematic block diagram of a pixel circuit of a display substrate provided by some embodiments of the present disclosure;

[0038] FIG3B is a schematic block diagram of a pixel circuit of another display substrate provided in some embodiments of the present disclosure;

[0039] FIG4 is a schematic block diagram of a light emitting control circuit in a pixel circuit of a display substrate provided by some embodiments of the present disclosure;

[0040] FIG5A is a schematic diagram of a specific example of the pixel circuit shown in FIG3B ;

[0041] FIG5B is a schematic diagram of a specific example of the pixel circuit shown in FIG3A ;

[0042] FIG6 is a plan view of a layer structure of a display substrate provided by some embodiments of the present disclosure;

[0043] FIG7A is a plan view of an active layer of a display substrate provided in some embodiments of the present disclosure;

[0044] FIG7B is a plan view of a gate layer of a display substrate provided in some embodiments of the present disclosure;

[0045] FIG7C is a plan view of the layer structure of FIG7A and FIG7B after superposition;

[0046] FIG8A is a plan view of an injection layer of a display substrate provided in some embodiments of the present disclosure;

[0047] FIG8B is a plan view of a first metal layer of a display substrate provided in some embodiments of the present disclosure;

[0048] FIG8C is a plan view of the layer structure of FIG7C , FIG8A and FIG8B after superposition;

[0049] FIG9A is a plan view of a second metal layer of a display substrate provided in some embodiments of the present disclosure;

[0050] FIG9B is a plan view of the layer structure of FIG9A and FIG8C after superposition;

[0051] FIG10A is a plan view of a third metal layer of a display substrate provided in some embodiments of the present disclosure;

[0052] FIG10B is a plan view of a fourth metal layer of a display substrate provided in some embodiments of the present disclosure;

[0053] FIG10C is a plan view of a fifth metal layer of a display substrate provided in some embodiments of the present disclosure;

[0054] FIG10D is a plan view of a sixth metal layer of a display substrate provided in some embodiments of the present disclosure;

[0055] FIG10E is a plan view of the layer structure of FIG9B and FIG10A to FIG10D after superposition;

[0056] FIG11A is a plan view of a storage capacitor of a display substrate provided in some embodiments of the present disclosure;

[0057] FIG11B is a plan view of a capacitance switching electrode layer in a storage capacitor of a display substrate provided by some embodiments of the present disclosure;

[0058] FIG12 is a schematic block diagram of a display device provided by some embodiments of the present disclosure;

[0059] FIG13 is a schematic flow chart of a method for driving a display substrate according to some embodiments of the present disclosure;

[0060] FIG14 is a driving timing diagram of a display substrate provided by some embodiments of the present disclosure;

[0061] FIG15 is a schematic diagram of a source driving circuit provided in some embodiments of the present disclosure;

[0062] FIG16 is a schematic diagram of a display driver architecture provided by some embodiments of the present disclosure;

[0063] FIG17 is a schematic diagram of a sensing circuit provided in some embodiments of the present disclosure;

[0064] FIG18 is a comparison diagram of sensing timings provided by some embodiments of the present disclosure; and

[0065] FIG19 is a schematic diagram of the layout of a display substrate provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0066] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0068] Silicon-based OLEDs integrate the characteristics of OLEDs with the advantages of complementary metal oxide semiconductor (CMOS) technology. They can achieve high PPI (current silicon-based OLED technology can achieve approximately 4000 PPI) and are capable of mass production, which helps reduce size and production costs. As consumers' demand for display performance increases, silicon-based OLED technology faces numerous challenges.

[0069] First, silicon-based OLED technology is constrained by the process of the pixel circuit itself. The pixel size corresponding to 4000PPI is about 4μm. If the PPI needs to be further increased to achieve higher resolution, the pixel size needs to be further reduced, which poses a challenge to the analog CMOS process. For example, the capacitance area of ​​the storage capacitor cannot be significantly increased, and it is difficult for a small area capacitor to maintain voltage stability. The unit area capacitance that can be achieved by current CMOS technology does not exceed 2Ff / μm. 2 , it is difficult to achieve a higher PPI.

[0070] FIG1 is a schematic diagram of a pixel circuit. This pixel circuit is, for example, a pixel circuit suitable for silicon-based OLEDs and employs a 3T1C structure. For example, T1 is a switching transistor that, under the control of a first gate signal G01, transmits a data signal Vd to the gate of T2. T2 is a driving transistor whose drain is connected to a high voltage terminal ELVDD and whose source is connected to the anode of the OLED. The driving transistor T2 provides the required driving current for the OLED. T3 is a sensing transistor that, under the control of a second gate signal G02, transmits the sensed voltage value to a sensing signal line Se for further transmission to a compensation circuit. During data writing, the driving transistor T2 operates in a subthreshold region, such that the driving transistor T2 is in a linear following relationship at points g and s. The current of the driving transistor T2 is changed by writing the data signal, thereby adjusting the brightness of the OLED.

[0071] To increase PPI, the size of the MOS transistor needs to be further reduced, as does the size of the storage capacitor C. Under current CMOS process conditions, when the capacitance per unit area cannot be increased, reducing the capacitor area will result in the data signal (voltage value) transmitted to the gate of the driving transistor T2 not being maintained within a frame, which can cause display problems and reduce display quality.

[0072] Secondly, silicon-based OLED technology is constrained by the driver circuits required for the pixel circuits. Given the same area, a higher PPI requires more data drivers and gate drivers, significantly increasing chip area and power consumption, thus increasing chip cost. Given the sheer number of channels, minimizing driver circuit area and controlling power consumption is a challenge that has constrained the development of silicon-based OLED technology.

[0073] Third, silicon-based OLED technology is constrained by compensation circuits. Similar to OLED, silicon-based OLED also faces the problem of threshold voltage drift and requires threshold voltage compensation. Current silicon-based products do not compensate for threshold voltage. The capacitance of a typical large-size OLED sensing line can be as high as hundreds of picofarads (pf), while the corresponding capacitance in a silicon-based OLED is only on the order of pf, which is comparable to the size of the sampling capacitor. If the traditional design timing is followed, the compensation deviation will be caused by capacitance sharing and capacitance deviation between the sensing signal lines, thereby reducing the compensation effect or even failing to obtain the compensation effect.

[0074] Fourth, silicon-based OLED technology is constrained by system-level limitations. A higher PPI requires more data processing, greater bandwidth, and more complex algorithms, significantly increasing system area and power consumption. Achieving higher-definition displays while conserving power and area within existing bandwidths is a challenge that constrains the development of silicon-based OLED technology.

[0075] At least one embodiment of the present disclosure provides a display substrate, a driving method thereof, and a display device. The pixel circuit in the display substrate implements capacitor multiplexing, so that one storage capacitor corresponds to multiple pixel units. Only one capacitor is required within the area occupied by the multiple pixel units on the substrate. This increases the capacitor area, facilitates capacitor voltage maintenance, and thus improves display quality.

[0076] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements described above.

[0077] At least one embodiment of the present disclosure provides a display substrate. The display substrate includes a base substrate, a plurality of pixel units disposed on the base substrate, and a plurality of pixel circuits disposed on the base substrate. The plurality of pixel units are arranged in multiple rows and columns and divided into multiple groups, each group of pixel units including at least two pixel units, each of which includes a light-emitting element. Each pixel circuit is configured to drive a corresponding group of pixel units and includes a driving circuit, a data writing circuit, a storage circuit, a sensing circuit, and a light-emitting control circuit. The driving circuit is respectively connected to the data writing circuit, the storage circuit, the sensing circuit, and the light-emitting control circuit and is configured to control the magnitude of a driving current. The data writing circuit is configured to write a data signal to the driving circuit in response to a first scanning signal; the storage circuit is configured to store the data signal written by the data writing circuit; and the sensing circuit is configured to connect the driving circuit to a sensing signal line in response to a second scanning signal. The light-emitting control circuit is connected to the driving circuit and to at least two light-emitting elements of at least two pixel units in a corresponding group of pixel units. The light-emitting control circuit is configured to apply a driving current to the light-emitting elements of each pixel unit in the group at different times in response to the at least two light-emitting control signals. The light-emitting elements are configured to emit light in response to the received driving current.

[0078] FIG2 is a schematic diagram of a layout of a display substrate provided in some embodiments of the present disclosure. As shown in FIG2 , the display substrate 100 includes a base substrate 10, a plurality of pixel units 20 disposed on the base substrate 10, and a plurality of pixel circuits 30 disposed on the base substrate 10. For example, the base substrate 10 may be a silicon substrate.

[0079] For example, a plurality of pixel units 20 are arranged into multiple rows and columns to form a pixel array. For example, a plurality of pixel units 20 can be arranged into Q rows and K columns, where Q and K can be any positive integers. For example, a plurality of pixel units 20 are divided into multiple groups, each group of pixel units 20 includes at least two pixel units 20, and the pixel units 20 of the same group are located in the same row and arranged adjacent to each other in sequence. For example, in the example shown in Figure 2, each group of pixel units 20 includes 4 pixel units 20, and the 4 pixel units 20 of each group are located in the same row and arranged adjacent to each other in sequence. Of course, the embodiments of the present disclosure are not limited to this, and the number of pixel units 20 contained in each group can be any number such as 2, 3, 5, etc., which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this. Each pixel unit 20 includes a light-emitting element, which can be an OLED. Thus, the display substrate 100 can be a silicon-based OLED display substrate.

[0080] For example, multiple pixel circuits 30 correspond one-to-one to multiple groups of pixel units 20, with each pixel circuit 30 used to drive a corresponding group of pixel units 20. That is, one pixel circuit 30 is used to drive multiple pixel units 20 belonging to the same group. The pixel circuits 30 can be stacked below a corresponding group of pixel units 20. Because the pixel units 20 of the same group are located in the same row, the drive control method can be simplified when the pixel circuits 30 are used to drive the corresponding group of pixel units 20, resulting in a more natural and uniform frame switching effect and improved display quality.

[0081] FIG3A is a schematic block diagram of a pixel circuit of a display substrate provided in some embodiments of the present disclosure. As shown in FIG3A , each pixel circuit 30 includes a driving circuit 31 , a data writing circuit 32 , a storage circuit 33 , and a sensing circuit 34 .

[0082] The drive circuit 31 is connected to the data write circuit 32, the storage circuit 33, and the sensing circuit 34, respectively, and is configured to control the magnitude of the drive current. The data write circuit 32 is configured to write the data signal of the data line Vd to the drive circuit 31 in response to the first scan signal of the first scan line G1. The storage circuit 33 is configured to store the data signal written by the data write circuit 32. The sensing circuit 34 is configured to connect the drive circuit 31 to the sensing signal line Se in response to the second scan signal of the second scan line G2. The light-emitting elements L1...LN are connected to the pixel circuit 30 and are configured to emit light in response to the received drive current. For example, the light-emitting elements L1...LN are light-emitting elements of the pixel units 20 of the same group.

[0083] FIG3B is a schematic block diagram of another pixel circuit of a display substrate provided in some embodiments of the present disclosure. As shown in FIG3B , each pixel circuit 30 includes a driving circuit 31 , a data writing circuit 32 , a storage circuit 33 , a sensing circuit 34 , and a light emitting control circuit 35 .

[0084] The driving circuit 31 includes a control terminal 310, a first terminal 311, and a second terminal 312, and is configured to control the magnitude of the driving current. The first terminal 311 of the driving circuit 31 receives a first voltage from the first voltage terminal ELVDD. For example, in some examples, the first terminal 311 of the driving circuit 31 can be directly connected to the first voltage terminal ELVDD. For example, in other examples, the first terminal 311 of the driving circuit 31 can also be connected to the first voltage terminal ELVDD via other components.

[0085] The data write circuit 32 is connected to the control terminal 310 of the driving circuit 31 and is configured to write a data signal to the control terminal 310 of the driving circuit 31 in response to the first scan signal. For example, the data write circuit 32 is connected to the data line Vd to receive the data signal, which can be a voltage signal. The data write circuit 32 is also connected to the first scan line G1 to receive the first scan signal.

[0086] A first terminal of the storage circuit 33 is connected to the control terminal 310 of the driving circuit 31 , and a second terminal of the storage circuit 33 is connected to the first terminal 311 of the driving circuit 31 . The storage circuit 33 is configured to store the data signal written by the data writing circuit 32 .

[0087] The sensing circuit 34 is connected to the second terminal 312 of the driving circuit 31 and is configured to connect the second terminal 312 of the driving circuit 31 to the sensing signal line Se in response to the second scanning signal. For example, the sensing circuit 34 is connected to the second scanning line G2 to receive the second scanning signal.

[0088] The light control circuit 35 is connected to the second terminal 312 of the driver circuit 31 and is respectively connected to at least two light-emitting elements L1 ... LN of at least two pixel units 20 in a corresponding group of pixel units 20. For example, the light control circuit 35 is respectively connected to the light-emitting elements L1 ... LN of all pixel units 20 in the corresponding group of pixel units 20. The light control circuit 35 is configured to apply a driving current to the light-emitting elements L1 ... LN of each pixel unit 20 in the group of pixel units 20 at different times in response to at least two light control signals. For example, the light control circuit 35 is connected to at least two light control signal lines EM1 ... EMN, thereby receiving at least two light control signals. For example, each light control signal line provides one light control signal. For example, in some examples, at a first moment, the light control circuit 35 applies a driving current to light-emitting element L1, while the other light-emitting elements do not receive the driving current; at a second moment, the light control circuit 35 applies a driving current to light-emitting element L2, while the other light-emitting elements do not receive the driving current, and so on.

[0089] Taking light-emitting element L1 as an example, a first terminal S1 of light-emitting element L1 is connected to the light-emitting control circuit 35, and a second terminal S2 of light-emitting element L1 receives the second voltage from the second voltage terminal ELVSS. Light-emitting element L1 is configured to emit light based on the received drive current. The connection methods of other light-emitting elements are similar to those of light-emitting element L1 and are not further described here.

[0090] In this embodiment, the first voltage terminal ELVDD is configured to maintain an input DC high-level signal, for example, and this DC high-level signal is referred to as the first voltage. For example, the second voltage terminal ELVSS is configured to maintain an input DC low-level signal, for example, and this DC low-level signal is referred to as the second voltage. For example, the second voltage can be ground voltage. The following embodiments are similar to this and are not further described.

[0091] Figure 4 is a schematic block diagram of a light-emitting control circuit in a pixel circuit of a display substrate provided in some embodiments of the present disclosure. As shown in Figure 4 , when each group of pixel units 20 includes N pixel units 20 (N is a positive integer), the corresponding light-emitting control circuit 35 includes N light-emitting control sub-circuits 351. Accordingly, the light-emitting control signal includes N light-emitting control signals. That is, the N light-emitting control sub-circuits 351 are respectively connected to N light-emitting control signal lines EM1…EMN to receive the N light-emitting control signals. The light-emitting elements of this group of pixel units 20 are L1…LN.

[0092] For example, each light-emitting control subcircuit 351 is connected to the light-emitting element of one pixel unit 20 in a corresponding group of pixel units 20, and each light-emitting control subcircuit 351 receives one of N light-emitting control signals. Different light-emitting control subcircuits 351 are connected to different light-emitting elements of different pixel units 20 in a corresponding group of pixel units 20, and different light-emitting control subcircuits 351 receive different light-emitting control signals. That is, there is a one-to-one correspondence between the N light-emitting control signals, the N light-emitting control subcircuits 351, and the N light-emitting elements. Each light-emitting control subcircuit 351 receives a corresponding light-emitting control signal and controls the corresponding light-emitting element to emit light.

[0093] For example, when a light-emission control signal is at an active level, the corresponding light-emission control subcircuit 351 is turned on, thereby applying a drive current to the corresponding light-emitting element, thereby driving the corresponding light-emitting element to emit light. At this time, the remaining light-emission control signals are at an inactive level, and therefore the remaining light-emission control subcircuits 351 are turned off, causing the remaining light-emitting elements to not emit light. This allows independent control of the light-emitting elements.

[0094] FIG5A is a schematic diagram of a specific example of the pixel circuit shown in FIG3B . As shown in FIG5A , the data write circuit 32 may include a first transistor M1, the sensing circuit 34 may include a second transistor M2, and the drive circuit 31 may include a third transistor M3. The storage circuit 33 may include a storage capacitor C1, which includes two stacked capacitor plates, one of which serves as a first electrode of the storage capacitor C1, and the other of which serves as a second electrode of the storage capacitor C1. The structure of the capacitor plates will be described later and will not be detailed here.

[0095] For example, the gate of the third transistor M3 serves as the control terminal 310 of the driving circuit 31, the first electrode of the third transistor M3 serves as the first terminal 311 of the driving circuit 31, and the second electrode of the third transistor M3 serves as the second terminal 312 of the driving circuit 31. The first electrode of the third transistor M3 is connected to the first voltage terminal ELVDD.

[0096] A gate of the first transistor M1 is connected to the first scan line G1 to receive a first scan signal, a first electrode of the first transistor M1 is connected to the data line Vd to receive a data signal, and a second electrode of the first transistor M1 is connected to the gate of the third transistor M3.

[0097] A gate of the second transistor M2 is connected to the second scan line G2 to receive a second scan signal, a first electrode of the second transistor M2 is connected to the second electrode of the third transistor M3 , and a second electrode of the second transistor M2 is connected to the sensing signal line Se.

[0098] The first electrode of the storage capacitor C1 (i.e., one of the two capacitor plates) serves as the first end of the storage circuit 33, and the second electrode of the storage capacitor C1 (i.e., the other of the two capacitor plates) serves as the second end of the storage circuit 33. That is, the first electrode of the storage capacitor C1 serves as the first end of the storage circuit 33 and is connected to the gate of the third transistor M3, and the second electrode of the storage capacitor C1 serves as the second end of the storage circuit 33 and is connected to the first electrode of the third transistor M3.

[0099] For example, each light-emitting control subcircuit 351 includes a light-emitting control transistor. Taking the light-emitting control circuit 35 as an example, which includes four light-emitting control subcircuits 351 (i.e., N=4), the four light-emitting control subcircuits 351 can be implemented as four light-emitting control transistors M4-M7. Each light-emitting control subcircuit 351 is implemented as one light-emitting control transistor. It should be noted that N can be any applicable positive integer, as long as it is greater than or equal to 2. Although four light-emitting control transistors M4-M7 are shown in FIG5A, this does not constitute a limitation on the embodiments of the present disclosure. For example, the gates of the light-emitting control transistors M4-M7 are connected to the corresponding light-emitting control signal lines EM1-EM4 to receive the corresponding light-emitting control signals, the first electrodes of the light-emitting control transistors M4-M7 are connected to the second electrodes of the third transistor M3, and the second electrodes of the light-emitting control transistors M4-M7 are connected to the corresponding light-emitting elements L1-L4.

[0100] For example, in this example, the N light-emission control subcircuits 351 include a first light-emission control subcircuit, a second light-emission control subcircuit, a third light-emission control subcircuit, and a fourth light-emission control subcircuit. The first light-emission control subcircuit includes a first light-emission control transistor M4, the second light-emission control subcircuit includes a second light-emission control transistor M5, the third light-emission control subcircuit includes a third light-emission control transistor M6, and the fourth light-emission control subcircuit includes a fourth light-emission control transistor M7.

[0101] For example, the gate of the first emission control transistor M4 is connected to the emission control signal line EM1 to receive a corresponding emission control signal. The first electrode of the first emission control transistor M4 is connected to the second electrode of the third transistor M3, and the second electrode of the first emission control transistor M4 is connected to the light-emitting element L1. The gate of the second emission control transistor M5 is connected to the emission control signal line EM2 to receive a corresponding emission control signal. The first electrode of the second emission control transistor M5 is connected to the second electrode of the third transistor M3, and the second electrode of the second emission control transistor M5 is connected to the light-emitting element L2. The gate of the third emission control transistor M6 is connected to the emission control signal line EM3 to receive a corresponding emission control signal. The first electrode of the third emission control transistor M6 is connected to the second electrode of the third transistor M3, and the second electrode of the third emission control transistor M6 is connected to the light-emitting element L3. The gate of the fourth emission control transistor M7 is connected to the emission control signal line EM4 to receive a corresponding emission control signal. The first electrode of the fourth emission control transistor M7 is connected to the second electrode of the third transistor M3, and the second electrode of the fourth emission control transistor M7 is connected to the light-emitting element L4.

[0102] For example, the light-emitting elements L1-L4 are also connected to the second voltage terminal ELVSS. For example, the light-emitting elements L1-L4 belong to four different pixel units 20, and these four pixel units 20 belong to the same pixel unit group. In other words, the pixel circuit 30 is used to drive the four light-emitting elements L1-L4 in a group of pixel units 20.

[0103] Thus, the pixel circuit 30 realizes capacitor multiplexing, so that one storage capacitor C1 corresponds to multiple pixel units 20. In a conventional pixel circuit, one data writing transistor, one driving transistor, and one storage capacitor correspond to one light-emitting element. In the embodiment of the present disclosure, the transistors M1, M2, M3, and the storage capacitor C1 correspond to N (for example, N ≥ 2) light-emitting elements, and these N light-emitting elements are controlled by their respective corresponding light-emitting control transistors. Therefore, in the area occupied by the N pixel units 20 on the substrate 10, only one capacitor needs to be set, thereby increasing the area of ​​the capacitor and facilitating the voltage maintenance of the capacitor.

[0104] It should be noted that in the embodiments of the present disclosure, the pixel circuit 30 can also adopt any other applicable circuit structure, for example, it can include more components and structures, for example, it can also include a circuit for implementing internal compensation, etc., which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this. For example, in other examples, the pixel circuit 30 can also be implemented as the circuit structure shown in Figure 5B. For example, as shown in Figure 5B, the data write circuit can be implemented as transistors T4-T7, and the storage circuit can be implemented as capacitors C3 and C4. The pixel circuit also includes a reset circuit, and the reset circuit is implemented as transistor T8. It should be noted that the sensing circuit is not shown in Figure 5B. The setting method of the sensing circuit can refer to the circuit structure shown in Figure 5A. For example, any one of the transistors T4-T7 can be equivalent to the first transistor M1 described above, and any one of the capacitors C3 and C4 can be equivalent to the storage capacitor C1 described above. The pixel circuit can drive the four light-emitting elements L1-L4 in a group of pixel units 20.

[0105] FIG6 is a plan view of the layer structure of a display substrate provided in some embodiments of the present disclosure. As shown in FIG6 , the storage capacitor C1 includes two stacked capacitor plates, for example, a first capacitor plate C11 and a second capacitor plate C12. The orthographic projection of at least one of the two capacitor plates on the base substrate 10 at least partially covers the orthographic projection of the first transistor M1 on the base substrate 10 and at least partially covers the orthographic projection of the second transistor M2 on the base substrate 10. For example, only the orthographic projection of the first capacitor plate C11 may at least partially cover the orthographic projection of the first transistor M1 on the base substrate 10 and at least partially cover the orthographic projection of the second transistor M2 on the base substrate 10, or only the orthographic projection of the second capacitor plate C12 may at least partially cover the orthographic projection of the first transistor M1 on the base substrate 10 and at least partially cover the orthographic projection of the second transistor M2 on the base substrate 10, or both the orthographic projections of the first capacitor plate C11 and the second capacitor plate C12 may at least partially cover the orthographic projection of the first transistor M1 on the base substrate 10 and at least partially cover the orthographic projection of the second transistor M2 on the base substrate 10. Here, “orthographic projection” refers to a projection in a direction perpendicular to the base substrate 10. For example, “at least partially covering” can mean partial covering or full covering, and as long as there is overlap, it can be considered as at least partial covering.

[0106] For example, the orthographic projection of the first transistor M1 on the substrate 10 includes at least the orthographic projection of the active layer of the first transistor M1 on the substrate 10. That is, the orthographic projection of the first transistor M1 can be the orthographic projection of the active layer of the first transistor M1, and the orthographic projection of the first transistor M1 can also further include the orthographic projections of its gate, source, and drain on the basis of including the orthographic projection of its active layer. Similarly, the orthographic projection of the second transistor M2 on the substrate 10 includes at least the orthographic projection of the active layer of the second transistor M2 on the substrate 10. That is, the orthographic projection of the second transistor M2 can be the orthographic projection of the active layer of the second transistor M2, and the orthographic projection of the second transistor M2 can also further include the orthographic projections of its gate, source, and drain on the basis of including the orthographic projection of its active layer.

[0107] Since the signal transmitted by the first transistor M1 (e.g., a data signal) and the signal transmitted by the second transistor M2 (e.g., a sensing signal) are generally transition signals, by making the positive projection of the capacitor plate of the storage capacitor C1 at least partially cover the positive projection of the first transistor M1 and the second transistor M2, the capacitor plate can be used to shield or weaken the influence of the pixel circuit 30 on the light-emitting element (e.g., an OLED), thereby improving the display quality.

[0108] For example, in some examples, the orthographic projection of at least one of the two capacitor plates of the storage capacitor C1 on the substrate substrate 10 at least partially covers the orthographic projection of the third transistor M3 on the substrate substrate 10. For example, the orthographic projection of the third transistor M3 on the substrate substrate 10 at least includes the orthographic projection of the active layer of the third transistor M3 on the substrate substrate 10. That is, the orthographic projection of the third transistor M3 can be the orthographic projection of the active layer of the third transistor M3, and the orthographic projection of the third transistor M3 can also further include the orthographic projection of its gate, source, and drain on the basis of including the orthographic projection of its active layer. Thus, the capacitor plate can be used to further shield or weaken the influence of the pixel circuit 30 on the light-emitting element, thereby improving the display quality.

[0109] For example, in some examples, the orthographic projection of at least one of the two capacitor plates of the storage capacitor C1 on the base substrate 10 at least partially covers the orthographic projection of the light-emitting control transistor on the base substrate 10. The light-emitting control transistor that is at least partially covered can be any one or more of the first light-emitting control transistor M4, the second light-emitting control transistor M5, the third light-emitting control transistor M6, and the fourth light-emitting control transistor M7. Thus, the capacitor plates can be used to further shield or reduce the impact of the pixel circuit 30 on the light-emitting element, thereby improving display quality.

[0110] Figures 7A to 11B respectively illustrate plan views of wiring layers of the display substrate shown in Figure 6. Figure 7A is a plan view of an active layer of a display substrate provided in some embodiments of the present disclosure, Figure 7B is a plan view of a gate layer of a display substrate provided in some embodiments of the present disclosure, Figure 7C is a plan view of the layer structures of Figures 7A and 7B superimposed, Figure 8A is a plan view of an injection layer of a display substrate provided in some embodiments of the present disclosure, Figure 8B is a plan view of a first metal layer of a display substrate provided in some embodiments of the present disclosure, Figure 8C is a plan view of the layer structures of Figures 7C, 8A, and 8B superimposed, Figure 9A is a plan view of a second metal layer of a display substrate provided in some embodiments of the present disclosure, Figure 9B is a plan view of the layer structures of Figures 9A and 8C superimposed, and Figure 1 0A is a plan view of the third metal layer of the display substrate provided in some embodiments of the present disclosure, Figure 10B is a plan view of the fourth metal layer of the display substrate provided in some embodiments of the present disclosure, Figure 10C is a plan view of the fifth metal layer of the display substrate provided in some embodiments of the present disclosure, Figure 10D is a plan view of the sixth metal layer of the display substrate provided in some embodiments of the present disclosure, Figure 10E is a plan view of the layer structure of Figure 9B and Figures 10A to 10D superimposed, Figure 11A is a plan view of the storage capacitor of the display substrate provided in some embodiments of the present disclosure, and Figure 11B is a plan view of the capacitor transfer electrode layer in the storage capacitor of the display substrate provided in some embodiments of the present disclosure.

[0111] The following briefly describes the various layer structures of the display substrate 100 in conjunction with the plan views shown in Figures 6 and 7A to 11B. It should be noted that the plan views shown in Figures 6 and 7A to 11B only illustrate components and structures relevant to the embodiments of the present disclosure. Other components and structures not shown can refer to conventional designs and will not be described in detail here. Furthermore, the components and structures shown in Figures 6 and 7A to 11B are merely schematic and non-restrictive, and do not constitute a limitation on the embodiments of the present disclosure.

[0112] It should be noted that in the description below, G1, G2, Vd, Se, ELVDD, ELVSS, EM1, EM2, EM3, EM4, etc. are used to represent corresponding signal terminals or signal lines, as well as corresponding signals or levels. The following embodiments are the same and will not be repeated here.

[0113] As shown in Figures 7A-7C, the first transistor M1 includes an active layer M11, a gate M12, a first electrode M13 and a second electrode M14; the second transistor M2 includes an active layer M21, a gate M22, a first electrode M23 and a second electrode M24; the third transistor M3 includes an active layer M31, a gate M32, a first electrode M33 and a second electrode M34; the first light-emitting control transistor M4 includes an active layer M41, a gate M42, a first electrode M43 and a second electrode M44; the second light-emitting control transistor M5 includes an active layer M51, a gate M52, a first electrode M53 and a second electrode M54; the third light-emitting control transistor M6 includes an active layer M61, a gate M62, a first electrode M63 and a second electrode M64; and the fourth light-emitting control transistor M7 includes an active layer M71, a gate M72, a first electrode M73 and a second electrode M74.

[0114] The orthographic projection of the first transistor M1 and the orthographic projection of the second transistor M2 on the substrate 10 are located on both sides of the orthographic projection of the third transistor M3 on the substrate 10. As described above, the orthographic projection of the first transistor M1 on the substrate 10 includes at least the orthographic projection of the active layer M11 of the first transistor M1 on the substrate 10. Similarly, the orthographic projection of the second transistor M2 on the substrate 10 includes at least the orthographic projection of the active layer M21 of the second transistor M2 on the substrate 10. The orthographic projection of the third transistor M3 on the substrate 10 includes at least the orthographic projection of the active layer M31 of the third transistor M3 on the substrate 10.

[0115] The first emission control transistor M4, the second emission control transistor M5, the third emission control transistor M6, and the fourth emission control transistor M7 are distributed along a first direction, which is, for example, the X direction. The first via H1 connected to the gate M42 of the first emission control transistor M4, the second via H2 connected to the gate M52 of the second emission control transistor M5, the third via H3 connected to the gate M62 of the third emission control transistor M6, and the fourth via H4 connected to the gate M72 of the fourth emission control transistor M7 are not located on the same straight line extending along the first direction. For example, in the example shown in FIG7C , the first via H1, the second via H2, the third via H3, and the fourth via H4 are located on two straight lines extending along the first direction: the first via H1 and the third via H3 are located on one straight line, and the second via H2 and the fourth via H4 are located on another straight line.

[0116] For example, the first electrode M43 and the second electrode M44 of the first emission control transistor M4, the first electrode M53 and the second electrode M54 of the second emission control transistor M5, the first electrode M63 and the second electrode M64 of the third emission control transistor M6, and the first electrode M73 and the second electrode M74 of the fourth emission control transistor M7 are all located on the same extension line extending along a first direction (e.g., the X direction). The first via H1, the second via H2, the third via H3, and the fourth via H4 are alternately located on either side of this extension line. In this manner, routing is facilitated and the length of the gate lines connected to each gate is reduced.

[0117] For example, the gate M12 of the first transistor M1, the gate M22 of the second transistor M2, and the gate M32 of the third transistor M3 are located on the same distribution line extending along a first direction (e.g., the X direction). This distribution line is parallel to the extension line and has a gap therebetween. That is, the first transistor M1, the second transistor M2, and the third transistor M3 are roughly located in one row, while the first emission control transistor M4, the second emission control transistor M5, the third emission control transistor M6, and the fourth emission control transistor M7 are roughly located in another row. For example, the low-voltage transfer electrode A11 extends along the first direction and is spaced apart from each of the transistors.

[0118] As shown in Figures 8A-8C, the orthographic projection of the P-type injection layer SP on the base substrate 10 covers the orthographic projection of the low-voltage transfer electrode A11 on the base substrate 10. The orthographic projection of the N-type injection layer SN on the base substrate 10 covers the orthographic projection of each transistor on the base substrate 10. The transfer electrode A31 is used to connect the first voltage line ELVDD and the capacitor plate to be formed later. The transfer electrode A32 is used to connect the data line Vd to be formed later. The transfer electrode 33 is used to connect the first scan line G1 to be formed later. The transfer electrode 34 is used to connect the sensing signal line Se to be formed later. The transfer electrode 35 is used to connect the second scan line G2 to be formed later. The second voltage line ELVSS covers the low-voltage transfer electrode A11 and is connected through a via to transmit a low-voltage signal.

[0119] The first adapter wire A21, the second adapter wire A22, the third adapter wire A23, and the fourth adapter wire A24 are respectively used to connect each light-emitting control transistor to a corresponding light-emitting element. For example, the first light-emitting control transistor M4 is connected to the corresponding light-emitting element via the first adapter wire A21, the second light-emitting control transistor M5 is connected to the corresponding light-emitting element via the second adapter wire A22, the third light-emitting control transistor M6 is connected to the corresponding light-emitting element via the third adapter wire A23, and the fourth light-emitting control transistor M7 is connected to the corresponding light-emitting element via the fourth adapter wire A24.

[0120] For example, the lengths of the current paths between the second and third emission control transistors M5 and M6 and their corresponding light-emitting elements are greater than the lengths of the current paths between the first and fourth emission control transistors M4 and M7 and their corresponding light-emitting elements. In other words, the lengths of the second and third patch cords A22 and A23 are greater than the lengths of the first and fourth patch cords A21 and A24. For example, the length of either the second and third patch cords A22 and A23 is greater than the lengths of either the first and fourth patch cords A21 and A24. Here, the length of the first patch cord A21 is equal to the length of the current path between the first emission control transistor M4 and its corresponding light-emitting element, the length of the second patch cord A22 is equal to the length of the current path between the second emission control transistor M5 and its corresponding light-emitting element, the length of the third patch cord A23 is equal to the length of the current path between the third emission control transistor M6 and its corresponding light-emitting element, and the length of the fourth patch cord A24 is equal to the length of the current path between the fourth emission control transistor M7 and its corresponding light-emitting element.

[0121] For example, the first adapter cable A21 and the fourth adapter cable A24 are axially symmetrically distributed. For example, the second adapter cable A22 and the third adapter cable A23 are axially symmetrically distributed. For example, the axis of symmetry between the first adapter cable A21 and the fourth adapter cable A24 and the axis of symmetry between the second adapter cable A22 and the third adapter cable A23 are the same axis of symmetry.

[0122] For example, the first patch cable A21, the second patch cable A22, the third patch cable A23, and the fourth patch cable A24 are all L-shaped. For example, the L-shaped cable includes a first segment extending along a first direction (e.g., the X direction) and a second segment extending along a second direction (e.g., the Y direction), where the second direction is perpendicular to the first direction. As shown in FIG8B , the first patch cable A21 includes a first segment A21a and a second segment A21b, the second patch cable A22 includes a first segment A22a and a second segment A22b, the third patch cable A23 includes a first segment A23a and a second segment A23b, and the fourth patch cable A24 includes a first segment A24a and a second segment A24b.

[0123] For example, the lengths of the first section A22a of the second adapter line A22 and the first section A23a of the third adapter line A23 are equal and both are the first length, the lengths of the first section A21a of the first adapter line A21 and the first section A24a of the fourth adapter line A24 are equal and both are the second length, and the first length is greater than the second length.

[0124] For example, the orthographic projections of the first segments A21a, A22a, A23a, and A24a on the base substrate 10 do not overlap with the orthographic projections of the capacitor plates C11 and C12 on the base substrate 10. The orthographic projections of the second segments A21b, A22b, A23b, and A24b on the base substrate 10 overlap with the orthographic projections of the capacitor plates C11 and C12 on the base substrate 10.

[0125] For example, the first adapter cable A21 is connected to the corresponding light-emitting element via the fifth via H5, which is located in the first section A21a of the first adapter cable A21. The second adapter cable A22 is connected to the corresponding light-emitting element via the sixth via H6, which is located in the first section A22a of the second adapter cable A22. The third adapter cable A23 is connected to the corresponding light-emitting element via the seventh via H7, which is located in the first section A23a of the third adapter cable A23. The fourth adapter cable A24 is connected to the corresponding light-emitting element via the eighth via H8, which is located in the first section A24a of the fourth adapter cable A24.

[0126] Through the above layout setting, signal interference can be effectively reduced, signal delay can be reduced, processing difficulty can be reduced, and reliability can be improved.

[0127] As shown in Figures 9A-9B, the first light-emitting control signal line EM1, the second light-emitting control signal line EM2, the third light-emitting control signal line EM3, and the fourth light-emitting control signal line EM4 are respectively connected to the gate M42 of the first light-emitting control transistor M4, the gate M52 of the second light-emitting control transistor M5, the gate M62 of the third light-emitting control transistor M6, and the gate M72 of the fourth light-emitting control transistor M7 to transmit light-emitting control signals respectively.

[0128] As shown in Figures 10A-10E, the data line Vd and the sensing signal line Se are spaced apart from each other and extend along a second direction on the base substrate 10, the second direction being perpendicular to the first direction. For example, the first direction is the X direction, and the second direction is the Y direction. The orthogonal projections of the data line Vd and the sensing signal line Se on the base substrate 10 are located on either side of the orthogonal projection of the third transistor M3 on the base substrate 10. The orthogonal projection of the data line Vd on the base substrate 10 is located between the orthogonal projections of the first transistor M1 and the third transistor M3 on the base substrate 10. The orthogonal projection of the sensing signal line Se on the base substrate 10 is located between the orthogonal projections of the second transistor M2 and the third transistor M3 on the base substrate 10.

[0129] For example, transition electrodes A41, A42, A43, and A44 are stacked in different film layers and electrically connected in sequence, thereby connecting the second electrode M74 of the fourth light-emitting control transistor M7 to the light-emitting element L4 stacked on the transition electrode A44. Light-emitting elements L1, L2, and L3 are also connected to the corresponding light-emitting control transistors in a similar manner.

[0130] For example, the switching electrodes A45, A46, A47, and A48 are stacked in different film layers and electrically connected in sequence, thereby connecting the first electrode M33 of the third transistor M3 to the second capacitor plate C12 of the storage capacitor C1, and also connecting the first electrode M33 of the third transistor M3 to the first voltage line ELVDD. The switching electrodes A51, A52, A53, and A54 are stacked in different film layers and electrically connected in sequence, thereby connecting the gate M32 of the third transistor M3 to the first capacitor plate C11 of the storage capacitor C1.

[0131] For example, the first scan line G1 and the second scan line G2 extend substantially along the first direction and are connected to the gate M12 of the first transistor M1 and the gate M22 of the second transistor M2, respectively. The first voltage line ELVDD extends along the first direction and is connected to the switching electrode A48.

[0132] As shown in Figures 11A-11B, the storage capacitor C1 is a MIM capacitor, also known as a plate capacitor. The two capacitor plates of the storage capacitor C1 include a first capacitor plate C11 and a second capacitor plate C12. The orthographic projection of the second capacitor plate C12 on the base substrate 10 covers the orthographic projection of the first capacitor plate C11 on the base substrate 10. For example, the layer structure shown in Figures 11A-11B is arranged on the layer structure shown in Figure 10E.

[0133] The first capacitor plate C11 is connected to the first transfer electrode TM1 through the first set of vias TV1. The orthographic projection of the first transfer electrode TM1 on the base substrate 10 and the orthographic projection of the first set of vias TV1 on the base substrate 10 are both located within the orthographic projection of the first capacitor plate C11 on the base substrate 10.

[0134] The second capacitor plate C12 is connected to the second transfer electrode TM2 through a second set of vias TV2. The orthographic projection of the second transfer electrode TM2 on the base substrate 10 and the orthographic projection of the second set of vias TV2 on the base substrate 10 are both located within the orthographic projection of the second capacitor plate C12 on the base substrate 10, and do not overlap with the orthographic projection of the first capacitor plate C11 on the base substrate 10. A gap exists between the orthographic projection of the second transfer electrode TM2 on the base substrate 10 and the orthographic projection of the first capacitor plate C11 on the base substrate 10.

[0135] For example, the transfer electrodes A61, A62, A63, and A64 are used to respectively connect the light-emitting elements L1-L4 to other transfer electrodes below the transfer electrodes A61, A62, A63, and A64.

[0136] It should be noted that one or more insulating layers may be provided between the various layer structures shown in FIG. 6 and FIG. 7A to FIG. 11B as required. The provision of the insulating layers may refer to conventional designs and will not be described in detail here.

[0137] In the embodiment of the present disclosure, the pixel circuit 30 implements capacitor multiplexing, so that one storage capacitor C1 corresponds to multiple pixel units 20. In the area occupied by the multiple pixel units 20 on the substrate 10, only one capacitor needs to be set, thereby increasing the area of ​​the capacitor, which is beneficial to maintaining the voltage of the capacitor. In addition, since the signal transmitted by the first transistor M1 (e.g., a data signal) and the signal transmitted by the second transistor M2 (e.g., a sensing signal) are generally transitional signals, by making the positive projection of the capacitor plate of the storage capacitor C1 at least partially cover the positive projection of the first transistor M1 and the second transistor M2, the capacitor plate can be used to shield or weaken the effect of the pixel circuit 30 on the light-emitting element (e.g., an OLED), thereby improving the display quality.

[0138] It should be noted that the transistors used in the embodiments of the present disclosure may all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used herein may be symmetrical in structure, so their source and drain structures may be identical. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0139] In addition, the transistors in the embodiments of the present disclosure are all described by taking N-type transistors as an example. In this case, the first electrode of the transistor is the drain electrode and the second electrode is the source electrode. It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the display substrate 100 provided in the embodiments of the present disclosure may also adopt P-type transistors. In this case, the first electrode of the transistor is the source electrode and the second electrode is the drain electrode. It is only necessary to connect the electrodes of the selected type of transistors with reference to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and make the corresponding voltage terminals provide the corresponding high voltage or low voltage. When an N-type transistor is used, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (such as hydrogenated amorphous silicon) as the active layer of the transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0140] In the embodiments of the present disclosure, the term "operating level" refers to a level at which a corresponding transistor is turned on, and the term "non-operating level" refers to a level at which a corresponding transistor is turned off. For example, the operating level may also be referred to as an active level, and the non-operating level may also be referred to as an inactive level.

[0141] At least one embodiment of the present disclosure further provides a display device. The pixel circuit in the display device implements capacitor multiplexing, so that one storage capacitor corresponds to multiple pixel units. Only one capacitor is required within the area occupied by the multiple pixel units on the substrate. This increases the capacitor area, facilitates capacitor voltage maintenance, and thus improves display quality.

[0142] FIG12 is a schematic block diagram of a display device provided by some embodiments of the present disclosure. As shown in FIG12 , the display device 200 includes a display substrate 100, which is the display substrate provided by any embodiment of the present disclosure. For example, the display device 200 can be any product or component with a display function, such as a smart wearable device, a virtual reality device, an augmented reality device, a television, a monitor, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto. The technical effects of the display device 200 can refer to the corresponding description of the display substrate 100 in the above embodiments and will not be repeated here.

[0143] At least one embodiment of the present disclosure further provides a method for driving a display substrate, which is used to drive the display substrate provided by any embodiment of the present disclosure. Utilizing this method can facilitate capacitor voltage maintenance, thereby improving display quality.

[0144] Figure 13 is a schematic flow chart of a method for driving a display substrate provided in some embodiments of the present disclosure. As shown in Figure 13, in some embodiments, the driving method includes the following operations.

[0145] Step S10: In the Pth stage of the display stage, a first scanning signal that is shifted in sequence is provided to multiple rows of pixel units on the display substrate, and the Pth light-emitting control signal of each row of pixel units is made to be at an operating level, and the light-emitting control signals other than the Pth light-emitting control signal of at least two light-emitting control signals of each row of pixel units are made to be at a non-operating level, so as to realize row-by-row scanning of the Pth pixel unit in each group of pixel units in the Pth stage, where 1≤P≤N and P is an integer.

[0146] For example, each group of pixel units includes at least two pixel units including the 1st to Nth pixel units, the above-mentioned at least two light-emitting control signals include the 1st to Nth light-emitting control signals, a frame display stage includes the first stage to the Nth stage, and N is a positive integer.

[0147] For example, in each of the first to Nth phases, the first scanning signal corresponding to the same row of pixel units has a pulse waveform having an operating level. In the display phase, the number of pulse waveforms of the first scanning signal corresponding to the same row of pixel units is N. That is, in one display phase, the first scanning signal corresponding to the same row of pixel units is turned on a total of N times.

[0148] For example, in some examples, the driving method may further include the following operations.

[0149] Step S20: In the blanking phase, at least two light emitting control signals of each row of pixel units are set to non-operating levels, and the first scanning signal and the second scanning signal of the target row of pixel units are set to operating levels. The target row of pixel units are pixel units that need to be detected.

[0150] FIG14 is a driving timing diagram of a display substrate provided in some embodiments of the present disclosure.

[0151] For example, in this example, the pixel resolution of the display substrate 100 is 4000*2000. For example, assuming a refresh rate of 90Hz, the time for one frame is 11.1ms. In one frame, 10ms is used for display light emission, and 1.1ms is used as a blanking phase for compensation sensing. For example, this timing sequence is used to drive the display substrate 100 shown in Figures 2 to 5A. In this display substrate 100, each pixel unit 20 is grouped into four groups, and each pixel circuit 30 drives a corresponding group of pixel units 20.

[0152] As shown in FIG14 , during 1 / 4 of the display phase of each frame, that is, during the first phase, the first scanning signal G1 of row 1 is at an active level (e.g., a high level), and row 1 receives 1000 data signals. Since each group of four pixel units 20 shares a pixel circuit 30, only 1000 data lines are required, even though the resolution is 4000*2000. At this point, all first light-emitting control signals EM1 in the pixel units 20 of row 1 are at an active level, while the second light-emitting control signals EM2, third light-emitting control signals EM3, and fourth light-emitting control signals EM4 are all at an inactive level. The first pixel unit 20 of each group of pixel units 20 emits light (a total of 1000 pixel units 20 emit light, while the other pixel units 20 in the same row are temporarily non-emitting light).

[0153] Then, the first scanning signal G1 of the second row is at an active level, the first light-emitting control signal EM1 of the second row is at an active level, and the first pixel unit 20 of each group of pixel units 20 in the second row (a total of 1000) begins to emit light. A similar process is used until the first scanning signal G1 of the 2000th row is at an active level, and then the first light-emitting control signal EM1 of the 2000th row is at an active level, and the first pixel unit 20 of each group of pixel units 20 in the 2000th row (a total of 1000) begins to emit light. Thus, in the first stage, row-by-row scanning of the first pixel unit 20 in each group of pixel units 20 is achieved.

[0154] During the 1 / 4 to 1 / 2 time of each frame's display phase, that is, during the second phase, the first scanning signal G1 of row 2000 becomes low at the same time that the first scanning signal G1 of row 1 becomes active (e.g., high), and row 1 receives 1000 data signals. At this point, all second emission control signals EM2 in the pixel units 20 of row 1 are active, while the first emission control signal EM1, the third emission control signal EM3, and the fourth emission control signal EM4 are all inactive. The second pixel unit 20 in each group of pixel units 20 emits light (a total of 1000 pixel units 20 emit light, while the other pixel units 20 in the same row are temporarily silent).

[0155] Then, the first scanning signal G1 of the second row is at an active level, the second light-emitting control signal EM2 of the second row is at an active level, and the second pixel unit 20 of each group of pixel units 20 in the second row (a total of 1000) begins to emit light. A similar process is used until the first scanning signal G1 of the 2000th row is at an active level, and then the second light-emitting control signal EM2 of the 2000th row is at an active level, and the second pixel unit 20 of each group of pixel units 20 in the 2000th row (a total of 1000) begins to emit light. Thus, in the second stage, row-by-row scanning of the second pixel unit 20 in each group of pixel units 20 is achieved.

[0156] During the 1 / 2 to 3 / 4 display phase of each frame, that is, during the third phase, the first scanning signal G1 of row 2000 becomes low at the same time that the first scanning signal G1 of row 1 becomes active (e.g., high), and row 1 receives 1000 data signals. At this point, all third emission control signals EM3 ​​in the pixel units 20 of row 1 are active, while the first emission control signal EM1, the second emission control signal EM2, and the fourth emission control signal EM4 are all inactive. The third pixel unit 20 in each group of pixel units 20 emits light (a total of 1000 pixel units 20 emit light, while the other pixel units 20 in the same row are temporarily silent).

[0157] Then, the first scanning signal G1 of the second row is at an active level, the third light-emitting control signal EM3 of the second row is at an active level, and the third pixel unit 20 of each group of pixel units 20 in the second row (a total of 1000) begins to emit light. A similar process is used until the first scanning signal G1 of the 2000th row is at an active level, and then the third light-emitting control signal EM3 of the 2000th row is at an active level, and the third pixel unit 20 of each group of pixel units 20 in the 2000th row (a total of 1000) begins to emit light. Thus, in the third stage, row-by-row scanning of the third pixel unit 20 in each group of pixel units 20 is achieved.

[0158] During the period from ¾ to 1 of the display phase of each frame, that is, during the fourth phase, the first scanning signal G1 of the 2000th row becomes low, while the first scanning signal G1 of the 1st row becomes active again (e.g., high), and the 1000th data signal is received by the 1st row. At this time, all the fourth emission control signals EM4 in the pixel units 20 of the 1st row are active, while the first emission control signals EM1, the second emission control signals EM2, and the third emission control signals EM3 ​​are all inactive. The fourth pixel unit 20 in each group of pixel units 20 emits light (a total of 1000 pixel units 20 emit light, while the other pixel units 20 in the same row are temporarily silent).

[0159] Then, the first scanning signal G1 of the second row is at an active level, the fourth light-emitting control signal EM4 of the second row is at an active level, and the fourth pixel unit 20 of each group of pixel units 20 in the second row (a total of 1000) begins to emit light. A similar process is used until the first scanning signal G1 of the 2000th row is at an active level, and then the fourth light-emitting control signal EM4 of the 2000th row is at an active level, and the fourth pixel unit 20 of each group of pixel units 20 in the 2000th row (a total of 1000) begins to emit light. Thus, in the fourth stage, row-by-row scanning of the fourth pixel unit 20 in each group of pixel units 20 is achieved.

[0160] In the embodiment of the present disclosure, during the display phase of a frame, the first scan signal G1 of each row is turned on four times, each time corresponding to the activation of a different light-emitting control signal. Only one-quarter of the pixel units 20 in the same row are simultaneously illuminated. The first scan signal G1 of each row can be generated by shifting, and the light-emitting control signal of each row can also be generated by shifting. For example, in some examples, if intelligent display is required, the first scan signal G1 and the corresponding light-emitting control signal can be turned on for any row to achieve intelligent display.

[0161] For example, in the blanking phase, if compensation sensing is required for a certain row, the light emitting control signals of the pixel units 20 in each row are all set to a non-operating level, and the first scanning signal G1 and the second scanning signal G2 of the pixel units 20 in the target row (i.e., the row to be sensed) are set to an operating level (i.e., an effective level), thereby achieving compensation sensing. For example, the pixel units 20 in the target row are the pixel units 20 to be detected.

[0162] It should be noted that the above embodiment is described by taking the example of each group of pixel units 20 including four pixel units 20, but this does not constitute a limitation on the embodiments of the present disclosure. When the number of pixel units 20 included in each group of pixel units 20 is other values, such as 2, 3, 5, etc., the display stage is also correspondingly divided into 2 stages, 3 stages, or 5 stages. This can be determined according to actual needs and is not limited in the embodiments of the present disclosure. The technical effects of this driving method can be referred to the corresponding description of the display substrate 100 in the above embodiment, and will not be repeated here.

[0163] At least one embodiment of the present disclosure further provides a source driver circuit that can reduce the number of digital-to-analog converters, effectively reduce the occupied area, lower production costs, and is applicable to various pixel circuits.

[0164] For high-PPI displays, source-level drivers present numerous challenges. For example, with a display substrate with a resolution of 4000 x 2000, for large-scale OLED displays, since the source driver and pixel unit are separate, the issue of excessive channels can be addressed by allocating multiple source drivers. However, for silicon-based OLED display substrates, the source driver and pixel unit are fabricated on the same device, eliminating the need for packaging. However, a resolution of 4000 x 2000 requires 4000 channels, necessitating 4000 digital-to-analog converters (DACs) and buffers. DACs and buffers typically occupy approximately 70% of the source driver chip area. Designing 4000 DACs and buffers on a silicon substrate would undoubtedly significantly increase the driver component's footprint, potentially eclipsing the display area (AA area), which would be unsuitable for production and user needs. Furthermore, 4000 DACs and buffers not only increase the footprint but also exponentially increase power consumption. For silicon-based microdisplays, power consumption is one of the core indicators, especially for high PPI displays, which need to reduce power consumption and cannot accept high power consumption.

[0165] In response to the above problems, an embodiment of the present disclosure provides a source driver circuit. Figure 15 is a schematic diagram of a source driver circuit provided by some embodiments of the present disclosure. As shown in Figure 15, the number of DACs is reduced by adopting a multiplexer (MUX). Taking a display substrate with a resolution of 4000*2000 as an example, the number of DACs and buffers required is 200. By increasing the number of MUXs to reduce the occupied area, the output requirement of 4000 channels can be met. For example, each MUX is connected to 20 channels, and each MUX is a 1:20 multiplexer. Thus, the output of 4000 channels can be achieved using 200 MUXs.

[0166] For example, as shown in Figure 15, the shift register and latch have the same circuit structure as a conventional source driver. The difference is that the conventional source driver only turns on the STB signal once per row and transmits one row of data each time. In the source driving circuit provided in the embodiment of the present disclosure, the STB signal per row is turned on multiple times, thereby correspondingly transmitting multiple rows of data.

[0167] For example, for a 4000*2000 display substrate, the latch releases 40,000 bits of data each time (assuming the DAC is 10 bits). If the pixel circuit shown in Figure 1 is used, then within the time of a row scan, the STB signal is turned on 20 times, and 2000 bits of data are transmitted each time. The DAC needs to undergo 20 conversions, each time through a 1:20 MUX to output the data signal to the corresponding channel. 200 data signals are generated each time, and a total of 4000 data signals are generated 20 times, thereby providing the data signals required for all pixel units in a row. In this case, the pixel units in the same row write data signals at the same time and emit light at the same time.

[0168] If the pixel circuit 30 shown in FIG5A is used, data needs to be written to 1 / 4 of the pixel cells in a row during a row scan, while data does not need to be written to the remaining 3 / 4 of the pixel cells during this scan. Therefore, the STB signal is turned on five times, each time transmitting 2000 bits. The DAC needs to undergo five conversions, each time outputting data signals to the corresponding channel through a 1:5 MUX, generating 200 data signals each time, and a total of 1000 data signals in five conversions, thereby providing the data signals required by 1 / 4 of the pixel cells in a row.

[0169] At least one embodiment of the present disclosure further provides a current regulation method that can dynamically adjust the current in real time, effectively reducing power consumption and facilitating system integration.

[0170] Low-power designs typically reduce power consumption by controlling the buffer current, but these typically operate in relatively fixed modes. For example, the buffer current can be regulated to 100% in normal display mode and 80% in energy-saving mode. Alternatively, the current may be higher when writing data and lower when no data is needed. While these approaches can reduce power consumption to a certain extent, the extent of this reduction is limited.

[0171] In response to the above problems, an embodiment of the present disclosure provides a current regulation method, which can dynamically regulate current, effectively reduce power consumption, facilitate system integration, and improve reliability.

[0172] Figure 16 is a schematic diagram of a display driver architecture provided in some embodiments of the present disclosure. As shown in Figure 16, the control system provides control signals CM<0:2> to the current adjustment unit to adjust the bias current Bias. For example, the control signals CM<0:2> can be 3-bit signals. By adjusting the bias current Bias using these control signals, the buffer current is controlled, thereby reducing power consumption.

[0173] For example, the control system pre-stores the data signals of two rows of pixel units (such as the current row and the next row), and determines the value of the control signal CM<2:0> by comparing the average brightness of each row of the two rows of pixel units and the maximum difference between the data signals at the same position. For example, in some examples, the current can be divided into 8 levels, and the difference between each level is equal (assuming a change from 1μA to 8μA). If the average brightness of the two adjacent rows of pixel units is the same and the maximum difference of the data signal at the same position is almost 0, the current size of the current row is maintained as the current size of the next row. If the average brightness of the two adjacent rows of pixel units is very different, and the maximum difference of the data signal at the same position is large (for example, from the lowest grayscale to the highest grayscale), the current of the next row is dynamically adjusted to 8μA. The current size in other cases can take the middle range value according to the specific situation. As a result, the current required by each row of pixel units is the optimal value actually needed at the moment, thereby avoiding wasteful power consumption and effectively reducing power consumption.

[0174] At least one embodiment of the present disclosure further provides a sensing circuit and sensing method. Utilizing such a sensing circuit and sensing method, problems such as poor compensation due to charge sharing and capacitance deviation can be resolved, thereby reducing compensation errors and improving display effects.

[0175] Figure 17 is a schematic diagram of a sensing circuit provided by some embodiments of the present disclosure. As shown in Figure 17, taking the display substrate with a resolution of 4000*2000 as an example, assuming that the pixel circuit shown in Figure 1 is used, 4000 sensing signal lines Se are required at this time. In order to save power consumption, only one analog-to-digital converter (ADC) can be used, so 4000 sampling and holding circuits are required. For example, during sensing, the signal SW0<1:4000> is turned on at the same time, and the signals of the 4000 sensing signal lines Se are all collected into the corresponding sampling and holding circuits. The signal SW1<1:4000> is turned on in sequence, so that multiple signals are output through the ADC in sequence.

[0176] FIG18 is a comparison diagram of the sensing timing provided by some embodiments of the present disclosure. As shown in FIG18 , in a driving method, the timing provided to the sensing circuit is the first timing. In the first timing, after the first scanning signal G1 becomes an effective level, the data signal charges the storage capacitor of the pixel circuit, and the anode voltage of the light-emitting element gradually increases. Due to the effect of the parasitic capacitance on the sensing signal line Se (for example, on the order of 1 pf, and there are differences between different sensing signal lines Se), the anode of the light-emitting element eventually stabilizes at a fixed value (assuming it is 2V). At this time, the signal SW0<1:4000> is turned on, and the size of the sampling capacitor C2 is also on the order of 1 pf. Since too large a sampling capacitor C2 will increase the charging time and increase the chip area, too small a sampling capacitor C2 is not conducive to maintaining a stable sampling voltage. Therefore, the sampling capacitor C2 is usually set at the order of 1 pf.

[0177] When the signal SW0<1:4000> is turned on, the capacitance on the sensing signal line Se and the sampling capacitor C2 will share charge. Assuming that the capacitance on the sensing signal line Se and the sampling capacitor C2 are both about 1pf, after charge sharing, the voltage on the sampling capacitor C2 is 1V. In fact, the capacitance on different sensing signal lines Se varies and is not equal. Assuming that the first sensing signal line Se <1> The capacitance of the second sensing signal line Se is 1pf. <2> The capacitance of the third sensing signal line Se is 1.2pf. <3> The capacitance of the sampling capacitor C2 is 0.8pf. When the sampling capacitor C2 is all 1pf, after signal SW0<1:4000> is turned on and charge sharing occurs, the corresponding voltages of sampling capacitor C2 are 1V, 1.09V, and 0.89V, respectively. SW1<1:4000> is then turned on sequentially, and the ADC performs conversions in sequence, ultimately producing different digital signals. Originally, the values ​​of these three sensing signal lines should be the same (assuming the threshold voltage remains unchanged and the sensed voltage is always 2V). This shows that parasitic capacitance on the sensing signal line Se directly causes errors in the sensing results.

[0178] In another driving method, a second timing sequence is provided to the sensing circuit, which can solve the aforementioned problem. In the second timing sequence, signal SW0<1:4000> is also turned on simultaneously with the first scan signal G1 becoming active. Thus, if the threshold voltage does not change and the same data signal is provided, the voltage sensed by sampling capacitor C2 is equal, thus avoiding sensing errors caused by differences in parasitic capacitance of sensing signal line Se.

[0179] As for the error in sampling capacitor C2 itself, the error caused by charge sharing can be ignored as long as the ADC's input parasitic capacitance is not of the same order of magnitude. For example, a capacitor calibration sequence can be added to calibrate the capacitor before shipment to overcome the error caused by the deviation of sampling capacitor C2.

[0180] It should be noted that when the signals SW1<1:4000> are turned on sequentially, they cannot overlap with each other, that is, there cannot be two SW1s turned on at the same time to prevent errors caused by charge sharing. In addition, the system error of the ADC itself can be eliminated by calculating the difference. For example, before leaving the factory, the same data signal is provided in one frame, and the sensed data is used as the initial data of the entire display and stored in the system. Each subsequent sensing is compared with the initial data sensed for the first time, for example, the difference is calculated. This difference reflects the aging of the OLED, thereby overcoming the impact of the error of the ADC itself. In this way, the compensation capability can be improved and the display effect can be improved. This sensing circuit is applicable to the pixel circuit shown in Figure 1 and also to the pixel circuit shown in Figure 5A. It is only necessary to adjust the number of sampling and holding circuits accordingly, for example, to make the number of sampling and holding circuits equal to the number of sensing signal lines.

[0181] At least one embodiment of the present disclosure further provides a display substrate and a driving method thereof. The display substrate and driving method thereof achieve independent and simultaneous display of each pixel unit by dividing the pixel unit into display blocks. High-definition display in the gaze area and low-definition display in the non-gaze area are achieved through eye-tracking technology, thereby realizing intelligent display and overcoming the bandwidth limitations faced by high-PPI.

[0182] For high-PPI silicon-based micro-display technology, as the amount of data per frame increases dramatically, the requirements for system bandwidth and algorithms also gradually increase. If hardware performance cannot be significantly improved, Smart View can be used to improve the display effect. That is, using eye tracking technology to locate the human eye's gaze area, the entire display area is divided into a gaze area and a non-gaze area. The gaze area can be displayed in high definition, while the non-gaze area can be displayed in multiple lines at the same time to reduce the resolution. As a result, under the same bandwidth, the gaze area can transmit more data.

[0183] The display substrate provided by the embodiments of the present disclosure can realize partitioning of the viewing area and the non-viewing area, thereby realizing intelligent display.

[0184] Figure 19 is a schematic diagram of the layout of a display substrate provided in some embodiments of the present disclosure. As shown in Figure 19, the AA area is divided into 20*20 display blocks Gro. Taking the resolution of 4000*2000 as an example, each display block Gro includes 200*100 pixel units. In order to achieve partitioned display, each display block Gro needs to be individually controllable, that is, each display block Gro can display normally or individually. Therefore, an independent switch is set for each display block Gro, and a set of switches, namely transistors Z1 and transistors Z2, is added to each row of each display block Gro. In this example, each display block Gro includes 200 rows of pixel units, so each display block Gro requires 200 sets of switches. Transistors Z1 and transistors Z2 are respectively controlled by a set of opposite signals, namely Gate_EN_N and Gate_EN_P. When the signal Gate_EN_N is high, the signal Gate_EN_P is low; when the signal Gate_EN_N is low, the signal Gate_EN_P is high. For example, the signal Gate_EN_P controls the transistor Z1, and Gate_EN_N controls the transistor Z2. For example, in order to match the pixel circuit and reduce the area, the transistors Z1 and Z2 corresponding to each row of each display block Gro use the same NMOS transistors as the pixel circuit.

[0185] In the row direction, since there are 20 display blocks Gro, 20 groups of control signals are required, Gate_EN1_N and Gate_EN1_P are the first group, Gate_EN2_N and Gate_EN2_P are the second group, and so on. In the column direction, each column of display blocks Gro is controlled by the same set of control signals Gate_EN_N and Gate_EN_P.

[0186] During normal display, all Gate_EN<1:20>_P signals are high, and each display block Gro receives the corresponding scan signal Gate<1:2000>. The scan signals for the same row are identical. When partitioned display is required, the control signals Gate_EN<1:20>_N and Gate_EN<1:20>_P are adjusted based on the gaze area determined by eye tracking technology.

[0187] For example, in some examples, assuming the attention zone is in the 5th and 6th pixels of the first row of display blocks Gro, when transmitting the first 100 rows of display data, the signals Gate_EN5_P and Gate_EN6_P are set to high, while the remaining Gate_EN_P signals are set to low. Then, the pixels in the 5th and 6th display blocks Gro are normally written with the corresponding data signals and display, while the Gate_EN_P signals of the other display blocks Gro are set to low. The ground potential is connected to each row of scan lines in these display blocks Gro, resulting in the gates of all pixel units in these display blocks Gro being unable to open and no new data signals being written, thereby causing the OLED to maintain the luminance of the previous frame. In this way, the attention zone can display in high definition, while the non-attention zone maintains the luminance of the previous frame.

[0188] For example, in other examples, for non-attention areas located in the same row as the attention area, the gates of the pixel units are turned on through Gate_EN_N and Gate_EN_P control, but different data signals are written. For other non-attention areas that are not in the same row as the attention area, the gates of multiple rows of pixel units are turned on simultaneously, thereby quickly refreshing and improving the frame rate.

[0189] For example, in some other examples, data signals are provided to the attention zone and the non-attention zone respectively, and the high-definition data of the attention zone is refreshed first, and then the low-definition data of other non-attention zones are refreshed.

[0190] It should be noted that in the embodiments of the present disclosure, the method for performing intelligent display is not limited to the method described above, and any other applicable method may be used, and the embodiments of the present disclosure are not limited thereto. For example, intelligent display can be achieved by combining Gate_EN<1:20>_N and Gate_EN<1:20>_P with data signals according to a front-end algorithm.

[0191] Through the above method, the display block Gro is independently controllable and can cooperate with the algorithm to display the gaze area and the non-gaze area separately. It is compatible with various intelligent display modes, such as multiple rows turned on at the same time, any row turned on, etc., thereby achieving high-definition display effects in the human eye gaze area within a certain bandwidth, and reducing resolution and power consumption in the non-gaze area.

[0192] For example, the circuits provided in the above embodiments, such as the pixel circuit, the source driving circuit, and the sensing circuit, can all be integrated on a single chip, thereby facilitating mass production and reducing costs.

[0193] There are a few points to note:

[0194] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0195] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0196] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: substrate; A plurality of pixel units are provided on the substrate; as well as A plurality of pixel circuits are provided on the base substrate; The plurality of pixel units are arranged in a plurality of rows and columns, the plurality of pixel units are divided into a plurality of groups, each group of pixel units includes at least two pixel units, and each pixel unit includes a light-emitting element; Each pixel circuit is used to drive a corresponding group of pixel units, and each pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, a sensing circuit and a light emitting control circuit; The driving circuit is connected to the data writing circuit, the storage circuit, the sensing circuit and the light emitting control circuit respectively, and is configured to control the magnitude of the driving current; The data writing circuit is configured to write a data signal into the driving circuit in response to a first scanning signal; The storage circuit is configured to store the data signal written by the data writing circuit; The sensing circuit is configured to connect the driving circuit to the sensing signal line in response to a second scanning signal; The light emitting control circuit is connected to the driving circuit and is respectively connected to at least two light emitting elements of at least two pixel units in a corresponding group of pixel units, and the light emitting control circuit is configured to apply the driving current to the light emitting elements of each pixel unit in the group of pixel units at different times in response to at least two light emitting control signals; The light emitting element is configured to emit light according to the received driving current.

2. The display substrate according to claim 1, wherein The number of pixel units included in each group of pixel units is N, where N is a positive integer. The light emitting control circuit includes N light emitting control sub-circuits, and the at least two light emitting control signals include N light emitting control signals. Each light-emitting control subcircuit is connected to the light-emitting element of a pixel unit in a corresponding group of pixel units, and each light-emitting control subcircuit receives one of the N light-emitting control signals. Different light-emitting control subcircuits are connected to the light-emitting elements of different pixel units in a corresponding group of pixel units, and different light-emitting control subcircuits receive different light-emitting control signals.

3. The display substrate according to claim 2, wherein: The driving circuit includes a control terminal, a first terminal, and a second terminal. The first terminal of the driving circuit receives a first voltage from a first voltage terminal. The data writing circuit is connected to the control end of the driving circuit, the first end of the storage circuit is connected to the control end of the driving circuit, the second end of the storage circuit is connected to the first end of the driving circuit, the sensing circuit is connected to the second end of the driving circuit, and the light emitting control circuit is connected to the second end of the driving circuit. The first end of the light emitting element is connected to the light emitting control circuit, and the second end of the light emitting element receives the second voltage from the second voltage end.

4. The display substrate according to claim 3, wherein: The data writing circuit includes a first transistor, the sensing circuit includes a second transistor, the driving circuit includes a third transistor, and the storage circuit includes a storage capacitor; The gate of the third transistor serves as the control terminal of the driving circuit, the first electrode of the third transistor serves as the first terminal of the driving circuit, and the second electrode of the third transistor serves as the second terminal of the driving circuit; The gate of the first transistor is connected to the first scan line to receive the first scan signal, the first electrode of the first transistor is connected to the data line to receive the data signal, and the second electrode of the first transistor is connected to the gate of the third transistor; The gate of the second transistor is connected to the second scan line to receive the second scan signal, the first electrode of the second transistor is connected to the second electrode of the third transistor, and the second electrode of the second transistor is connected to the sensing signal line; The first electrode of the storage capacitor serves as the first end of the storage circuit, and the second electrode of the storage capacitor serves as the second end of the storage circuit.

5. The display substrate according to claim 4, wherein: Each light emission control sub-circuit includes a light emission control transistor, The gate of the light-emitting control transistor is connected to the corresponding light-emitting control signal line to receive the corresponding light-emitting control signal, the first electrode of the light-emitting control transistor is connected to the second electrode of the third transistor, and the second electrode of the light-emitting control transistor is connected to the corresponding light-emitting element. The display substrate according to claim 5 , wherein: The storage capacitor includes two stacked capacitor plates, one of the two capacitor plates serves as a first electrode of the storage capacitor, and the other of the two capacitor plates serves as a second electrode of the storage capacitor; The orthographic projection of at least one of the two capacitor plates on the substrate at least partially covers the orthographic projection of the first transistor on the substrate and at least partially covers the orthographic projection of the second transistor on the substrate.

7. The display substrate according to claim 6, wherein: The orthographic projection of the first transistor on the substrate at least includes the orthographic projection of the active layer of the first transistor on the substrate. The orthographic projection of the second transistor on the substrate includes at least the orthographic projection of the active layer of the second transistor on the substrate.

8. The display substrate according to claim 6 or 7, wherein: The orthographic projection of at least one of the two capacitor plates on the substrate at least partially covers the orthographic projection of the third transistor on the substrate.

9. The display substrate according to any one of claims 6 to 8, wherein: An orthographic projection of the first transistor on the substrate and an orthographic projection of the second transistor on the substrate are located on both sides of an orthographic projection of the third transistor on the substrate.

10. The display substrate according to claim 6, wherein: The orthographic projection of at least one of the two capacitor plates on the base substrate at least partially covers the orthographic projection of the light emitting control transistor on the base substrate.

11. The display substrate according to any one of claims 6 to 10, wherein: The two capacitor plates include a first capacitor plate and a second capacitor plate, wherein the orthographic projection of the second capacitor plate on the base substrate covers the orthographic projection of the first capacitor plate on the base substrate; The first capacitor plate is connected to the first transfer electrode through a first set of via holes, and the orthographic projection of the first transfer electrode on the base substrate and the orthographic projection of the first set of via holes on the base substrate are both located within the orthographic projection of the first capacitor plate on the base substrate; The second capacitor plate is connected to the second transfer electrode through a second group of vias, and the orthographic projection of the second transfer electrode on the base substrate and the orthographic projection of the second group of vias on the base substrate are both located within the orthographic projection of the second capacitor plate on the base substrate, and do not overlap with the orthographic projection of the first capacitor plate on the base substrate.

12. The display substrate according to claim 11, wherein: There is a gap between the orthographic projection of the second switching electrode on the base substrate and the orthographic projection of the first capacitor plate on the base substrate.

13. The display substrate according to claim 6, wherein: The N light control subcircuits include a first light control subcircuit, a second light control subcircuit, a third light control subcircuit and a fourth light control subcircuit, The first light emitting control subcircuit includes a first light emitting control transistor, the second light emitting control subcircuit includes a second light emitting control transistor, the third light emitting control subcircuit includes a third light emitting control transistor, and the fourth light emitting control subcircuit includes a fourth light emitting control transistor. The first light emission control transistor, the second light emission control transistor, the third light emission control transistor, and the fourth light emission control transistor are distributed along a first direction. The first via connected to the gate of the first light emitting control transistor, the second via connected to the gate of the second light emitting control transistor, the third via connected to the gate of the third light emitting control transistor, and the fourth via connected to the gate of the fourth light emitting control transistor are not located on the same straight line extending along the first direction.

14. The display substrate according to claim 13, wherein: The first electrode and the second electrode of the first light-emitting control transistor, the first electrode and the second electrode of the second light-emitting control transistor, the first electrode and the second electrode of the third light-emitting control transistor, and the first electrode and the second electrode of the fourth light-emitting control transistor are all located on the same extension line extending along the first direction, and the first via hole, the second via hole, the third via hole and the fourth via hole are alternately located on both sides of the extension line.

15. The display substrate according to claim 14, wherein: The gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are located on the same distribution line extending along the first direction, The distribution line and the extension line are parallel to each other and have a gap therebetween.

16. The display substrate according to any one of claims 13 to 15, wherein: The data line and the sensing signal line are spaced apart from each other and extend along a second direction on the base substrate, wherein the second direction is perpendicular to the first direction. An orthographic projection of the data line on the base substrate and an orthographic projection of the sensing signal line on the base substrate are located on both sides of an orthographic projection of the third transistor on the base substrate.

17. The display substrate according to claim 16, wherein: The orthographic projection of the data line on the base substrate is located between the orthographic projection of the first transistor on the base substrate and the orthographic projection of the third transistor on the base substrate. An orthographic projection of the sensing signal line on the base substrate is located between an orthographic projection of the second transistor on the base substrate and an orthographic projection of the third transistor on the base substrate.

18. The display substrate according to any one of claims 13 to 15, wherein: The length of the current flow path between the second and third emission control transistors and the corresponding light emitting elements is greater than the length of the current flow path between the first and fourth emission control transistors and the corresponding light emitting elements.

19. The display substrate according to claim 18, wherein: The first light-emitting control transistor is connected to the corresponding light-emitting element through a first adapter wire, the second light-emitting control transistor is connected to the corresponding light-emitting element through a second adapter wire, the third light-emitting control transistor is connected to the corresponding light-emitting element through a third adapter wire, and the fourth light-emitting control transistor is connected to the corresponding light-emitting element through a fourth adapter wire. The first adapter wire and the fourth adapter wire are axially symmetrically distributed, and the second adapter wire and the third adapter wire are axially symmetrically distributed.

20. The display substrate according to claim 19, wherein The first adapter cable, the second adapter cable, the third adapter cable, and the fourth adapter cable are all L-shaped.

21. The display substrate according to claim 20, wherein: The L-shaped trace includes a first section extending along the first direction and a second section extending along a second direction, wherein the second direction is perpendicular to the first direction. The orthographic projection of the first segment on the substrate does not overlap with the orthographic projection of the capacitor plate on the substrate. The orthographic projection of the second segment on the base substrate overlaps with the orthographic projection of the capacitor plate on the base substrate.

22. The display substrate according to claim 21, wherein The first adapter wire is connected to the corresponding light-emitting element through a fifth via hole, and the fifth via hole is located in the first section of the first adapter wire; The second adapter wire is connected to the corresponding light-emitting element through a sixth via hole, and the sixth via hole is located in the first section of the second adapter wire; The third adapter wire is connected to the corresponding light-emitting element through a seventh via hole, and the seventh via hole is located in the first section of the third adapter wire; The fourth adapter wire is connected to the corresponding light-emitting element through an eighth via hole, and the eighth via hole is located in the first section of the fourth adapter wire.

23. The display substrate according to claim 21, wherein The first section of the second adapter wire and the first section of the third adapter wire are equal in length and are both the first length, the first section of the first adapter wire and the first section of the fourth adapter wire are equal in length and are both the second length, and the first length is greater than the second length.

24. The display substrate according to any one of claims 1 to 23, wherein: The pixel units of the same group are located in the same row and arranged adjacent to each other in sequence.

25. The display substrate according to any one of claims 1 to 24, wherein: The display substrate includes a silicon-based organic light emitting diode display substrate.

26. A display device comprising the display substrate according to any one of claims 1 to 25.

27. A driving method for a display substrate according to any one of claims 1 to 25, wherein: The at least two pixel units included in each group of pixel units include the first to Nth pixel units, the at least two light emitting control signals include the first to Nth light emitting control signals, a frame display stage includes the first stage to the Nth stage, N is a positive integer, The method comprises: In the P-th stage of the display stage, sequentially shifted first scanning signals are provided to multiple rows of pixel units on the display substrate, and the P-th light-emitting control signal of each row of pixel units is set to an operating level, and the light-emitting control signals other than the P-th light-emitting control signal of at least two light-emitting control signals of each row of pixel units are set to a non-operating level, so as to realize row-by-row scanning of the P-th pixel unit in each group of pixel units in the P-th stage, wherein 1≤P≤N and P is an integer.

28. The method according to claim 27, wherein In each stage from the first stage to the Nth stage, the first scanning signal corresponding to the pixel units in the same row has a pulse waveform having the working level. In the display phase, the number of the pulse waveforms of the first scanning signal corresponding to the same row of pixel units is N.

29. The method of claim 27, further comprising: In the blanking phase, at least two light emitting control signals of each row of pixel units are set to non-working levels, and the first scanning signal and the second scanning signal of the target row of pixel units are set to working levels. The target row pixel units are pixel units that need to be detected.

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