Integrated circuit package (IC) and methods for manufacturing integrated circuit packages (IC)

VN10060319BActive Publication Date: 2026-08-17QUALCOMM INC
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Patent Information

Application Number
VN1202300295
Authority / Receiving Office
VN · VN
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-06-18
Publication Date
2026-08-17
Estimated Expiration
2041-06-18
Patent Text Reader

Abstract

This section refers to integrated circuit (IC) packages and methods for manufacturing integrated circuit (IC) packages. An integrated circuit (IC) package with stacked die wire connections consists of two stacked IC dies, where the first die is directly connected to the metallized structure and the second die is stacked on top of the first die and connected to the metallized structure via wire connections. The two IC dies are joined together through the inner metal layer of the metallized structure. The pins are used to bond with the underlying metal layer.
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