SHIFT REGISTERS AND SHIFT REGISTER CONTROL METHODS, SCANNING CONTROL CIRCUITS, AND DISPLAY DEVICES

Abstract

The invention relates to a shift register (100), comprising an input circuit (1), an output circuit (2), a first control circuit (3), and a holding circuit (4). The input circuit (1) is electrically connected to the first clock signal input (CK), the input signal input (STV), and the first node (N1). The input circuit (1) is configured to transmit the input signal, which is received at the input signal input (STV), to the first node (N1). The output circuit (2) is electrically connected to the first node (N1), the second clock signal input (CB), and the output signal input (Gout). The output circuit (2) is configured to transmit the second clock signal, which is received at the second clock signal input (CB), to the output signal input (Gout). The first control circuit (3) is electrically connected to the first node (N1), the first voltage signal input (VGH), the second clock signal input (CB), and the second node (N2). The first control circuit (3) is configured to control the voltage of the second node (N2) in accordance with the control of the voltage of the first node (N1) and the second clock pulse signal.The holding circuit (4) is electrically connected to the second node (N2), the first voltage signal (VGH) and the output signal (Gout). The holding circuit (4) is configured to transmit the first voltage signal to the output signal (Gout).

Description

Shift register and driving method thereof, scanning driving circuit, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a scan driving circuit, and a display device. Background Art

[0002] The scan driver circuit is an important component of a display device. The scan driver circuit may include multiple cascaded shift registers, each of which may be electrically connected to multiple lines in the display device. The scan driver circuit may input scan signals to multiple lines (e.g., gate lines or enable signal lines) in the display device row by row, enabling the display device to display images.

[0003] Providing a scan driving circuit in a display device can effectively reduce costs and improve yield.

[0004] Summary of the Invention

[0005] In one aspect, a shift register is provided. The shift register includes an input circuit, an output circuit, a first control circuit, and a holding circuit. The input circuit is electrically connected to a first clock signal terminal, an input signal terminal, and a first node. The input circuit is configured to transmit an input signal received at the input signal terminal to the first node under the control of a first clock signal transmitted by the first clock signal terminal. The output circuit is electrically connected to the first node, a second clock signal terminal, and an output signal terminal. The output circuit is configured to transmit a second clock signal received at the second clock signal terminal to the output signal terminal under the control of the voltage at the first node. The first control circuit is electrically connected to the first node, a first voltage signal terminal, the second clock signal terminal, and a second node. The first control circuit is configured to control the voltage at the second node under the control of the voltage at the first node and the second clock signal. The holding circuit is electrically connected to the second node, the first voltage signal terminal, and the output signal terminal. The holding circuit is configured to transmit the first voltage signal to the output signal terminal under the control of the voltage at the second node.

[0006] In some embodiments, the first control circuit includes a first sub-control circuit and a second sub-control circuit. The first sub-control circuit is electrically connected to the first node, the first voltage signal terminal, the second clock signal terminal, and a third node; the first sub-control circuit is configured to control the voltage of the third node under the control of the voltage of the first node and the second clock signal. The second sub-control circuit is electrically connected to the first node, the third node, the first voltage signal terminal, the second clock signal terminal, and the second node; the second sub-control circuit is configured to control the voltage of the second node under the control of the voltage of the first node and the voltage of the third node.

[0007] In some embodiments, the first sub-control circuit includes: a third transistor and a second capacitor. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first voltage signal terminal, and the second electrode of the third transistor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the second clock signal terminal, and the second terminal of the second capacitor is electrically connected to the third node.

[0008] In some embodiments, the second sub-control circuit includes: a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0009] In some embodiments, the shift register further includes a potential stabilization circuit. The potential stabilization circuit is electrically connected to the first node, the second voltage signal terminal, and the fourth node. The potential stabilization circuit is configured to, under control of the second voltage signal transmitted by the second voltage signal terminal, transmit an input signal from the first node to the fourth node and stabilize the voltage of the fourth node. The output circuit is electrically connected to the fourth node and to the first node via the potential stabilization circuit. The output circuit is configured to, under control of the voltage of the fourth node, transmit the second clock signal received at the second clock signal terminal to the output signal terminal.

[0010] In some embodiments, the potential stabilization circuit includes a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second voltage signal terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to the fourth node.

[0011] In some embodiments, the shift register further includes a second control circuit electrically connected to the second node, the first voltage signal terminal, and the first node, and configured to transmit the first voltage signal to the first node under control of the voltage of the second node.

[0012] In some embodiments, the second control circuit includes an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node.

[0013] In some embodiments, the shift register further includes a third control circuit. The third control circuit is electrically connected to the second clock signal terminal, the fifth node, and the first node; the second control circuit is electrically connected to the fifth node and is electrically connected to the first node through the third control circuit. The second control circuit is configured to transmit the first voltage signal to the fifth node under the control of the voltage of the second node. The third control circuit is configured to transmit the first voltage signal from the fifth node to the first node under the control of the second clock signal.

[0014] In some embodiments, the third control circuit includes a ninth transistor. A control electrode of the ninth transistor is electrically connected to the second clock signal terminal, a first electrode of the ninth transistor is electrically connected to the fifth node, and a second electrode of the ninth transistor is electrically connected to the first node. If the second control circuit includes an eighth transistor, the second electrode of the eighth transistor is electrically connected to the fifth node and is electrically connected to the first node through the ninth transistor.

[0015] In some embodiments, the input circuit includes a first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the input signal terminal, and a second electrode of the first transistor is electrically connected to the first node.

[0016] In some embodiments, the output circuit includes a second transistor and a first capacitor. The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the output signal terminal. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the output signal terminal. If the potential stabilization circuit includes a seventh transistor, the control electrode of the second transistor is electrically connected to the fourth node and electrically connected to the first node through the seventh transistor.

[0017] In some embodiments, the holding circuit includes: a sixth transistor and a third capacitor. The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the output signal terminal. The first terminal of the third capacitor is electrically connected to the second node, and the second terminal of the third capacitor is electrically connected to the first voltage signal terminal.

[0018] In some embodiments, the shift register includes a plurality of transistors having the same conduction type.

[0019] In some embodiments, the first clock signal and the second clock signal are inverted signals of each other.

[0020] In another aspect, a driving method of a shift register as described above is provided, wherein the driving method comprises: a first stage and a second stage. In the first stage, in response to the first clock signal received at the first clock signal terminal, the input circuit is turned on and transmits the input signal received at the input signal terminal to the first node; under the control of the voltage of the first node, the output circuit is turned on and transmits the second clock signal received at the second clock signal terminal to the output signal terminal; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first voltage signal transmitted by the first voltage signal terminal to the second node and controls the voltage of the second node; under the control of the voltage of the second node, the holding circuit is turned off; in the second stage, in response to the first clock signal received at the first clock signal terminal, the input circuit is turned on and transmits the input signal received at the input signal terminal to the first node; under the control of the voltage of the first node, the output circuit is turned off; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node and controls the voltage of the second node; under the control of the voltage of the second node, the holding circuit is turned on and transmits the first voltage signal to the output signal terminal.

[0021] In some embodiments, the first phase includes an input phase and a scan phase. In the input phase, in response to the first clock signal, the input circuit turns on and transmits the input signal to the first node. Under the control of the voltage of the first node, the output circuit turns on and transmits the second clock signal to the output signal terminal. Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first voltage signal to the second node to control the voltage of the second node. Under the control of the voltage of the second node, the hold circuit turns off. In the scan phase, in response to the first clock signal, the input circuit turns off. The voltage of the first node remains substantially unchanged. The output circuit remains on under the control of the voltage of the first node and transmits the second clock signal to the output signal terminal. Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first voltage signal to the second node to control the voltage of the second node. Under the control of the voltage of the second node, the hold circuit turns off. The second phase includes a first hold phase and a second hold phase. In the first hold phase, in response to the first clock signal, the input circuit is turned on and transmits the input signal to the first node; under the control of the voltage of the first node, the output circuit is turned off; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the voltage of the second node; under the control of the voltage of the second node, the hold circuit is turned off. In the second hold phase, in response to the first clock signal, the input circuit is turned off; the voltage of the first node remains substantially unchanged, and the output circuit remains in an off state under the control of the voltage of the first node; under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the voltage of the second node; under the control of the voltage of the second node, the hold circuit is turned on and transmits the first voltage signal to the output signal terminal.

[0022] In yet another aspect, a scan drive circuit is provided. The scan drive circuit comprises: a plurality of cascaded shift registers as described in any of the above embodiments. Except for the last i shift registers, the output signal terminal of the Nth shift register is electrically connected to the input signal terminal of the N+ith shift register; wherein N and i are both positive integers, and i<N.

[0023] In some embodiments, the scan driving circuit further includes: at least one first clock signal line and at least one second clock signal line. When i=1, the first clock signal line is electrically connected to the first clock signal terminal of the 2N-1th shift register and the second clock signal terminal of the 2Nth shift register; and the second clock signal line is electrically connected to the second clock signal terminal of the 2N-1th shift register and the first clock signal terminal of the 2Nth shift register.

[0024] In another aspect, a display device is provided, comprising: a scan driving circuit as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a structural diagram of a shift register according to one implementation manner;

[0027] FIG2 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0028] FIG3 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0029] FIG4 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0030] FIG5 is a structural diagram of a shift register according to some embodiments of the present disclosure;

[0031] FIG6 is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0032] FIG7 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

[0033] FIG8 is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0034] FIG9 is a circuit diagram of another shift register according to some embodiments of the present disclosure;

[0035] FIG10 is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0036] FIG11 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0037] FIG12 is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0038] FIG13 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0039] FIG14 is a timing control diagram corresponding to the shift register shown in FIG13 according to some embodiments of the present disclosure;

[0040] FIG15 is a structural diagram of a scan driving circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0043] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0044] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments disclosed herein.

[0045] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0048] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0050] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0051] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0052] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0053] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; exemplarly, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0054] In the circuits provided in the embodiments of the present disclosure, “nodes” do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram.

[0055] In the following description of the circuits provided in the embodiments of the present disclosure, P-type transistors are used as examples. It should be noted that the transistors in the various circuits mentioned below use the same conduction type, which can simplify the process flow, reduce process difficulty, and improve the yield of products (such as the scan driver circuit 1000 and the display device 2000).

[0056] Some embodiments of the present disclosure provide a shift register 100 and a driving method thereof, a scan driving circuit 1000 , and a display device 2000 . The shift register 100 , the driving method of the shift register 100 , the scan driving circuit 1000 , and the display device 2000 are respectively introduced below.

[0057] Some embodiments of the present disclosure provide a display device 2000, as shown in FIG2 . The display device 2000 can be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or . More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0058] In some examples, the display device 2000 includes a frame, a display panel PNL disposed in the frame, a circuit board, a data driver IC (Integrated Circuit), and other electronic components.

[0059] The above-mentioned display panel PNL can be, for example: an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel or a mini light emitting diode (Mini LED), etc., and the present disclosure does not make any specific limitations on this.

[0060] The following takes the display panel PNL as an OLED display panel as an example to schematically illustrate some embodiments of the present disclosure.

[0061] In some embodiments, as shown in FIG3 , the display panel PNL includes a display area A and a frame area B disposed adjacent to the display area A. The term “adjacent” refers to one side, two sides, three sides, or a peripheral side of the display area A. That is, the frame area B may be located on one side, two sides, or three sides of the display area A, or the frame area B may surround the display area A.

[0062] In some examples, as shown in FIG. 3 , the display panel PNL may include a substrate 200 , and a plurality of sub-pixels P, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of enable signal lines EL disposed on one side of the substrate 200 .

[0063] There are many types of the substrate 200 , which can be selected according to actual needs.

[0064] For example, the substrate 200 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0065] For example, the substrate 200 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate diformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the display panel PNL may be a flexible display panel.

[0066] Optionally, as shown in FIG3 , the plurality of sub-pixels P, the plurality of gate lines GL, the plurality of data lines DL, and the plurality of enable signal lines EL may be located in the display area A, and the plurality of gate lines GL may extend along a first direction X, the plurality of data lines DL may extend along a second direction Y, and the plurality of enable signal lines EL may extend along the first direction X. The plurality of enable signal lines EL may, for example, be provided on the same layer as the plurality of gate lines GL.

[0067] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°, etc.

[0068] For example, the above-mentioned multiple sub-pixels P can be arranged in an array, that is, the multiple sub-pixels P can be arranged in multiple rows along the first direction X, and arranged in multiple rows along the second direction Y. Among them, the sub-pixels P arranged in a row along the first direction X can be called sub-pixels P in the same row, and the sub-pixels P arranged in a row along the second direction Y can be called sub-pixels P in the same column. The sub-pixels P in the same row can be electrically connected to at least one gate line GL and at least one enable signal line EL, and the sub-pixels P in the same column can be electrically connected to a data line DL. Among them, the number of gate lines GL and enable signal lines EL electrically connected to the sub-pixels P in the same row can be set according to the structure of the sub-pixels P. The present disclosure is explained by taking the example of the sub-pixels P in the same row being electrically connected to a gate line GL and an enable signal line EL.

[0069] In some examples, as shown in FIG3 , each of the plurality of sub-pixels P may include a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit. When the display panel PNL is an OLED display panel, the light-emitting device is an OLED.

[0070] The above-mentioned pixel driving circuit has various structures, which can be selected and configured according to actual needs. For example, the pixel driving circuit may include a "4T1C," "6T1C," "7T1C," "6T2C," "7T2C," or "8T2C" structure. "T" represents a transistor, and the number preceding "T" represents the number of transistors. "C" represents a storage capacitor, and the number preceding "C" represents the number of storage capacitors.

[0071] For example, a light-emitting device may include an anode, a light-emitting layer, and a cathode stacked in sequence. Furthermore, the light-emitting device may further include, for example, a hole injection layer and / or a hole transport layer disposed between the anode and the light-emitting layer, and may further include, for example, an electron transport layer and / or an electron injection layer disposed between the light-emitting layer and the cathode. The pixel driving circuit may be electrically connected to the anode of the light-emitting device, for example.

[0072] The following takes the “7T1C” structure of the pixel driving circuit as an example to schematically illustrate the structure of the sub-pixel P and the connection relationship between the sub-pixel P and the gate line GL, the data line DL, and the enable signal line EL.

[0073] Exemplarily, as shown in FIG4 , the pixel driving circuit includes: a first reset transistor M1 , a compensation transistor M2 , a driving transistor M3 , a switching transistor M4 , a first emission control transistor M5 , a second emission control transistor M6 , a second reset transistor M7 and a storage capacitor Cst.

[0074] For example, as shown in FIG4 , a control electrode of the first reset transistor M1 is electrically connected to the reset signal terminal RESET, a first electrode of the first reset transistor M1 is electrically connected to the initial signal terminal INIT, and a second electrode of the first reset transistor M1 is electrically connected to the first pixel node Q1. The first reset transistor M1 is configured to, under the control of a reset signal transmitted by the reset signal terminal RESET, transmit an initial signal received from the initial signal terminal INIT to the first pixel node Q1, thereby resetting the first pixel node Q1.

[0075] For example, as shown in FIG4 , the control electrode of the compensation transistor M2 is electrically connected to the scan signal terminal Gate, the first electrode of the compensation transistor M2 is electrically connected to the second pixel node Q2, and the second electrode of the compensation transistor M2 is electrically connected to the first pixel node Q1. The compensation transistor M2 is configured to, under the control of a scan signal transmitted by the scan signal terminal Gate, transmit a signal (e.g., a data signal) from the second pixel node Q2 to the first pixel node Q1, thereby performing threshold voltage compensation on the driving transistor T3.

[0076] For example, as shown in FIG4 , the control electrode of the driving transistor M3 is electrically connected to the first pixel node Q1, the first electrode of the driving transistor M3 is electrically connected to the third pixel node Q3, and the second electrode of the driving transistor M3 is electrically connected to the second pixel node Q2. The driving transistor M3 is configured to transmit a signal (e.g., a data signal) from the third pixel node Q3 to the second pixel node Q2 under the control of the voltage of the first pixel node Q1.

[0077] For example, as shown in FIG4 , the control electrode of the switching transistor M4 is electrically connected to the scan signal terminal Gate, the first electrode of the switching transistor M4 is electrically connected to the data signal terminal Data, and the second electrode of the switching transistor M4 is electrically connected to the third pixel node Q3. The switching transistor M4 is configured to transmit the data signal transmitted by the data signal terminal Data to the third pixel node Q3 under the control of the scan signal transmitted by the scan signal terminal Gate.

[0078] For example, as shown in FIG4 , a control electrode of the first emission control transistor M5 is electrically connected to the emission control signal terminal EM, a first electrode of the first emission control transistor M5 is electrically connected to the first power signal terminal VDD, and a second electrode of the first emission control transistor M5 is electrically connected to the third pixel node Q3. The first emission control transistor M5 is configured to transmit the first power signal transmitted by the first power signal terminal VDD to the third pixel node Q3 under the control of the emission control signal transmitted by the emission control signal terminal EM.

[0079] For example, as shown in FIG4 , the control electrode of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal terminal EM, the first electrode of the second light-emitting control transistor M6 is electrically connected to the second pixel node Q2, and the second electrode of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting device. The second light-emitting control transistor M6 is configured to transmit a signal (e.g., a first power supply signal) from the second pixel node Q2 to the anode of the light-emitting device under the control of the light-emitting control signal transmitted by the light-emitting control signal terminal EM.

[0080] For example, as shown in FIG4 , the control electrode of the second reset transistor M7 is electrically connected to the scan signal terminal Gate, the first electrode of the second reset transistor M7 is electrically connected to the initial signal terminal INIT, and the second electrode of the second reset transistor M7 is electrically connected to the anode of the light-emitting device. The second reset transistor M7 is configured to, under the control of the scan signal transmitted by the scan signal terminal Gate, transmit the initial signal received from the initial signal terminal INIT to the anode of the light-emitting device to reset the anode of the light-emitting device.

[0081] 4 , the cathode of the light emitting device is electrically connected to the second power signal terminal VSS, wherein the light emitting device is configured to emit light under the control of the first power signal and the second power signal transmitted by the second power signal terminal VSS.

[0082] 4 , a first end of the storage capacitor Cst is electrically connected to the first power signal terminal VDD, and a second end of the storage capacitor Cst is electrically connected to the first pixel node Q1. The storage capacitor Cst is configured to store a signal transmitted to the first pixel node Q1 and maintain the voltage of the first pixel node Q1.

[0083] Illustratively, the pixel driving circuit may be electrically connected to the corresponding gate line GL via the scan signal terminal Gate, electrically connected to the corresponding data line DL via the data signal terminal Data, and electrically connected to the corresponding enable signal line EL via the emission control signal terminal EM.

[0084] During display operation on the display panel PNL, the pixel driving circuit receives a scan signal from the corresponding gate line GL, a data signal from the corresponding data line DL, and an enable signal from the corresponding enable signal line EL to generate a drive current. This drive current is then transmitted to the light-emitting device via the first emission control transistor M5, the drive transistor M3, and the second emission control transistor M6, thereby driving the light-emitting device to emit light. The light-emitting devices of the multiple sub-pixels P work together to enable the display panel PNL to display images.

[0085] Here, each transistor in the pixel driving circuit may include, for example, at least one of a low-temperature polysilicon thin film transistor (LTPS TFT) and an oxide thin film transistor. Low-temperature polysilicon thin film transistors have advantages such as high mobility and fast charging, while oxide thin film transistors have advantages such as low leakage current. In this example, LTPS TFT and oxide thin film transistors can be integrated into the same display panel to form a low-temperature polycrystalline oxide (LTPO) display panel, which can take advantage of the advantages of both to achieve high resolution (Pixel Per Inch, PPI) and low-frequency driving, which is conducive to reducing power consumption and improving display quality.

[0086] In some examples, as shown in FIG3 , the data driver IC may be located in the frame area B and electrically connected to a plurality of data lines DL located in the display area A, and provide data signals to corresponding pixel driver circuits through the plurality of data lines DL.

[0087] In some examples, as shown in FIG3 , the display panel PNL may include the scan driving circuit 1000 . The scan driving circuit 1000 and the plurality of sub-pixels P, the gate lines GL, and the data lines DL may be located on the same side of the substrate 200 .

[0088] The scan driving circuit 1000 may have various structures, which may be selected according to actual needs.

[0089] Exemplarily, the scan driving circuit 1000 may be a gate driving circuit GD. The gate driving circuit GD may be electrically connected to the plurality of gate lines GL to provide scan signals to corresponding pixel driving circuits through the plurality of gate lines GL.

[0090] Exemplarily, the scan driving circuit 1000 may also be a light emitting control circuit ED. The light emitting control circuit ED may be electrically connected to the plurality of enable signal lines EL to provide enable signals to corresponding pixel driving circuits through the plurality of enable signal lines EL.

[0091] The scan driving circuit 1000 may be arranged at various locations, which may be selected according to actual needs.

[0092] For example, as shown in FIG. 3 , the scan driving circuit 1000 may be disposed in the border area B and located on at least one side of the extending direction of the plurality of gate lines GL.

[0093] For example, at least a portion of the scan driving circuit 1000 may be disposed within the display area A. This helps reduce the area occupied by the scan driving circuit 1000 within the border area B, thereby reducing the size of the border area B, thereby enabling the display panel PNL and the display device 2000 to achieve a narrow-border design.

[0094] The following is a schematic description using an example in which the scan driving circuit 1000 is a gate driving circuit GD and the scan driving circuit 1000 is disposed in the border area B.

[0095] In some embodiments, as shown in FIG. 15 , the scan driving circuit 1000 includes a plurality of shift registers 100 , which may be arranged in cascade.

[0096] In some examples, the number of shift registers 100 included in the scan driving circuit 1000 and the number of rows of sub-pixels P may be equal or different.

[0097] For example, the number of the shift registers 100 may be equal to the number of rows of sub-pixels P. Based on this, one shift register 100 may be electrically connected to the pixel driving circuits in the same row of sub-pixels P through one gate line GL.

[0098] For another example, the number of shift registers 100 can be greater than the number of rows of sub-pixels P. Based on this, one shift register 100 can be electrically connected to the pixel driving circuit in the same row of sub-pixels P via a gate line GL, and the output signal terminals Gout of the remaining shift registers 100 not electrically connected to the gate line GL can be in a suspended state. For an explanation of the output signal terminals Gout, please refer to the description below and will not be repeated here.

[0099] For another example, the number of shift registers 100 may be less than the number of rows of sub-pixels P. Based on this, one shift register 100 may be electrically connected to the pixel driving circuits in the corresponding rows of sub-pixels P through multiple gate lines GL.

[0100] The shift register 100 may have various structures, which can be selected and configured according to actual needs. The structure of the shift register 100 is schematically illustrated below, but the structure of the shift register 100 in the present disclosure is not limited to the illustrated structure.

[0101] It should be noted that the shift register 100 includes a plurality of transistors, and the conduction type of the plurality of transistors is the same. For example, the plurality of transistors may all be N-type transistors, or the plurality of transistors may all be P-type transistors. It will be understood by those skilled in the art that when the types of the transistors are different, the corresponding timing diagrams may also be different, so the timing diagrams in this application are not limited thereto.

[0102] Furthermore, the structural types of the aforementioned multiple transistors may be the same or different. For example, the multiple transistors may include low-temperature polysilicon thin film transistors, amorphous silicon thin film transistors, or metal oxide thin film transistors.

[0103] In the following, the shift register 100 provided in the embodiment of the present disclosure is described by taking an example in which all transistors are LTPS TFTs.

[0104] In some embodiments, as shown in FIG. 5 to FIG. 7 , the shift register 100 may include: an input circuit 1 , an output circuit 2 , a first control circuit 3 , and a holding circuit 4 .

[0105] In some examples, as shown in Figures 5 to 7, the input circuit 1 is electrically connected to the first clock signal terminal CK, the input signal terminal STV, and the first node N1. The input circuit 1 is configured to transmit an input signal received at the input signal terminal STV to the first node N1 under the control of the first clock signal transmitted by the first clock signal terminal CK.

[0106] For example, when the level of the first clock signal is low, the input circuit 1 can be turned on under the control of the first clock signal and transmit the input signal received at the input signal terminal STV to the first node N1 to charge the first node N1. When the level of the input signal is low, the voltage of the first node N1 is low; when the level of the input signal is high, the voltage of the first node N1 is high.

[0107] In some examples, as shown in Figures 5 to 7, the output circuit 2 is electrically connected to the first node N1, the second clock signal terminal CB, and the output signal terminal Gout. The output circuit 2 is configured to transmit the second clock signal received at the second clock signal terminal CB to the output signal terminal Gout under the control of the voltage of the first node N1.

[0108] For example, when the voltage of the first node N1 is at a low level, the output circuit 2 may be turned on under the control of the voltage of the first node N1 to receive and transmit the second clock signal to the output signal terminal Gout.

[0109] Here, during the period when the output circuit 2 is turned on, the output signal terminal Gout can output the second clock signal as an output signal, which is a scanning signal received by the pixel driving circuit.

[0110] In some examples, as shown in Figures 5 to 7, the first control circuit 3 is electrically connected to the first node N1, the first voltage signal terminal VGH, the second clock signal terminal CB, and the second node N2. The first control circuit 3 is configured to control the voltage of the second node N2 under the control of the voltage of the first node N1 and the second clock signal.

[0111] Here, the first voltage signal terminal VGH is configured to transmit a DC high-level signal (eg, higher than or equal to the high-level portion of the clock signal); the DC high-level signal is referred to as a first voltage signal.

[0112] For example, when the voltage at the first node N1 is at a low level, the first control circuit 3 can, under the control of the voltage at the first node N1, receive and transmit the first voltage signal terminal VGH to the second node N2, charge the second node N2, and make the voltage at the second node N2 at a high level. When the voltage at the first node N1 is at a high level and the level of the second clock signal is at a low level, the first control circuit 3 can, under the control of the second clock signal, receive and transmit the second clock signal to the second node N2, charge the second node N2, and make the voltage at the second node N2 at a low level.

[0113] Furthermore, when the voltage of the first node N1 is at a high level and the second clock signal is at a high level, the voltage of the second node N2 may remain unchanged. That is, the voltage of the second node N2 may, for example, be maintained at the voltage when the voltage of the first node N1 is at a high level and the second clock signal is at a low level; or, the voltage of the second node N2 may, for example, be maintained at the voltage when the voltage of the first node N1 is at a low level and the second clock signal is at a high level.

[0114] Optionally, as shown in FIG. 6 and FIG. 7 , the first control circuit 3 may include a first sub-control circuit 31 and a second sub-control circuit 32 .

[0115] 6 and 7 , the first sub-control circuit 31 is electrically connected to the first node N1, the first voltage signal terminal VGH, the second clock signal terminal CB, and the third node N3. The first sub-control circuit 31 is configured to control the voltage of the third node N3 under the control of the voltage of the first node N1 and the second clock signal.

[0116] For example, when the voltage of the first node N1 is at a high level, the third node N3 is in a floating state. In this case, the first sub-control circuit 31 can couple the second clock signal to the third node N3, and the voltage of the third node N3 can be the same as the level of the second clock signal. For example, when the level of the second clock signal is low, the voltage of the third node N3 is low; when the level of the second clock signal is high, the voltage of the third node N3 is high.

[0117] When the voltage at the first node N1 is at a low level, the first sub-control circuit 31 can receive and transmit the first voltage signal terminal VGH to the third node N3, charging the third node N3 so that the voltage at the third node N3 is at a high level. It should be noted that in this case, the second clock signal is coupled to the third node N3. However, regardless of whether the second clock signal is at a high level or a low level, the voltage at the third node N3 is determined by the first voltage signal.

[0118] 6 and 7 , the second sub-control circuit 32 is electrically connected to the first node N1, the third node N3, the first voltage signal terminal, the second clock signal terminal CB, and the second node N2. The second sub-control circuit 32 is configured to control the voltage of the second node N2 under the control of the voltage of the first node N1 and the voltage of the third node N3.

[0119] For example, when the voltage of the first node N1 is low and the voltage of the third node N3 is high, the second sub-control circuit 32 can receive and transmit the first voltage signal terminal VGH to the second node N2, charge the second node N2, and make the voltage of the second node N2 high.

[0120] When the voltage of the first node N1 is at a high level and the level of the second clock signal is at a low level, the voltage of the third node N3 is at a low level, and the second sub-control circuit 32 can receive and transmit the second clock signal to the second node N2, charge the second node N2, and make the voltage of the second node N2 at a low level.

[0121] Furthermore, when the voltage of the first node N1 is at a high level and the second clock signal is at a high level, the voltage of the second node N2 may remain unchanged. That is, the voltage of the second node N2 may, for example, be maintained at a low level when the voltage of the first node N1 is at a high level and the second clock signal is at a low level; or, the voltage of the second node N2 may, for example, be maintained at a high level when the voltage of the first node N1 is at a low level and the second clock signal is at a high level.

[0122] In some examples, as shown in Figures 5 to 7 , the holding circuit 4 is electrically connected to the second node N2, the first voltage signal terminal VGH, and the output signal terminal Gout. The holding circuit 4 is configured to transmit the first voltage signal to the output signal terminal Gout under the control of the voltage of the second node N2.

[0123] For example, when the voltage at the second node N2 is at a low level, the holding circuit 4 may be turned on under the control of the voltage at the second node N2 to receive and transmit the first voltage signal to the output signal terminal Gout.

[0124] Here, during the period when the circuit 4 is kept turned on, the output signal terminal Gout can output the first voltage signal as the output signal.

[0125] As can be seen from the above, when the voltage at the first node N1 is low, the voltage at the second node N2 is high; and when the voltage at the second node N2 is low, the voltage at the first node N1 is high. That is, while the output circuit 2 is conducting and transmitting the second clock signal to the output signal terminal Gout, the holding circuit 4 remains in an off state, preventing the first voltage signal from being transmitted to the output signal terminal Gout, thereby preventing the accuracy of the output signal from being affected. While the holding circuit 4 is conducting and transmitting the first voltage signal to the output signal terminal Gout, the output circuit 2 remains in an off state, preventing the second clock signal from being transmitted to the output signal terminal Gout, thereby preventing the accuracy of the output signal from being affected.

[0126] 14 as an example, in combination with the structures shown in FIG5 to FIG7 , a driving method of the input circuit 1, the output circuit 2, the first control circuit 3 and the holding circuit 4 included in the shift register 100 is schematically described.

[0127] As shown in FIG14 , the operation process of the shift register 100 includes a first stage S1 and a second stage S2 .

[0128] In the first stage S1 , first, the level of the first clock signal is low, and the level of the input signal is low.

[0129] In response to the first clock signal received at the first clock signal terminal CK, the input circuit 1 is turned on and transmits the input signal received at the input signal terminal STV to the first node N1 , so that the voltage of the first node N1 is at a low level.

[0130] Under the control of the voltage at the first node N1, the output circuit 2 is turned on, transmitting the second clock signal received at the second clock signal terminal CB to the output signal terminal Gout. Here, the output circuit 2 has a voltage storage function, that is, the output circuit 2 stores low-level input signals. Even if the input circuit 1 is turned off in the first phase S1, this function of the output circuit 2 can keep the voltage at the first node N1 at a low level in the first phase S1, thereby keeping the output circuit 2 in the conductive state in the first phase S1.

[0131] Under the control of the voltage of the first node N1 and the second clock signal, the first control circuit 3 transmits the first voltage signal transmitted by the first voltage signal terminal VGH to the second node N2 to control the voltage of the second node N2.

[0132] Under the control of the voltage at the second node N2, the holding circuit 4 is turned off. Since the voltage at the first node N1 remains at a low level in the first phase S1, the first control circuit 3 can continue to transmit the first voltage signal to the second node N2 without being affected by the second clock signal, so that the voltage at the second node N2 remains at a high level, thereby keeping the holding circuit 4 in the off state.

[0133] During this phase, the waveform of the output signal outputted by the output signal terminal Gout is the same as the waveform of the second clock signal. Since the second clock signal first remains at a high level and then transitions to a low level, the output signal first remains at a high level and then transitions to a low level. The waveform of the output signal can be shown in FIG14 .

[0134] In the second stage S2 , first, the level of the first clock signal is low, and the level of the input signal is high.

[0135] In response to the first clock signal received at the first clock signal terminal CK, the input circuit 1 is turned on and transmits the input signal received at the input signal terminal STV to the first node N1 , so that the voltage of the first node N1 is at a high level.

[0136] Under the control of the voltage at the first node N1, the output circuit 2 is turned off. Because the output circuit 2 has a voltage storage function, that is, the output circuit 2 stores high-level input signals, even if the input circuit 1 is turned off in the second phase S1, this function of the output circuit 2 can keep the voltage at the first node N1 at a high level, thereby keeping the output circuit 2 in the off state in the second phase S1.

[0137] Under the control of the voltage of the first node N1 and the second clock signal, the first control circuit 3 transmits the second clock signal to the second node N2 to control the voltage of the second node N2.

[0138] Under the control of the voltage at the second node N2, the holding circuit 4 is turned on and transmits the first voltage signal to the output signal terminal Gout. Since the voltage at the first node N1 remains at a high level during the second phase S2, the voltage at the second node N2 changes under the influence of the second clock signal. For example, if the level of the second clock signal drops to a low level, the voltage at the second node N2 may also drop to a low level under the influence of the second clock signal.

[0139] In this stage, the waveform of the output signal outputted by the output signal terminal Gout is the same as the waveform of the first voltage signal. That is, the level of the output signal remains at a high level, and the waveform of the output signal may be as shown in FIG14 .

[0140] It should be noted that the low-level portion of the output signal can be referred to as an operating level, which is used to turn on some transistors in the corresponding pixel driving circuit; the high-level portion of the output signal can be referred to as a non-operating level, which is used to turn off some transistors in the corresponding pixel driving circuit. By electrically connecting the shift register 100 to the pixel driving circuit in the corresponding sub-pixel P, the shift register 100 can be used to provide the required operating timing to the pixel driving circuit in the corresponding sub-pixel P, thereby driving the corresponding sub-pixel P to display.

[0141] Thus, the shift register 100 provided in some embodiments of the present disclosure, by providing an input circuit 1, an output circuit 2, a first control circuit 3, and a holding circuit 4, and electrically connecting the input circuit 1, the output circuit 2, the first control circuit 3, and the holding circuit 4 to corresponding signal terminals, can utilize the mutual coordination between the signal terminals to enable the output circuit 2 and the holding circuit 4 to be turned on at different time periods, and the second clock signal output by the output circuit 2 and the first voltage signal output by the holding circuit 4 to jointly constitute an output signal. This output signal can be used to drive the corresponding sub-pixel P for display.

[0142] The shift register 100 provided in some embodiments of the present disclosure has a relatively simple structure, which helps improve the manufacturing yield of the shift register 100 and reduces the area occupied by the shift register 100 in the display panel PNL. When the shift register 100 is arranged within the border area B, the size of the border area B is reduced, thereby facilitating a narrow border design.

[0143] In some embodiments, the first clock signal and the second clock signal are inverted signals.

[0144] For example, the "inverted signal" here means that within a certain time period, the level of the first clock signal and the level of the second voltage signal remain unchanged, and when the level of the first clock signal is high, the level of the second clock signal is low, and when the level of the first clock signal is low, the level of the second clock signal is high.

[0145] The above-mentioned inverted signal can be set in a variety of ways, and the specific setting can be selected according to actual needs, and the present disclosure does not limit this.

[0146] For example, within a certain time period, while the level of the first clock signal changes from a high level to a low level, the level of the second clock signal changes from a low level to a high level. While the level of the first clock signal changes from a low level to a high level, the level of the second clock signal changes from a high level to a low level.

[0147] Exemplarily, as shown in FIG14 , the level of the first clock signal and the level of the second clock signal do not change at the same time.

[0148] For example, before the level of the first clock signal changes from a high level to a low level, the second clock signal has already changed from a low level to a high level.

[0149] It should be noted that during the driving process of the shift register 100, considering many uncontrollable factors (such as aging of transistors or different loads, etc.), the waveform of the first clock signal and the waveform of the second clock signal can be set to the waveform shown in Figure 14.

[0150] The present disclosure is schematically described by taking the waveforms of the first clock signal and the second clock signal as shown in FIG14 as an example.

[0151] By setting the first clock signal and the second clock signal as inverted signals, it is not only convenient to control the clock signal, but also helps to reduce the number of settings of the first clock signal terminal CK and the second clock signal terminal CB, simplify the structure of the shift register 100, and simplify the structure of the scan drive circuit 1000 used by the shift register 100, which is conducive to achieving a narrow border design.

[0152] 7 , the structures of the input circuit 1 , the output circuit 2 , the first control circuit 3 and the holding circuit 4 are schematically described below.

[0153] In some examples, as shown in FIG7 , the input circuit 1 includes: a first transistor T1 .

[0154] Exemplarily, as shown in FIG7 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the input signal terminal STV, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0155] For example, when the level of the first clock signal is low, the first transistor T1 can be turned on under the control of the first clock signal, receive and transmit the input signal to the first node N1, and charge the first node N1. When the level of the input signal is low, the voltage of the first node N1 is low; when the level of the input signal is high, the voltage of the first node N1 is high.

[0156] In some examples, as shown in FIG7 , the output circuit 2 includes: a second transistor T2 and a first capacitor C1 .

[0157] Exemplarily, as shown in FIG7 , the control electrode of the second transistor T2 is electrically connected to the first node N1 , the first electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB, and the second electrode of the second transistor T2 is electrically connected to the output signal terminal Gout.

[0158] For example, when the voltage of the first node N1 is at a low level, the second transistor T2 may be turned on under the control of the voltage of the first node N1 to receive and transmit the second clock signal to the output signal terminal Gout.

[0159] Exemplarily, as shown in FIG7 , a first end of the first capacitor C1 is electrically connected to the first node N1 , and a second end of the first capacitor C1 is electrically connected to the output signal terminal Gout.

[0160] For example, when the first transistor T1 is turned on and transmits the input signal to the first node N1, the first capacitor C1 may be charged. When the first transistor T1 is turned off, the first capacitor C1 may be discharged to maintain the voltage of the first node N1.

[0161] Optionally, after the first transistor T1 is turned off, the first capacitor C1 may be discharged so that the voltage of the first node N1 is maintained at a low level, thereby keeping the second transistor T2 turned on to continuously receive and transmit the second clock signal to the output signal terminal Gout.

[0162] In some examples, as shown in FIG7 , the first sub-control circuit 31 includes: a third transistor T3 and a second capacitor C2 .

[0163] For example, as shown in FIG7 , a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the first voltage signal terminal VGH, and a second electrode of the third transistor T3 is electrically connected to the third node N3. A first end of the second capacitor C2 is electrically connected to the second clock signal terminal CB, and a second end of the second capacitor C2 is electrically connected to the third node N3.

[0164] For example, when the voltage of the first node N1 is high, the third transistor T3 can be turned off under the control of the voltage of the first node N1. At this time, the third node N3 is in a floating state. The second capacitor C2 can couple the second clock signal to the third node N3. When the level of the second clock signal is high, the voltage of the third node N3 is high. When the level of the second clock signal is low, the voltage of the third node N3 is low.

[0165] When the voltage at the first node N1 is low, the third transistor T3 can be turned on under the control of the voltage at the first node N1, receiving and transmitting the first voltage signal to the third node N3, charging the third node N3, and increasing the voltage at the third node N3. In this case, the second clock signal is still coupled to the third node N3 through the second capacitor C2. However, regardless of whether the second clock signal is high or low, the voltage at the third node N3 is controlled by the first voltage signal.

[0166] In some examples, as shown in FIG. 7 , the second sub-control circuit 32 includes a fourth transistor T4 and a fifth transistor T5 .

[0167] Exemplarily, as shown in FIG7 , the control electrode of the fourth transistor T4 is electrically connected to the first node N1 , the first electrode of the fourth transistor T4 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2 .

[0168] For example, when the voltage of the first node N1 is at a low level, the fourth transistor T4 can be turned on under the control of the voltage of the first node N1, receive and transmit the first voltage signal to the second node N2, charge the second node N2, and increase the voltage of the second node N2.

[0169] Exemplarily, as shown in FIG7 , the control electrode of the fifth transistor T5 is electrically connected to the third node N3 , the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2 .

[0170] For example, when the voltage of the third node N3 is at a low level, the fifth transistor T5 may be turned on under the control of the voltage of the third node N3 , receive and transmit the second clock signal to the second node N2 , and charge the second node N2 .

[0171] That is to say, when the voltage of the first node N1 is at a low level, the third transistor T3 and the fourth transistor T4 can be turned on under the control of the voltage of the first node N1, the third transistor T3 can receive and transmit the first voltage signal to the third node N3, so that the fifth transistor T5 is turned off, and the fourth transistor T4 can receive and transmit the first voltage signal to the second node N2, so that the voltage of the second node N2 is a high level.

[0172] When the voltage of the first node N1 is high, the third transistor T3 and the fourth transistor T4 can be turned off under the control of the voltage of the first node N1. When the level of the second clock signal is low, the second capacitor C2 can couple the second clock signal to the third node N3, turning on the fifth transistor T5. The fifth transistor T5 can receive and transmit the second clock signal to the second node N2, causing the voltage of the second node N2 to be low.

[0173] In some examples, as shown in FIG7 , the holding circuit 4 includes: a sixth transistor T6 and a third capacitor C3 .

[0174] Exemplarily, as shown in FIG7 , the control electrode of the sixth transistor T6 is electrically connected to the second node N2 , the first electrode of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the output signal terminal Gout.

[0175] For example, when the voltage of the second node N2 is at a low level, the sixth transistor T6 may be turned on under the control of the voltage of the second node N2 to receive and transmit the first voltage signal to the output signal terminal Gout.

[0176] Exemplarily, as shown in FIG7 , a first end of the third capacitor C3 is electrically connected to the second node N2 , and a second end of the third capacitor C3 is electrically connected to the first voltage signal terminal VGH.

[0177] For example, when the fifth transistor T5 is turned on and transmits the second clock signal to the second node N2, the third capacitor C3 can be charged. When the fifth transistor T5 is turned off, the third capacitor C3 can be discharged to maintain the voltage of the second node N2.

[0178] Optionally, after the fifth transistor T5 is turned off, the third capacitor C3 can be discharged so that the voltage of the second node N2 is maintained at a low level, thereby keeping the sixth transistor T6 turned on to continuously receive and transmit the first voltage signal to the output signal terminal Gout.

[0179] In the related art, as shown in Figure 1, a shift register includes two D flip-flops. The first D flip-flop includes a first transmission gate TG1, a first NAND gate Nand1, a first inverter INV1, and a second transmission gate TG2. The second D flip-flop includes a third transmission gate TG3, a second NAND gate Nand2, a second inverter INV2, and a fourth transmission gate TG4. Its driving method is as follows: when the level of the clock signal clk is low and the level of the inverted clock signal clkb is high, the first D flip-flop is turned on, and the signal output by the previous shift register is transmitted to the first D flip-flop. Since the third transmission gate TG3 of the second D flip-flop is in the off state, the signal cannot enter the second D flip-flop; when the level of the clock signal clk is high and the level of the inverted clock signal clkb is low, the first D flip-flop is turned off and latches the signal. At this time, the second D flip-flop is turned on and outputs the signal. This achieves the shift from the previous shift register to the next shift register.

[0180] Since each D flip-flop in the shift register in the related art requires two transmission gates, an inverter and a NAND gate, and each shift register requires two D flip-flops, this will make the circuit structure more complicated and occupy a larger layout space, making it difficult to achieve a narrow-frame design.

[0181] The shift register 100 provided in some embodiments of the present disclosure includes six transistors and three capacitors, and has a simple structure. This helps improve the manufacturing yield of the shift register 100 and reduces the area occupied by the shift register 100 in the display panel PNL. When the shift register 100 is disposed within the border area B, the size of the border area B is reduced, thereby facilitating a narrow-border design.

[0182] It should be noted that the “electrical connection” mentioned in the present disclosure may refer to a direct electrical connection or an indirect electrical connection, and the specific method may be determined according to actual needs.

[0183] In some embodiments, as shown in FIG. 8 and FIG. 9 , the shift register 100 may further include a potential stabilization circuit 5 .

[0184] In some examples, as shown in Figures 8 and 9, the potential stabilization circuit 5 is electrically connected to the first node N1, the second voltage signal terminal VGL, and the fourth node N4. The potential stabilization circuit 5 is configured to, under the control of the second voltage signal transmitted by the second voltage signal terminal VGL, transmit the input signal from the first node N1 to the fourth node N4 and stabilize the voltage of the fourth node N4.

[0185] Based on this, the output circuit 2 is electrically connected to the fourth node N4 and to the first node N1 via the potential stabilization circuit 5. That is, the electrical connection between the output circuit 2 and the input circuit 1 is indirect, and the electrical connection between the two is achieved via the potential stabilization circuit 5. The output circuit 2 is configured to transmit the second clock signal received at the second clock signal terminal CB to the output signal terminal Gout under the control of the voltage of the fourth node N4.

[0186] Here, the second voltage signal terminal VGL is configured to transmit a DC low-level signal (e.g., lower than or equal to the low-level portion of the clock signal); this DC low-level signal is referred to herein as the second voltage signal. The terms "high level" and "low level" mentioned herein are relative, and the voltage values ​​of "high level" and "low level" are not limited.

[0187] For example, the level of the second voltage signal is low, and the potential stabilization circuit 5 remains on. When the input circuit 1 is on and transmits the input signal to the first node N1, the potential stabilization circuit 5 can transmit the input signal to the fourth node N4. When the level of the input signal transmitted to the fourth node N4 is low, the output circuit 2 can be turned on under the control of the voltage of the fourth node N4, receive and transmit the second clock signal to the output signal terminal Gout.

[0188] When the input circuit 1 is turned off, no signal is output from the input circuit 1. At this time, the first node N1 is in a floating state.

[0189] It should be noted that when the output circuit 2 is on and the second clock signal is at a low level, the voltage at the fourth node N4 is likely to further decrease due to the bootstrap effect of the first capacitor C1. Under the influence of the voltage at the fourth node N4, the potential stabilization circuit 5 can be turned off, preventing leakage of the fourth node N4 through the input circuit 1. This can stabilize the voltage at the fourth node N4, ensure the stable conduction state of the output circuit 2, and thus ensure the accuracy of the output signal.

[0190] Furthermore, after the potential stabilization circuit 5 is turned off, the voltage of the first node N1 is prevented from being significantly reduced due to changes in the voltage of the fourth node N4. This prevents the voltage of the first node N1 from significantly reducing and adversely affecting the operating performance of the input circuit 1 (i.e., the first transistor T1) and the third control circuit 7 (i.e., the ninth transistor T9). For details about the third control circuit 7 (i.e., the ninth transistor T9), please refer to the following description and will not be repeated here.

[0191] The structure of the potential stabilization circuit 5 will be schematically described below with reference to FIG. 9 .

[0192] In some examples, as shown in FIG9 , the potential stabilization circuit 5 includes: a seventh transistor T7 .

[0193] Exemplarily, as shown in FIG9 , the control electrode of the seventh transistor T7 is electrically connected to the second voltage signal terminal VGL, the first electrode of the seventh transistor T7 is electrically connected to the first node N1 , and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4 .

[0194] Here, since the control electrode of the seventh transistor T7 is electrically connected to the second voltage signal terminal VGL and the second voltage signal is a DC low-level signal, the seventh transistor T7 is in a normally-on state and transmits the input signal from the first node N1 to the fourth node N4.

[0195] For example, as shown in FIG9 , when the output circuit 2 includes a second transistor T2, the control electrode of the second transistor T2 is electrically connected to the fourth node N4 and electrically connected to the first node N1 through the seventh transistor T7. That is, the electrical connection between the control electrode of the second transistor T2 and the first node N1 is indirect.

[0196] By providing the seventh transistor T7, leakage of the fourth node N4 through the first transistor T1 can be prevented, thereby making the voltage of the fourth node N4 more stable, and allowing the second transistor T2 to maintain a more stable on-state. Furthermore, the voltage of the first node N1 can be made more controllable and stable, preventing the operating performance of the first transistor T1 and the ninth transistor T9 from being affected by large changes in the voltage of the first node N1.

[0197] In some embodiments, as shown in FIG. 10 and FIG. 11 , the shift register 100 may further include: a second control circuit 6 .

[0198] In some examples, as shown in Figures 10 and 11 , the second control circuit 6 is electrically connected to the second node N2, the first voltage signal terminal VGH, and the first node N1. The second control circuit 6 is configured to transmit the first voltage signal to the first node N1 under control of the voltage of the second node N2.

[0199] For example, when the voltage of the second node N2 is at a low level, the second control circuit 6 can be turned on under the control of the voltage of the second node N2, receive and transmit the first voltage signal to the first node N1, charge the first node N1, and make the voltage of the first node N1 at a high level.

[0200] By providing the second control circuit 6, when the voltage at the second node N2 is at a low level, the voltage at the first node N1 can be set to a high level, thereby placing the third node N3 in a floating state, and causing the voltage at the third node N3 to be controlled by the low-level second clock signal. This prevents the first sub-control circuit 31 from mistakenly transmitting the high-level first voltage signal to the third node N3, and prevents the second sub-control circuit 32 from mistakenly transmitting the high-level first voltage signal to the second node N2. This helps ensure that the voltage at the second node N2 remains at a low level, thereby ensuring that the holding circuit 4 is in a relatively stable conductive state, ensuring that the holding circuit 4 can maintain stable transmission of the high-level first voltage signal, and ensuring that the output signal terminal Gout stably outputs the high-level output signal.

[0201] The structure of the second control circuit 6 is schematically described below with reference to FIG. 11 .

[0202] In some examples, as shown in FIG11 , the second control circuit 6 includes: an eighth transistor T8 .

[0203] Exemplarily, as shown in FIG11 , the control electrode of the eighth transistor T8 is electrically connected to the second node N2 , the first electrode of the eighth transistor T8 is electrically connected to the first voltage signal terminal VGH, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1 .

[0204] For example, when the voltage of the second node N2 is at a low level, the eighth transistor T8 can be turned on under the control of the voltage of the second node N2, receive and transmit the first voltage signal to the first node N1, charge the first node N1, and make the voltage of the first node N1 high.

[0205] By providing the eighth transistor T8, when the voltage at the second node N2 is at a low level, the voltage at the first node N1 can be at a high level, thereby keeping the third transistor T3 and the fourth transistor T4 in an off state. This can avoid the situation where the third transistor T3 is mis-turned on, causing the fifth transistor T5 to be turned off, making it difficult to transmit the low-level second clock signal to the second node N2, and avoid the situation where the fourth transistor T4 is mis-turned on, causing the high-level first voltage signal to be transmitted to the second node N2. This helps ensure that the voltage at the second node N2 remains at a low level, and further helps ensure that the sixth transistor T6 is in a relatively stably turned-on state, ensuring that the sixth transistor T6 can maintain stable transmission of the high-level first voltage signal, and ensuring that the output signal terminal Gout stably outputs the high-level output signal.

[0206] In some embodiments, as shown in FIG. 12 and FIG. 13 , the shift register 100 may further include: a third control circuit 7 .

[0207] In some examples, as shown in Figures 12 and 13, the third control circuit 7 is electrically connected to the second clock signal terminal CB, the fifth node N5, and the first node N1. The second control circuit 6 is electrically connected to the fifth node N5 and is electrically connected to the first node N1 through the third control circuit 7. That is, the electrical connection between the second control circuit 6 and the first node N1 is indirect, and the electrical connection between the second control circuit 6 and the first node N1 is achieved through the third control circuit 7.

[0208] Based on this, the second control circuit 6 is configured to transmit the first voltage signal to the fifth node N5 under the control of the voltage of the second node N2. The third control circuit 7 is configured to transmit the first voltage signal from the fifth node N5 to the first node N1 under the control of the second clock signal.

[0209] For example, when the voltage at the second node N2 is at a low level, the second control circuit 6 may be turned on under the control of the voltage at the second node N2, and receive and transmit the first voltage signal to the fifth node N5. When the level of the second clock signal is at a low level, the third control circuit 7 may be turned on under the control of the second clock signal, and transmit the first voltage signal from the fifth node N5 to the first node N1, thereby charging the first node N1 and making the voltage at the first node N1 high.

[0210] That is to say, when the voltage of the second node N2 is at a low level and the level of the second clock signal is at a low level, the first voltage signal can be transmitted to the first node N1 through the second control circuit 6 and the third control circuit 7 in sequence to control the voltage of the first node N1 and avoid affecting the voltage of the second node N2.

[0211] Furthermore, at the beginning of the first stage S1, the voltage of the second node N2 jumps from a low level to a high level, while the levels of the first clock signal and the input signal both jump to a low level. The input circuit 1 transmits the input signal to the first node N1, causing the voltage of the first node N1 to jump from a high level to a low level. During this process, the voltage of the first node N1 may be unstable.

[0212] By setting the third control circuit 7 between the second control circuit 6 and the first node N1, it is possible to ensure that the third control circuit 7 is in the off state at the beginning of the first stage S1, and thus, in the process of the input circuit 1 transmitting the input signal to the first node N1, the voltage of the first node N1 can be prevented from being affected by the first voltage signal, ensuring that the voltage of the first node N1 is controlled by the input signal, which is conducive to improving the overall reliability of the shift register 100.

[0213] The structure of the third control circuit 7 is schematically described below with reference to FIG. 13 .

[0214] In some examples, as shown in FIG13 , the third control circuit 7 includes: a ninth transistor T9 .

[0215] For example, as shown in FIG13 , the control electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal CB, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected to the first node N1. Specifically, when the second control circuit 6 includes an eighth transistor T8, the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5 and is electrically connected to the first node N1 through the ninth transistor T9. That is, the electrical connection between the second electrode of the eighth transistor T8 and the first node N1 is indirect.

[0216] For example, when the voltage of the second node N2 is at a low level, the eighth transistor T8 can be turned on under the control of the voltage of the second node N2, receiving and transmitting the first voltage signal to the fifth node N5. When the level of the second clock signal is at a low level, the ninth transistor T9 can be turned on under the control of the second clock signal, transmitting the first voltage signal from the fifth node N5 to the first node N1, charging the first node N1, and making the voltage of the first node N1 at a high level. When the level of the first clock signal is at a low level and the level of the second clock signal is at a high level, the ninth transistor T9 can be turned off under the control of the second clock signal, preventing the first voltage signal from the fifth node N5 from being transmitted to the first node N1.

[0217] It should be noted that before the start of the first phase S1, the voltage at the second node N2 is at a low level. The first voltage signal can be transmitted to the first node N1 via the eighth transistor T8, causing the voltage at the first node N1 to be high. At the beginning of the first phase S1, the first transistor T1 is turned on under the control of the low-level first clock signal, transmitting the low-level input signal to the first node N1. At this time, the voltage at the first node N1 is difficult to determine, and the conduction states of the third transistor T3 and the fourth transistor T4 are also difficult to determine.

[0218] By providing the ninth transistor T9 between the eighth transistor T8 and the first node N1, the ninth transistor T9 can be turned off when the first transistor T1 is turned on, thereby preventing the first voltage signal from being transmitted to the first node N1. This ensures that the voltage of the first node N1 is also controlled by the low-level input signal at the beginning of the first stage S1, ensuring that the third transistor T3 and the fourth transistor T4 are turned on. This helps improve the overall reliability of the shift register 100.

[0219] The shift register 100 provided in some embodiments of the present disclosure includes only nine transistors and three capacitors, which can realize the output of the output signal. In the first stage S1, after the output signal terminal Gout outputs a low-level second clock signal, the first control circuit 3, the second control circuit 6 and the third control circuit 7 can be used to reset the first node N1 and the fourth node N4. In the second stage S2, the capacitor can be coupled to the transistor control electrode to control the potential of the second node N2, so that the holding circuit 4 can output the high-level first voltage signal more stably, which is beneficial to improving the accuracy of the output signal.

[0220] The shift register 100 has a simple structure, which is beneficial to improving the manufacturing yield of the shift register 100 and reducing the area occupied by the shift register 100 in the display panel PNL. When the shift register 100 is arranged in the border area B, the size of the border area B is reduced, thereby facilitating a narrow border design.

[0221] In the scan driving circuit 1000 provided in some embodiments of the present disclosure, the cascade relationship of the plurality of shift registers 100 may include various types, which may be selected and set according to actual needs.

[0222] In some embodiments, among the plurality of shift registers 100, except for the last i shift registers 100, the output signal terminal Gout of the Nth shift register 100 is electrically connected to the input signal terminal STV of the N+ith shift register 100. Wherein, N and i are both positive integers, and i<N.

[0223] That is, the output signal output by the Nth shift register 100 can be used as the input signal of the (N+i)th shift register 100 .

[0224] In some examples, as shown in FIG15 , i=1. In this case, except for the last shift register 100, the output signal terminal Gout of each shift register 100 can be electrically connected to the input signal terminal STV of the next shift register 100. That is, except for the last shift register 100, the output signal of each shift register 100 can serve as the input signal of the next shift register 100.

[0225] In some examples, i=2. In this case, except for the last two shift registers 100, the output signal terminal Gout of the Nth shift register 100 is electrically connected to the input signal terminal STV of the N+2th shift register 100. That is, the plurality of shift registers 100 can be divided into two groups of shift registers. One group of shift registers includes an odd number of shift registers, and the output signal terminal Gout of each odd number of shift registers can be electrically connected to the input signal terminal STV of the next odd number of shift registers 100; the other group of shift registers includes an even number of shift registers, and the output signal terminal Gout of each even number of shift registers can be electrically connected to the input signal terminal STV of the next even number of shift registers 100.

[0226] In some embodiments, as shown in FIG. 15 , the scan driving circuit 1000 may further include: at least one first clock signal line 201 and at least one second clock signal line 202 .

[0227] In some examples, the scan driving circuit 1000 may include: a first clock signal line 201 and a second clock signal line 202 .

[0228] In other examples, the scan driving circuit 1000 may include: a plurality of first clock signal lines 201 and a plurality of second clock signal lines 202 .

[0229] Here, the number of the first clock signal lines 201 and the number of the second clock signal lines 202 included in the scan driving circuit 1000 may be determined according to the cascade relationship of the plurality of shift registers 100 .

[0230] In some examples, as shown in FIG. 15 , when i=1, the scan driving circuit 1000 may include a first clock signal line 201 and a second clock signal line 202 .

[0231] 15 , the first clock signal line 201 can be electrically connected to the first clock signal terminal CK of the 2N-1th shift register 100 and the second clock signal terminal CB of the 2Nth shift register 100. The second clock signal line 202 can be electrically connected to the second clock signal terminal CB of the 2N-1th shift register 100 and the first clock signal terminal CK of the 2Nth shift register 100.

[0232] The 2N-1th shift register 100 may use the clock signal transmitted by the first clock signal line 201 as the first clock signal, and the clock signal transmitted by the second clock signal line 202 as the second clock signal. The 2Nth shift register 100 may use the clock signal transmitted by the second clock signal line 202 as the first clock signal, and the clock signal transmitted by the first clock signal line 201 as the second clock signal.

[0233] In some examples, as shown in FIG. 15 , the scan driving circuit 1000 may further include: a start signal line 203 .

[0234] In the case of i=1, the input signal terminal of the first shift register 100 in the scan driving circuit 1000 may be electrically connected to the start signal line 203 to use the start signal transmitted by the start signal line 203 as the input signal.

[0235] In some examples, as shown in FIG. 15 , the scan driving circuit 1000 may further include: a first voltage signal line 204 and a second voltage signal line 205 .

[0236] The first voltage signal terminal VGH of each shift register 100 can be electrically connected to the first voltage signal line 204 to receive the first voltage signal, and the second voltage signal terminal VGL of each shift register 100 can be electrically connected to the second voltage signal line 205 to receive the second voltage signal.

[0237] The driving method of the shift register 100 shown in FIG13 is schematically described below with reference to FIG14 and FIG15 .

[0238] A1, A2, A3, A4...AN-1, AN shown in Figure 15 respectively represent the 1st shift register 100, the 2nd shift register 100, the 3rd shift register 100, the 4th shift register 100...N-1th shift register 100, and the Nth shift register 100.

[0239] FIG14 shows a timing diagram of the operation of the shift register 100 shown in FIG13. In FIG14, N1 <1> 、N2 <1> 、N3 <1> and N4 <1> Gout represents the first node N1, the second node N2, the third node N3 and the fourth node N4 of the first shift register 100 respectively. <1> represents the output signal terminal Gout of the first shift register 100.

[0240] Exemplarily, a driving method for the first shift register 100 (i.e., corresponding to the first row of sub-pixels P of the display panel PNL) is described as follows. The driving method includes a first phase S1 and a second phase S2. The first phase S2 includes an input phase S11 and a scan phase S12, and the second phase S2 includes a first hold phase S21 and a second hold phase S22.

[0241] In the input phase S11 , the level of the input signal is low, the level of the first clock signal is low, and the level of the second clock signal is high.

[0242] In response to the first clock signal, the first transistor T1 in the input circuit 1 is turned on, transmitting the input signal to the first node N1. <1> , for the first node N1 <1> Charge the first node N1 <1> The voltage is low.

[0243] At the first node N1 <1> Under the control of the voltage of the first control circuit 3 and the second clock signal, the first control circuit 3 transmits the first voltage signal to the second node N2 <1> , controls the second node N2 <1> Specifically, the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are at the first node N1. <1> The third transistor T3 transmits the first voltage signal to the third node N3. <1> , for the third node N3 <1> Charge the third node N3 <1> The voltage of the transistor T5 is high, thereby turning off the fifth transistor T5. The fourth transistor T4 transmits the first voltage signal to the second node N2. <1> , for the second node N2 <1> Charge the second node N2 <1> The voltage is high level.

[0244] At the second node N2 <1> Under the control of the voltage of , the sixth transistor T6 in the holding circuit 4 is turned off. At this time, the first voltage signal simultaneously charges the third capacitor C3.

[0245] The eighth transistor T8 in the second control circuit 6 is at the second node N2 <1> The voltage is controlled and turned off.

[0246] The ninth transistor T9 in the third control circuit 7 is turned off under the control of the second clock signal.

[0247] The seventh transistor T7 in the potential stabilization circuit 5 remains in the on state under the control of the second voltage signal, thereby enabling the first node N1 to be <1> The input signal at is transmitted to the fourth node N4 <1> , so that the fourth node N4 <1> The voltage of is low. At this time, the first capacitor C1 is charged at the same time.

[0248] At the first node N1 <1> (That is, the fourth node N4 <1> ) voltage, the second transistor T2 in the output circuit 2 is turned on, and the second clock signal is transmitted to the output signal terminal Gout <1> , as the output signal from the output signal terminal Gout <1> In this phase, the level of the second clock signal is high, and therefore, the level of the output signal is high.

[0249] In the scanning phase S12 , the level of the input signal is high, the level of the first clock signal is high, and the level of the second clock signal is low.

[0250] In response to the first clock signal, the first transistor T1 in the input circuit 1 is turned off. The first node N1 <1> There is no discharge path, so the first node N1 <1> The voltage of the first node N1 remains substantially unchanged, that is, <1> The voltage remains low.

[0251] At the first node N1 <1> Under the control of the voltage of the first control circuit 3 and the second clock signal, the first control circuit 3 transmits the first voltage signal to the second node N2 <1> , controls the second node N2 <1> Specifically, the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are at the first node N1. <1> The third node N3 is kept in the on state under the control of the voltage. <1> The voltage of the second node N2 is still high, and the fifth transistor T5 remains in the off state. <1> The voltage of the second node N2 is still high. <1> Under the control of the voltage of , the sixth transistor T6 in the circuit 4 is kept in the off state. At this time, the third capacitor C3 is continuously charged.

[0252] The eighth transistor T8 in the second control circuit 6 is at the second node N2 <1> The voltage is controlled to keep the OFF state.

[0253] The ninth transistor T9 in the third control circuit 7 is turned on under the control of the second clock signal.

[0254] The first capacitor C1 is discharged, so that the fourth node N4 <1> The voltage of the second transistor T2 in the output circuit 2 is kept at a low level at the first node N1. <1> (That is, the fourth node N4 <1> ) voltage to maintain the on state, and continuously transmit the second clock signal to the output signal terminal Gout <1> In this phase, the level of the second clock signal is low, and therefore, the level of the output signal is low.

[0255] In the first holding phase S21 , the level of the input signal is high, the level of the first clock signal is first maintained at a high level and then changes to a low level, and the level of the second clock signal is high.

[0256] Before the level of the first clock signal changes to a low level, the first node N1 <1> The voltage of the fourth node N4 <1> Based on this, the voltage of the second node N2 is kept at a low level. <1> The voltage of the third node N3 <1> The voltage of the output circuit 2 remains at a high level. The second transistor T2 in the output circuit 2 remains in the on state, continuously transmitting the second clock signal to the output signal terminal Gout. <1> Since the level of the second clock signal is a high level, the level of the output signal is a high level.

[0257] After the level of the first clock signal jumps to a low level, in response to the first clock signal, the first transistor T1 in the input circuit 1 is turned on, transmitting the input signal to the first node N1. <1> , for the first node N1 <1> Charge the first node N1 <1> The voltage is high level.

[0258] The seventh transistor T7 in the potential stabilization circuit 5 remains in the on state under the control of the second voltage signal, thereby enabling the first node N1 to be <1> The input signal at is transmitted to the fourth node N4 <1> , so that the fourth node N4 <1> The voltage of the first node N1 is high. <1> and the fourth node N4 <1> At this time, the first capacitor C1 is charged at the same time.

[0259] At the first node N1 <1> (That is, the fourth node N4 <1> ) voltage, the second transistor T2 in the output circuit 2 is turned off.

[0260] At the first node N1 <1> Under the control of the voltage of the second clock signal and the second clock signal, the first control circuit 3 transmits the second clock signal to the second node N2 <1> , controls the second node N2 <1> Specifically, the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are at the first node N1. <1> The third node N3 is turned off under the control of the voltage. <1> Since the level of the second clock signal is high, the third node N3 <1> The voltage of the second node N2 can be changed to a high level under the coupling effect of the second capacitor C2, thereby keeping the fifth transistor T5 in the off state. The third capacitor C3 is discharged, so that the second node N2 <1> The voltage of the second node N2 remains high. <1> Under the control of the voltage, the sixth transistor T6 in the keeping circuit 4 remains in the off state.

[0261] The eighth transistor T8 in the second control circuit 6 is at the second node N2 <1> The voltage is controlled to keep the OFF state.

[0262] Since the output signal terminal Gout of the shift register 100 <1> A load (ie, a pixel driving circuit in the sub-pixel P) is connected, so the output signal terminal Gout <1> The level of the output signal is the same as that of the first clock signal before the level jump, that is, the output signal terminal Gout <1> The level of the output signal is still high.

[0263] In the second holding phase S22 , the level of the input signal is high, the level of the first clock signal is high, and the level of the second clock signal is low.

[0264] In response to the first clock signal, the first transistor T1 in the input circuit 1 is turned off. The first node N1 <1> The voltage of the fourth node N4 <1> The voltage of the first node N1 remains substantially unchanged, that is, <1> The voltage of the fourth node N4 <1> The voltage of the second transistor T2 in the output circuit 2 is kept at a high level at the first node N1. <1> (That is, the fourth node N4 <1> ) voltage, and remains in the off state.

[0265] At the first node N1 <1> Under the control of the voltage of the second clock signal and the second clock signal, the first control circuit 3 transmits the second clock signal to the second node N2 <1> , controls the second node N2 <1> Specifically, the third transistor T3 and the fourth transistor T4 in the first control circuit 3 are at the first node N1. <1> The voltage of the third node N3 is kept in the off state. <1> Since the level of the second clock signal is low, the third node N3 <1> The voltage of the second capacitor C2 can be changed to a low level under the coupling effect of the second capacitor C2, thereby turning on the fifth transistor T5. The fifth transistor T5 transmits the second clock signal to the second node N2. <1> , for the second node N2 <1> Charge the second node N2 <1> The voltage is low.

[0266] The eighth transistor T8 in the second control circuit 6 is at the second node N2 <1> is turned on under the control of the voltage of , and transmits the first voltage signal to the fifth node N5.

[0267] The ninth transistor T9 in the third control circuit 7 is turned on under the control of the second clock signal, and transmits the first voltage signal from the fifth node N5 to the first node N1. <1> , for the first node N1 <1> Charge the first node N1 <1> The voltage is high level.

[0268] At the second node N2 <1> Under the control of the voltage, the sixth transistor T6 in the holding circuit 4 is turned on, and the first voltage signal is transmitted to the output signal terminal Gout <1> Output signal terminal Gout <1> The level of the output signal outputted is a high level.

[0269] It should be noted that the driving method of the shift register 100 may include multiple S21 stages and S22 stages that are performed in a sequential cycle. During this process, the eighth transistor T8 in the second control circuit 6 and the ninth transistor T9 in the third control circuit 7 remain in the on state, and the sixth transistor T6 in the holding circuit 4 remains in the on state, and continuously transmits the first voltage signal to the output signal terminal Gout. <1> , which makes the output signal terminal Gout <1> Continuously output high-level output signals. Every time the level of the second clock signal jumps from high to low, the level of the control electrode of the fifth transistor T5 will be coupled and pulled down once, and the fifth transistor T5 will be turned on, transmitting the second clock signal to the second node N2. <1> , and at the same time, the third capacitor C3 is charged so that the second node N2 <1> The voltage of the input signal can be kept at a low level. This process ends after the level of the input signal jumps to a low level.

[0270] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A shift register comprising: an input circuit electrically connected to the first clock signal terminal, the input signal terminal and the first node; The input circuit is configured to transmit an input signal received at the input signal terminal to the first node under the control of a first clock signal transmitted by the first clock signal terminal; an output circuit electrically connected to the first node, the second clock signal terminal and the output signal terminal; The output circuit is configured to transmit the second clock signal received at the second clock signal terminal to the output signal terminal under the control of the voltage of the first node; a first control circuit electrically connected to the first node, the first voltage signal terminal, the second clock signal terminal, and the second node; the first control circuit being configured to control the voltage of the second node under the control of the voltage of the first node and the second clock signal; and A holding circuit is electrically connected to the second node, the first voltage signal terminal and the output signal terminal; the holding circuit is configured to transmit the first voltage signal to the output signal terminal under the control of the voltage of the second node.

2. The shift register according to claim 1, wherein: The first control circuit includes a first sub-control circuit and a second sub-control circuit; The first sub-control circuit is electrically connected to the first node, the first voltage signal terminal, the second clock signal terminal, and a third node; the first sub-control circuit is configured to control the voltage of the third node under the control of the voltage of the first node and the second clock signal; The second sub-control circuit is electrically connected to the first node, the third node, the first voltage signal terminal, the second clock signal terminal and the second node; the second sub-control circuit is configured to control the voltage of the second node under the control of the voltage of the first node and the voltage of the third node.

3. The shift register according to claim 2, wherein: The first sub-control circuit includes: a third transistor and a second capacitor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first voltage signal terminal, and the second electrode of the third transistor is electrically connected to the third node; A first terminal of the second capacitor is electrically connected to the second clock signal terminal, and a second terminal of the second capacitor is electrically connected to the third node.

4. The shift register according to claim 2, wherein: The second sub-control circuit includes: a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

5. The shift register according to any one of claims 1 to 4, further comprising: Potential stabilization circuit; The potential stabilization circuit is electrically connected to the first node, the second voltage signal terminal and the fourth node; The potential stabilization circuit is configured to, under the control of the second voltage signal transmitted by the second voltage signal terminal, transmit the input signal from the first node to the fourth node and stabilize the voltage of the fourth node; In which, the output circuit is electrically connected to the fourth node and is electrically connected to the first node through the potential stabilization circuit; the output circuit is configured to transmit the second clock signal received at the second clock signal end to the output signal end under the control of the voltage of the fourth node. The shift register according to claim 5 , wherein: The potential stabilization circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the second voltage signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the fourth node.

7. The shift register according to any one of claims 1 to 6, further comprising: a second control circuit; The second control circuit is electrically connected to the second node, the first voltage signal terminal and the first node; The second control circuit is configured to transmit the first voltage signal to the first node under the control of the voltage of the second node.

8. The shift register according to claim 7, wherein: The second control circuit includes: an eighth transistor; The control electrode of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node.

9. The shift register according to claim 7 or 8, further comprising: a third control circuit; The third control circuit is electrically connected to the second clock signal terminal, the fifth node and the first node; The second control circuit is electrically connected to the fifth node, and is electrically connected to the first node through the third control circuit; The second control circuit is configured to transmit the first voltage signal to the fifth node under the control of the voltage of the second node; The third control circuit is configured to transmit the first voltage signal from the fifth node to the first node under the control of the second clock signal.

10. The shift register according to claim 9, wherein: The third control circuit includes: a ninth transistor; The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the fifth node, and the second electrode of the ninth transistor is electrically connected to the first node; In the case where the second control circuit includes an eighth transistor, a second electrode of the eighth transistor is electrically connected to the fifth node and is electrically connected to the first node through the ninth transistor.

11. The shift register according to any one of claims 1 to 10, wherein: The input circuit includes: a first transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the input signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

12. The shift register according to any one of claims 1 to 11, wherein: The output circuit includes: a second transistor and a first capacitor; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second clock signal terminal, and the second electrode of the second transistor is electrically connected to the output signal terminal; A first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the output signal terminal; When the potential stabilization circuit includes a seventh transistor, the control electrode of the second transistor is electrically connected to the fourth node and is electrically connected to the first node through the seventh transistor.

13. The shift register according to any one of claims 1 to 12, wherein: The holding circuit includes: a sixth transistor and a third capacitor; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the output signal terminal; A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to the first voltage signal end.

14. The shift register according to any one of claims 1 to 13, wherein: The shift register includes a plurality of transistors of the same conduction type.

15. The shift register according to any one of claims 1 to 14, wherein: The first clock signal and the second clock signal are inverted signals of each other.

16. A method for driving a shift register according to any one of claims 1 to 15, comprising: Phase I and Phase II; In the first phase, in response to a first clock signal received at a first clock signal terminal, the input circuit is turned on to transmit an input signal received at the input signal terminal to the first node; Under the control of the voltage of the first node, the output circuit is turned on to transmit the second clock signal received at the second clock signal terminal to the output signal terminal; Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first voltage signal transmitted by the first voltage signal terminal to the second node to control the voltage of the second node; Keeping the circuit off under the control of the voltage of the second node; In the second phase, in response to the first clock signal received at the first clock signal terminal, the input circuit is turned on to transmit the input signal received at the input signal terminal to the first node; Under the control of the voltage of the first node, the output circuit is turned off; Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the holding circuit is turned on to transmit the first voltage signal to the output signal terminal.

17. The shift register driving method according to claim 16, wherein: The first stage includes an input stage and a scanning stage; In the input phase, in response to the first clock signal, the input circuit is turned on to transmit the input signal to the first node; Under the control of the voltage of the first node, the output circuit is turned on to transmit the second clock signal to the output signal terminal; Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first voltage signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the holding circuit is turned off; In the scanning phase, in response to the first clock signal, the input circuit is turned off; The voltage of the first node remains substantially unchanged, and the output circuit remains in an on state under the control of the voltage of the first node, transmitting the second clock signal to the output signal terminal; Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the first voltage signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the holding circuit is turned off; The second stage includes: a first holding stage and a second holding stage; In the first holding phase, in response to the first clock signal, the input circuit is turned on to transmit the input signal to the first node; Under the control of the voltage of the first node, the output circuit is turned off; Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the holding circuit is turned off; In the second holding phase, the input circuit is turned off in response to the first clock signal; The voltage of the first node remains substantially unchanged, and the output circuit remains in an off state under the control of the voltage of the first node; Under the control of the voltage of the first node and the second clock signal, the first control circuit transmits the second clock signal to the second node to control the voltage of the second node; Under the control of the voltage of the second node, the holding circuit is turned on to transmit the first voltage signal to the output signal terminal.

18. A scan driving circuit comprising: A plurality of cascaded shift registers according to any one of claims 1 to 15; Except for the last i shift registers, the output signal terminal of the Nth shift register is electrically connected to the input signal terminal of the N+ith shift register; wherein N and i are both positive integers, and i<N.

19. The scan driving circuit according to claim 18, further comprising: at least one first clock signal line and at least one second clock signal line; In the case of i=1, A first clock signal line is electrically connected to the first clock signal terminal of the 2N-1th shift register and the second clock signal terminal of the 2Nth shift register; A second clock signal line is electrically connected to the second clock signal terminal of the 2N-1th shift register and the first clock signal terminal of the 2Nth shift register.

20. A display device comprising: The scan driving circuit according to claim 18 or 19.

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