DISPLAY PLATFORMS AND THEIR MANUFACTURING METHODS, AND DISPLAY EQUIPMENT

Abstract

The invention proposes a display substrate and a method for its fabrication, and a display device. The display substrate consists of: a base; a control circuit layer arranged on the base; a light-emitting structure layer arranged on the side of the control circuit layer furthest from the base; the light-emitting structure layer has a pixel-determining layer and an organic light-emitting layer; the pixel-determining layer defines many sub-pixel regions and has a first hole that at least partially exposes the control circuit layer; the organic light-emitting layer is placed in the sub-pixel regions and overlaps the first hole of the pixel-determining layer; and a color film structure layer arranged on the side of the light-emitting structure furthest from the base; the color film structure layer has a color film and a black matrix; the black matrix has a second hole that at least partially exposes the first hole; the color film is arranged in the second hole; the black matrix has a first sub-face edge; and the first sub-face edge has a folded line structure.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 7, 2021, with application number 202110764582.0 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a display substrate, comprising: a substrate; a driving circuit layer arranged on the substrate; a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the light-emitting structure layer comprising a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel areas, and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel area and overlapping with the first opening of the pixel defining layer; and a color film structure layer arranged on a side of the light-emitting structure layer away from the substrate, the color film structure layer comprising a color film and a black matrix, the black matrix having a second opening at least partially exposing the first opening, the color film being arranged in the second opening, the black matrix comprising a first sub-side, and the first sub-side having a fold line structure.

[0007] In an exemplary embodiment, the first sub-side has a plurality of folded corners, and the first sub-side has a greater number of folded corners in an area farther from a center line of the sub-pixel area.

[0008] In an exemplary embodiment, the sub-pixel area includes a center line, a first reference line, a second reference line, a third reference line and a fourth reference line in sequence along the first direction, and the fourth reference line coincides with the farthest boundary of the first sub-side away from the center line, wherein: the distance between the first reference line and the center line of the sub-pixel area is k, the distance between the first reference line and the second reference line is n1, the distance between the second reference line and the third reference line is n2, and the distance between the third reference line and the fourth reference line is n3; k+n1+n2+n3=L / 2, L is the length of the sub-pixel area along the first direction; the number of corners x between the center line and the first reference line, the number of corners y between the first reference line and the second reference line, and the number of corners z between the second reference line and the third reference line of the first sub-side satisfy the following conditions: x≤y≤z.

[0009] In an exemplary embodiment, n1=n2=n3.

[0010] In an exemplary embodiment, the number of folded corners x of the first sub-side between the center line and the first reference line is ≥3; the number of folded corners y of the first sub-side between the first reference line and the second reference line is ≥3; and the number of folded corners z of the first sub-side between the second reference line and the third reference line is ≥3.

[0011] In an exemplary embodiment, the first sub-side has at least two approximately equal fold angles between the center line and the first reference line; the first sub-side has at least two approximately equal fold angles between the first reference line and the second reference line; and the first sub-side has at least two approximately equal fold angles between the second reference line and the third reference line.

[0012] In an exemplary embodiment, the first sub-side has at least one first fold angle between the center line and the first reference line, the first sub-side has at least one second fold angle between the first reference line and the second reference line, and the first sub-side has at least one third fold angle between the second reference line and the third reference line, and the angles of the first fold angle, the second fold angle and the third fold angle are approximately equal.

[0013] In an exemplary embodiment, the number of folded corners x of the first sub-side between the center line and the first reference line is ≥3, the number of folded corners y of the first sub-side between the first reference line and the second reference line is ≥4, and the number of folded corners z of the first sub-side between the second reference line and the third reference line is ≥5.

[0014] In an exemplary embodiment, the first sub-side includes at least three fold angles between the center line and the first reference line: x1, x2, and x3, wherein x2 is approximately equal to x3, and x1+x2 is approximately equal to 360 degrees; the first sub-side includes at least four fold angles between the first reference line and the second reference line: y1, y2, y3, and y4, wherein y1 is approximately equal to y2, and y3+y4 is approximately equal to 360 degrees; the first sub-side includes at least four fold angles between the second reference line and the third reference line: z1, z2, z3, and z4, wherein z1 is approximately equal to z2, and z3+z4 is approximately equal to 360 degrees.

[0015] In an exemplary embodiment, the first sub-side has at least three fold angles with substantially equal angles between the center line and the first reference line.

[0016] In an exemplary embodiment, the angles of the at least three corners of the first sub-side between the center line and the first reference line are equal to n times 45 degrees, where n=3 or 5.

[0017] In an exemplary embodiment, the first sub-side has a first width along the first direction; the driving circuit layer includes at least one first signal line, the first signal line has a second width along the first direction, the orthographic projection of the first signal line on the substrate and the orthographic projection of the first sub-side on the substrate have a first overlap, and the first overlap has a third width along the first direction.

[0018] In an exemplary embodiment, an orthographic projection of the first signal line on the substrate, an orthographic projection of the first sub-side on the substrate, and an orthographic projection of the color filter on the substrate have a first overlap.

[0019] In an exemplary embodiment, the first signal line has a fold line structure, the black matrix has multiple sub-sides, and the number of fold corners of the first signal line in any sub-pixel area is less than the number of fold corners of at least one sub-side of the black matrix, and greater than the number of fold corners of at least one other sub-side of the black matrix.

[0020] In an exemplary embodiment, the first width is l1, the second width is l2, the sub-pixel area includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel area is k, and the length of the sub-pixel area along the first direction is L, then: 10*l1≤L≤10*l2; 2*k<L≤3*k.

[0021] In an exemplary embodiment, the first width is l1, the second width is l2, the third width is l3, the sub-pixel area includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel area is k, and the length of the sub-pixel area along the first direction is L, then: 6*l2<L<7*l2; 20*l3<L<35*l3; 3.5*l3<l2≤4*l3.

[0022] In an exemplary embodiment, the orthographic projection of the color film on the substrate at least partially covers the orthographic projection of the first opening of the pixel defining layer on the substrate; in a third direction, the maximum thickness of the color film is greater than the maximum thickness of the first sub-side, and the color film at least partially covers the first sub-side, and the third direction is the direction along the substrate toward the color film structure layer.

[0023] In an exemplary embodiment, the black matrix has a second thickness l4 in a third direction, and the second thickness is between 0.9 micrometers and 1.2 micrometers. The third direction is a direction along the base substrate toward the color filter structure layer.

[0024] In an exemplary embodiment, the first sub-side includes a third sub-line segment that is neither parallel to nor perpendicular to the first direction and the second direction, and the black matrix includes a plurality of the third sub-line segments.

[0025] In an exemplary embodiment, the first sub-side includes four separately arranged third sub-line segments, and the four third sub-line segments are spaced apart from each other.

[0026] In an exemplary embodiment, the first sub-side has a stepped structure.

[0027] In an exemplary embodiment, the black matrix further includes a second sub-side opposite to the first sub-side, and the second sub-side has a fold line structure, and the first sub-side and the second sub-side are asymmetrically arranged relative to the center line of the sub-pixel area.

[0028] In an exemplary embodiment, the sub-pixel area includes an eighth reference line, a seventh reference line, a sixth reference line, a fifth reference line, a center line, a first reference line, a second reference line, a third reference line, and a fourth reference line in sequence along the first direction, the fourth reference line coincides with the farthest boundary of the first sub-side away from the center line, and the eighth reference line coincides with the farthest boundary of the second sub-side away from the center line, wherein: the distance between the first reference line and the center line of the sub-pixel area is k, the distance between the fifth reference line and the center line of the sub-pixel area is k, the distance between the first reference line and the second reference line is n1, the distance between the sixth reference line and the fifth reference line is n1, the distance between the second reference line and the third reference line is n2, the distance between the seventh reference line and the sixth reference line is n2, and the distance between the seventh reference line and the sixth reference line is n2. The distance between the third reference line and the fourth reference line is n3, and the distance between the eighth reference line and the seventh reference line is n3; k+n1+n2+n3=L / 2, L is the length of the sub-pixel area along the first direction; the number of corners x of the first sub-side between the center line and the first reference line, the number of corners y of the first sub-side between the first reference line and the second reference line, the number of corners z of the first sub-side between the second reference line and the third reference line, the number of corners x' of the second sub-side between the center line and the fifth reference line, the number of corners y' of the second sub-side between the fifth reference line and the sixth reference line, and the number of corners z' of the second sub-side between the sixth reference line and the seventh reference line satisfy the following conditions: x=x', y≠y', z≠z'.

[0029] In an exemplary embodiment, the black matrix further includes a third sub-side and a fourth sub-side arranged opposite to each other, the first sub-side, the third sub-side, the second sub-side and the fourth sub-side are connected end to end, and the third sub-side and the fourth sub-side have a straight bar shape or a substantially straight bar shape.

[0030] In an exemplary embodiment, the sub-pixel area includes a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area, the first sub-pixel area includes a first light-emitting unit and a first color filter, the second sub-pixel area includes a second light-emitting unit and a second color filter, the third sub-pixel area includes a third light-emitting unit and a third color filter, the orthographic projection of the first color filter on the substrate covers the orthographic projection of the first light-emitting unit on the substrate, the orthographic projection of the second color filter on the substrate covers the orthographic projection of the second light-emitting unit on the substrate, and the orthographic projection of the third color filter on the substrate covers the orthographic projection of the third light-emitting unit on the substrate.

[0031] In an exemplary embodiment, the second light-emitting unit includes two discrete sub-light-emitting units, and the second color filter includes two discrete sub-color filters, the orthographic projection of one sub-color filter on the substrate covers the orthographic projection of one sub-light-emitting unit on the substrate, and the orthographic projection of the other sub-color filter on the substrate covers the orthographic projection of the other sub-light-emitting unit on the substrate.

[0032] In an exemplary embodiment, the display substrate further includes an encapsulation layer disposed on a side of the color filter structure layer away from the light emitting structure layer, and an orthographic projection of the encapsulation layer on the base covers an orthographic projection of the color filter structure layer on the substrate.

[0033] In an exemplary embodiment, the sub-pixel area includes a first sub-pixel area, a second sub-pixel area, a third sub-pixel area and a fourth sub-pixel area, the first sub-pixel area includes a first light-emitting unit and a first color filter, the second sub-pixel area includes a second light-emitting unit and a second color filter, the third sub-pixel area includes a third light-emitting unit and a third color filter, the fourth sub-pixel area includes a fourth light-emitting unit and a fourth color filter, the orthographic projection of the first color filter on the substrate covers the orthographic projection of the first light-emitting unit on the substrate, the orthographic projection of the second color filter on the substrate covers the orthographic projection of the second light-emitting unit on the substrate, the orthographic projection of the third color filter on the substrate covers the orthographic projection of the third light-emitting unit on the substrate, and the orthographic projection of the fourth color filter on the substrate covers the orthographic projection of the fourth light-emitting unit on the substrate.

[0034] In an exemplary embodiment, the display substrate further includes an encapsulation layer covering the color filter structure layer, the encapsulation layer covers the first color filter, the second color filter and the third color filter, and the fourth color filter is provided in the same layer and material as at least part of the encapsulation layer.

[0035] In an exemplary embodiment, the first sub-pixel region is a red sub-pixel region, the second sub-pixel region is a green sub-pixel region, the third sub-pixel region is a blue sub-pixel region, and the fourth sub-pixel region is a white sub-pixel region.

[0036] In an exemplary embodiment, the first sub-side of the white sub-pixel region is connected to the first sub-side of the red sub-pixel region, and the morphology of the first sub-side of the white sub-pixel region is different from that of the first sub-side of the red sub-pixel region.

[0037] In an exemplary embodiment, the black matrix also includes a second sub-side arranged opposite to the first sub-side, the second sub-side of the green sub-pixel area is adjacent to the second sub-side of the blue sub-pixel area, and the number of folding angles of the second sub-side of the green sub-pixel area is greater than the number of folding angles of the second sub-side of the blue sub-pixel area.

[0038] In an exemplary embodiment, the black matrix between two adjacent sub-pixel regions is conformal.

[0039] In an exemplary embodiment, the number of folding angles of the black matrix between the white sub-pixel region and the green sub-pixel region is greater than the number of folding angles of the black matrix between the red sub-pixel region and the blue sub-pixel region.

[0040] In an exemplary embodiment, the areas of sub-pixel regions of different colors are different.

[0041] In an exemplary embodiment, the display substrate further includes a blank structure, and an orthographic projection of the blank structure on the substrate does not overlap with an orthographic projection of the sub-pixel region on the substrate.

[0042] In an exemplary embodiment, a ratio of an area of ​​the blank structure to an area of ​​the sub-pixel region is greater than or equal to 45%.

[0043] In an exemplary embodiment, a ratio of an area of ​​the blank structure to an area of ​​the sub-pixel region is equal to 46%.

[0044] In an exemplary embodiment, the blank structure has a fifth width along the first direction, and the fifth width is equal to or substantially equal to the total length of all fold line structures of the first sub-side.

[0045] In an exemplary embodiment, the multiple sub-pixel areas include a white sub-pixel area and a red sub-pixel area, the blank structure has a first sub-edge adjacent to the first sub-side of the white sub-pixel area and the first sub-side of the red sub-pixel area, and the shape of the first sub-edge is conformal to the shape of the first sub-side of the white sub-pixel area and the first sub-side of the red sub-pixel area.

[0046] In an exemplary embodiment, the driving circuit layer further includes a repair structure, and an orthographic projection of the repair structure on the substrate at least partially overlaps with an orthographic projection of the blank structure on the substrate.

[0047] In an exemplary embodiment, the plurality of sub-pixel regions include a red sub-pixel region and a blue sub-pixel region, and the repair structures of the red sub-pixel region and the repair structures of the blue sub-pixel region are at least partially symmetrical and at least partially asymmetrical.

[0048] In an exemplary embodiment, the light emitting structure layer further includes an anode, the first opening at least partially exposes the anode, and at least one sub-pixel region includes a plurality of discretely arranged sub-anode blocks.

[0049] In an exemplary embodiment, the plurality of discretely disposed sub-anode blocks includes two.

[0050] In an exemplary embodiment, the two sub-anode blocks have different morphologies.

[0051] In an exemplary embodiment, the driving circuit layer includes anode holes electrically connected to the two sub-anode blocks, respectively.

[0052] In an exemplary embodiment, the driving circuit layer further includes a repair structure, and the two sub-anode blocks are electrically connected to each other and to the repair structure.

[0053] An embodiment of the present disclosure further provides a display device, comprising: the display substrate as described above.

[0054] The present disclosure also provides a method for preparing a display substrate, the method comprising:

[0055] forming a driving circuit layer on the substrate;

[0056] forming a light-emitting structure layer on a side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel region and overlapping with the first opening of the pixel defining layer;

[0057] A color film structure layer is formed on a side of the light-emitting structure layer away from the substrate, the color film structure layer includes a color film and a black matrix, the black matrix has a second opening that at least partially exposes the first opening, the color film is arranged in the second opening, the black matrix includes a first sub-side, and the first sub-side has a fold line structure.

[0058] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0060] FIG1 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure;

[0061] 2 to 5 are schematic diagrams of pixel arrays of four display substrates according to exemplary embodiments of the present disclosure;

[0062] FIG6 is a schematic structural diagram of a sub-pixel according to an exemplary embodiment of the present disclosure;

[0063] FIG7 is a schematic cross-sectional view of the OO' region in FIG6;

[0064] FIG8 is a schematic structural diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure;

[0065] FIG9 is a schematic structural diagram of a first sub-side of a black matrix in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0066] FIG10 is a schematic structural diagram of the first sub-side of a black matrix in another sub-pixel according to an exemplary embodiment of the present disclosure;

[0067] FIG11 is a schematic diagram of the overlapping structure of a first signal line and a first sub-side in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0068] FIG12 is a schematic diagram of the cross-sectional structure of the aa' region in FIG11;

[0069] FIG13 is a schematic structural diagram of a first opening and a second opening in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0070] FIG14 is a schematic diagram of the structure of a color filter in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0071] FIG15 is a schematic diagram of the overlapping structure of the first signal line and the first sub-side in another sub-pixel according to an exemplary embodiment of the present disclosure;

[0072] FIG16 is a schematic structural diagram of a first sub-side in another sub-pixel according to an exemplary embodiment of the present disclosure;

[0073] FIG17 is a schematic structural diagram of a first sub-side and a second sub-side in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0074] FIG18 is a schematic structural diagram of a second sub-side in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0075] FIG19 is a schematic structural diagram of a black matrix in adjacent pixels according to an exemplary embodiment of the present disclosure;

[0076] FIG20 is a schematic structural diagram of another black matrix in adjacent pixels according to an exemplary embodiment of the present disclosure;

[0077] FIG21 is a schematic diagram of a color filter structure in a sub-pixel of different colors according to an exemplary embodiment of the present disclosure;

[0078] FIG22 is a schematic diagram of a packaging structure of sub-pixels of different colors according to an exemplary embodiment of the present disclosure;

[0079] FIG23 is a schematic diagram of a blank structure in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0080] FIG24 is a schematic diagram of a repair structure in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0081] FIG25 is a schematic diagram of a repair structure in another sub-pixel according to an exemplary embodiment of the present disclosure;

[0082] FIG26 is a schematic diagram of a repair structure in another sub-pixel according to an exemplary embodiment of the present disclosure;

[0083] FIG27 is a schematic structural diagram of an anode in a sub-pixel according to an exemplary embodiment of the present disclosure;

[0084] FIG28 is a schematic diagram of the cross-sectional structure of the bb' region in FIG27. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0086] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0087] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0088] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0089] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0090] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0091] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0092] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0093] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0094] In this specification, "two angles are substantially equal" means that the ratio between the two angles is within the range of 0.9 to 1.1, and thus includes the range of 0.95 to 1.05. Thus, the sum of the two angles being substantially equal to 360° may include the range of 342° to 378°.

[0095] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0096] "Approximately" in this disclosure means that the limits are not strictly defined, and numerical values ​​within the range of process and measurement errors are allowed. Figure 1 is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver to the scan signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of sub-pixel rows, where n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver can sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be constructed in the form of a shift register, and can generate a scan signal by sequentially transmitting the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of a clock signal, and m can be a natural number. The sub-pixel array may include a plurality of pixel sub-Pxij. Each pixel sub-Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, and i and j can be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0097] Figures 2 to 4 are schematic diagrams of the planar structures of three display substrates according to embodiments of the present disclosure. As shown in Figures 2 to 4, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P including a first light-emitting unit (sub-pixel) P1 emitting a first color light, a second light-emitting unit P2 emitting a second color light, and a third light-emitting unit P3 emitting a third color light. The first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of the light-emitting unit in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the light-emitting unit in which they are located.

[0098] In an exemplary embodiment, the first light emitting unit may be a red (R) light emitting unit, the second light emitting unit may be a green (G) light emitting unit, and the third light emitting unit may be a blue (B) light emitting unit. This disclosure is not limited herein.

[0099] In an exemplary embodiment, as shown in FIG5 , at least one of the plurality of pixel units P further includes a fourth light-emitting unit P4 that emits a fourth color light. Exemplarily, the fourth light-emitting unit P4 may be a white (W) light-emitting unit, which is not limited in the present disclosure. The fourth light-emitting unit P4 may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the fourth light-emitting unit P4 is respectively connected to the scan signal line, the data signal line, and the light-emitting signal line. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in the fourth light-emitting unit P4 is connected to the pixel driving circuit in the fourth light-emitting unit P4. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the light-emitting unit in which it is located.

[0100] In an exemplary embodiment, the shape of the light-emitting units in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal. When the pixel unit includes three light-emitting units, the three light-emitting units can be arranged in parallel horizontally, vertically, or in a triangular pattern. When the pixel unit includes four light-emitting units, the four light-emitting units can be arranged in parallel horizontally, vertically, or in a square pattern. This disclosure is not limited hereto.

[0101] With the continuous development of display technology, OLED technology is increasingly being used in transparent displays. Transparent display is an important personalized display field in display technology. It refers to the display of images in a transparent state. Viewers can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR), augmented reality (AR) and 3D display functions. Transparent display devices using AMOLED technology usually divide each pixel into a display area and a transparent area. The display area is equipped with pixel driving circuits and light-emitting elements to realize image display, and the transparent area allows light to pass through.

[0102] Displays larger than 27 inches are considered large-screen displays. In large-size transparent display products, when external light passes through the gaps between adjacent pixel columns, it can produce strong diffraction, interference, and scattered color separation effects, resulting in poor display quality on large-size transparent display panels.

[0103] An exemplary embodiment of the present disclosure provides a display substrate, which may include a substrate, a driving circuit layer arranged on the substrate; a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defines a plurality of sub-pixel areas, and has a first opening that at least partially exposes the driving circuit layer, the organic light-emitting layer is located in the sub-pixel area and overlaps with the first opening of the pixel defining layer; and a color film structure layer arranged on a side of the light-emitting structure layer away from the substrate, the color film structure layer including a color film and a black matrix, the black matrix of at least one sub-pixel area having a second opening that at least partially exposes the first opening, the color film being arranged in the second opening, the black matrix of at least one sub-pixel area having at least one side edge, and the at least one side edge having a fold line structure.

[0104] The display substrate of the embodiment of the present disclosure reduces reflectivity and improves light purity by arranging a color film and a black matrix on the color film structure layer, and the black matrix has a side with a fold line structure. The display substrate of the embodiment of the present disclosure does not require the use of a polarizing plate, which reduces the cost of the display substrate, reduces the thickness of the display substrate, improves the bendability of the display substrate, and reduces grating effects such as diffraction effect, interference effect and scattered color separation, thereby improving the display effect.

[0105] FIG6 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure, and FIG7 is a schematic cross-sectional structural diagram of the OO' region in FIG6 , illustrating the structure of a sub-pixel. As shown in FIG6 and FIG7 , an exemplary embodiment of the present disclosure provides a display substrate, including:

[0106] substrate 101;

[0107] A driving circuit layer 102 is provided on the substrate 101;

[0108] A light-emitting structure layer 103 is provided on a side of the driving circuit layer 102 away from the substrate 101. The light-emitting structure layer 103 includes a pixel defining layer 103b and an organic light-emitting layer 103c. The pixel defining layer 103b defines a plurality of sub-pixel regions and has a first opening K1 that at least partially exposes the driving circuit layer 102. The organic light-emitting layer 103c is located in the sub-pixel region and overlaps with the first opening K1 of the pixel defining layer 103b.

[0109] And a color film structure layer 104 is arranged on the side of the light-emitting structure layer 103 away from the substrate 101, the color film structure layer 104 includes a color film 104b and a black matrix 104a, the black matrix 104a has a second opening K2 that at least partially exposes the first opening K1, the color film 104b is arranged in the second opening K2, the black matrix 104a includes a first sub-side 1041, and the first sub-side 1041 has a broken line structure.

[0110] In an exemplary embodiment, the display substrate further includes an encapsulation layer 105 disposed on a side of the color filter structure layer 104 away from the light emitting structure layer 103. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0111] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. FIG8 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG8 , the pixel driving circuit is a 3T1C structure, which may include three transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C STand six signal lines (data signal line Dn, first scan signal line Gn, second scan signal line Sn, compensation line Se, first power line VDD, and second power line VSS). In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The gate electrode of the first transistor T1 is coupled to the first scan signal line Gn, the first electrode of the first transistor T1 is coupled to the data signal line Dn, and the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2. Under the control of the first scan signal line Gn, the first transistor T1 is configured to receive a data signal transmitted by the data signal line Dn, causing the gate electrode of the second transistor T2 to receive the data signal. The gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, and the second electrode of the second transistor T2 is coupled to the first electrode of the OLED. The second transistor T2 is configured to generate a corresponding current at its second electrode under the control of the data signal received at its gate electrode. The gate electrode of the third transistor T3 is coupled to the second scan signal line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, and the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The first electrode of the OLED is coupled to the second electrode of the second transistor T2, and the second electrode of the OLED is coupled to the second power line VSS. The OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2. The storage capacitor C ST The first electrode of the second transistor T2 is coupled to the gate electrode of the storage capacitor C ST The second electrode of the second transistor T2 is coupled to the second electrode of the storage capacitor C ST Used to store the potential of the gate electrode of the second transistor T2.

[0112] In an exemplary embodiment, the signal of the first power line VDD continuously provides a high-level signal, and the signal of the second power line VSS continuously provides a low-level signal. The first transistor T1 to the third transistor T3 can be P-type transistors, or they can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the third transistor T3 can include P-type transistors and N-type transistors. In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0113] In an exemplary embodiment, the light-emitting structure layer 103 may include an anode 103a, a pixel-defining layer 103b, an organic light-emitting layer 103c, and a cathode 103d. The pixel-defining layer 103b defines multiple sub-pixel regions and has a first opening K1 that at least partially exposes the driving circuit layer 102. The anode 103a is connected to the drain electrode of the transistor in the driving circuit layer 102 through a via hole. The organic light-emitting layer 103c is connected to the anode 103a, and the cathode 103d is connected to the organic light-emitting layer 103c. Driven by the anode 103a and cathode 103d, the organic light-emitting layer 103c emits light of a corresponding color. The color filter structure layer 104 may include a black matrix 104a and a color filter 104b. The black matrix 104a has a second opening K2 that at least partially exposes the first opening K1. The color filter 104b is disposed within the second opening K2. The encapsulation layer 105 may include a first encapsulation layer and a second encapsulation layer stacked together. The first encapsulation layer may be made of organic material, and the second encapsulation layer may be made of inorganic material, which can ensure that external water vapor cannot enter the light-emitting structure layer and the color filter structure layer.

[0114] Figure 9 is a schematic diagram of the structure of the first sub-side in the black matrix of a sub-pixel region in an exemplary embodiment of the present disclosure. As shown in Figures 6 and 9, in an exemplary embodiment, within a sub-pixel region, the black matrix includes a first sub-side 1041. The first sub-side 1041 has a certain width along a first direction and has a fold line structure with multiple fold angles. The farther away from the center line A of the sub-pixel region, the more fold angles there are.

[0115] The display substrate of the embodiment of the present disclosure, by setting a fold line structure of the first sub-side edge 1041 of the black matrix, has more fold angles in the area farther away from the sub-pixel center line A, further reducing the diffraction and interference effects of the display panel and improving the display effect.

[0116] As shown in Figure 6, the sub-pixel area has a sub-side I and a sub-side III arranged along the first direction and a sub-side II and a sub-side IV arranged along the second direction, and the sub-side I, the sub-side II, the sub-side III and the sub-side IV are connected end to end. The sub-side in the embodiment of the present disclosure is defined as the outer contour line of the sub-pixel area (the outer contour line is the boundary away from the center of the sub-pixel area). For example, if in a certain direction, the outer contour line of the black matrix is ​​the outermost contour line of the sub-pixel area, then in this direction, the sub-side of the sub-pixel is the outer contour line of the black matrix; and if in a certain direction, the outer contour line of the pixel defining layer is the outermost contour line of the sub-pixel area, then in this direction, the sub-side of the sub-pixel is the outer contour line of the pixel defining layer.

[0117] In an exemplary embodiment, the sub-pixel region has a centerline A, which can be defined as the centerline of two oppositely disposed sub-sides. In an exemplary embodiment, if one or both of the two oppositely disposed sub-sides have a zigzag segment, the centerlines of the two zigzag segments that are farthest from each other in the two oppositely disposed sub-sides are selected as the centerline of the sub-pixel region. For example, as shown in FIG6 , the two oppositely disposed sub-sides can be sub-side I and sub-side III, or can be sub-side II and sub-side IV. The following description assumes that the two oppositely disposed sub-sides are sub-sides II and sub-side IV.

[0118] In an exemplary embodiment, the length of the sub-pixel area along the first direction is L. As shown in FIG6 , the length L of the sub-pixel area along the first direction can be defined as the farthest distance between two edges of the sub-pixel area disposed opposite each other along the first direction, that is, the distance between the leftmost edge of the sub-pixel area and the rightmost edge of the sub-pixel area. A first reference line B can be set at a distance k from the center line A, and the distance k between the center line A and the first reference line B is the length of the shortest line segment between the center line A and the first reference line B. In this embodiment, since the center line A is parallel to the first reference line B, the distance k between the center line A and the first reference line B is the length of the line segment between the center line A and the first reference line B, which is perpendicular to the center line A and the first reference line B. The sub-pixel area may further include a second reference line C, a third reference line D, and a fourth reference line E. Among them, the sub-side IV has a sub-boundary m farthest from the center line A (if the sub-side IV is a straight line, the sub-boundary m is the sub-side IV). The fourth reference line E overlaps with the sub-boundary m. That is, the orthographic projection of the fourth reference line E on the substrate overlaps with the orthographic projection of the sub-boundary m of the sub-pixel 10 on a sub-side that is farthest from the center line. The distances between the first reference line B and the second reference line C, the second reference line C and the third reference line D, and the third reference line D and the fourth reference line E are identical. As shown in FIG6 or FIG9 , the distance between the first reference line B and the second reference line C is n1, the distance between the second reference line C and the third reference line D is n2, and the distance between the third reference line D and the fourth reference line E is n3. In an exemplary embodiment, n1 = n2 = n3; and k + n1 + n2 + n3 = L / 2. In this embodiment, the center line A, the first reference line B, the second reference line C, the third reference line D, and the fourth reference line E all extend along the second direction.

[0119] In an exemplary embodiment, within a sub-pixel region, the black matrix 104a has at least one first sub-side 1041 having a certain width along a first direction. The first sub-side 1041 has multiple corners. The number x of corners between the center line A and the first reference line B, the number y of corners between the first reference line B and the second reference line C, and the number z of corners between the second reference line C and the third reference line D of the first sub-side 1041 satisfy the following condition: x≤y≤z.

[0120] In this embodiment, within the range of a vertical distance from the center line A less than or equal to k (i.e., between the center line A and the first reference line B), the number of folded corners included in the first sub-side 1041 is x; the folded corner described in the embodiment of the present disclosure refers to an angle less than 360° and not equal to 180° toward the side of the center line A. Within the range of a vertical distance from the center line between k and (k+(L / 2-k) / 3) (i.e., between the first reference line B and the second reference line C), the number of folded corners included in the first sub-side 1041 is y; within the range of a vertical distance from the center line between (k+(L / 2-k) / 3) and (k+2(L / 2-k) / 3) (i.e., between the second reference line C and the third reference line D), the number of folded corners included in the first sub-side 1041 is z; wherein x, y, and z satisfy the following conditions: x≤y≤z.

[0121] In another exemplary embodiment, the fold angle is not equal to 90°, that is, the fold angle refers to an angle toward the center line A that is less than 360° and is not equal to 180° and 90°.

[0122] In another exemplary embodiment, the fold angle is an obtuse angle, that is, an angle smaller than 360° and larger than 90° toward the center line A, but not equal to 180°.

[0123] In another exemplary embodiment, the number of corners x between the center line A and the first reference line B, the number of corners y between the first reference line B and the second reference line C, and the number of corners z between the second reference line C and the third reference line D of the first sub-side 1041 satisfy the following conditions: x≥3, y≥3, z≥3.

[0124] In an exemplary embodiment, within a range where the vertical distance from the center line A is less than or equal to k, the first sub-side 1041 includes at least three fold angles, and at least two of the at least three fold angles are substantially equal;

[0125] In the range of a vertical distance k to (k+(L / 2-k) / 3) from the center line A, the first sub-side 1041 includes at least three fold angles, and at least two of the at least three fold angles are substantially equal;

[0126] Within the range of a vertical distance from the center line A of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3), the first sub-side 1041 includes at least three fold angles, and at least two of the at least three fold angles are approximately equal.

[0127] Exemplarily, as shown in FIG10 , within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the first sub-side 1041 includes at least three fold angles: x1, x2, and x3, and two of the fold angles are approximately equal. Exemplarily, x2 and x3 are approximately equal. Within a range where the vertical distance from the center line A is between k and (k+(L / 2-k) / 3) (i.e., between the first reference line B and the second reference line C), the first sub-side 1041 includes at least three fold angles y1, y2, and y3, and two of the fold angles are approximately equal. Exemplarily, y2 and y3 are approximately equal. Within the range of a vertical distance from the center line A of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) (i.e., between the second reference line C and the third reference line D), the first sub-side 1041 includes at least three fold angles: z1z2 and z3, and two of the fold angles are approximately equal. For example, z1 and z4 are approximately equal.

[0128] In another exemplary embodiment, within the range of a vertical distance from the center line A being less than or equal to k, the first sub-side 1041 has at least one first fold angle; within the range of a vertical distance from the center line being k to (k+(L / 2-k) / 3), the first sub-side 1041 has at least one second fold angle; within the range of a vertical distance from the center line being (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3), the first sub-side 1041 has at least one third fold angle, wherein the angles of the first fold angle, the second fold angle and the third fold angle are approximately equal.

[0129] For example, as shown in FIG10 , within a range where the vertical distance from the center line A is less than or equal to k, the first sub-side 1041 has a first fold angle x1 = 135°; within a range where the vertical distance from the center line A is k to (k+(L / 2-k) / 3), the first sub-side 1041 has a second fold angle y1 = 135°; within a range where the vertical distance from the center line A is (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3), the first sub-side 1041 has a third fold angle z1 = 135°. The disclosed embodiment makes the angles of some fold angles in the black matrix approximately equal, which is more conducive to the implementation of the process.

[0130] In another exemplary embodiment, the number of corners x between the center line A and the first reference line B, the number of corners y between the first reference line B and the second reference line C, and the number of corners z between the second reference line C and the third reference line D of the first sub-side 1041 satisfy the following conditions: x≥3, y≥4, z≥5.

[0131] For example, as shown in FIG10 , within the range of a vertical distance from the center line A of less than or equal to k, the black matrix 104a has three fold angles x1, x2, and x3; within the range of a vertical distance from the center line A of k to (k+(L / 2-k) / 3), the black matrix 104a has four fold angles y1, y2, y3, and y4; within the range of a vertical distance from the center line A of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3), the black matrix 104a has six fold angles z1, z2, z3, z4, z5, and z6. The embodiment of the present disclosure allows the number of fold angles to increase as the distance from the sub-pixel center line increases, thereby reducing grating effects, such as diffraction effect, interference effect, and scattered color separation.

[0132] In another exemplary embodiment, within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three fold angles: x1, x2, and x3, wherein x2 and x3 are substantially equal, and x1+x2 is substantially equal to 360°; within a range where the vertical distance from the center line A is between k and (k+(L / 2-k) / 3) (i.e., between the first reference line B and the second reference line C), the black matrix 104a includes At least four fold angles y1, y2, y3 and y4, wherein y1 is approximately equal to y2, and y3+y4 is approximately equal to 360°; within the range of a vertical distance from the center line A of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) (i.e., between the second reference line C and the third reference line D), the black matrix 104a includes at least four fold angles: z1z2, z3 and z4, wherein z1 is approximately equal to z2, and z3+z4 is approximately equal to 360°.

[0133] Exemplarily, x1 is approximately equal to 135°, and x2 is approximately equal to 225°. Exemplarily, y1 is approximately equal to 135°, and y3 is approximately equal to 225°.

[0134] In another exemplary embodiment, within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three angles: x1, x2, and x3, where x1, x2, and x3 are approximately equal. In this embodiment, by making some angles of the black matrix 104a approximately equal, process implementation is facilitated.

[0135] In another exemplary embodiment, as shown in FIG10 , within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three angles: x1, x2, and x3, which are equal to n times of 45 degrees, where n = 3 or 5. In this embodiment, by making some angles of the black matrix 104a integer multiples of 45 degrees, process implementation is facilitated.

[0136] In an exemplary embodiment, FIG12 is a schematic cross-sectional view of the aa' region in FIG11 . As shown in FIG11 and FIG12 , the display substrate includes a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 (including a pixel defining layer, an organic light-emitting layer, an anode, and a cathode, etc.) disposed on the driving circuit layer 102, and a color filter structure layer 104 disposed on the light-emitting structure layer 103. The color filter structure layer 104 includes a black matrix 104a, and the black matrix 104a includes at least one first sub-side 1041. The driving circuit layer 102 includes at least one first signal line 1021. The first signal line 1021 has a second width l2 along the first direction, and the first sub-side 1041 has a first width l1 along the first direction. The orthographic projection of the first signal line 1021 on the substrate and the orthographic projection of the first sub-side 1041 on the substrate have a first overlap, and the first overlap has a third width l3 along the first direction.

[0137] The above widths satisfy the following relationship:

[0138] 10*l1≤L≤10*l2.

[0139] 2*k<L≤3*k.

[0140] Exemplarily, L=220 μm, l1=12-20 μm, k is approximately equal to 74 μm, l3 is approximately equal to 8 μm, and l2 is approximately equal to 32 μm.

[0141] In another exemplary embodiment, 6*l2<L<7*l2.

[0142] In another exemplary embodiment, 20*l3<L<35*l3.

[0143] In another exemplary embodiment, 3.5*l3<l2≤4*l3.

[0144] In an exemplary embodiment, the first signal line 1021 has a fold line structure, the black matrix has multiple sub-sides, and the number of fold corners of the first signal line in any sub-pixel area is less than the number of fold corners of at least one sub-side of the black matrix, and greater than the number of fold corners of at least one other sub-side of the black matrix.

[0145] As shown in Figures 6 and 11, the first signal line 1021 has a fold line structure, the black matrix has sub-side I, sub-side II, sub-side III and sub-side IV, and the number of fold corners of the first signal line in any sub-pixel area is less than the number of fold corners of at least one sub-side of the black matrix (such as sub-side II and sub-side IV), and is greater than the number of fold corners of at least one other sub-side of the black matrix (such as sub-side I and sub-side III).

[0146] In an exemplary embodiment, as shown in FIG12 , in the third direction (ie, a direction perpendicular to and away from the substrate), the first sub-side 1041 has a first thickness l4 , where 0.9 μm<l4<1.2 μm.

[0147] In one exemplary embodiment, as shown in FIG13 , the color filter structure layer 104 includes a ring-shaped black matrix 104a and a color filter 104b located within an opening, or second opening, of the black matrix 104a. The orthographic projection of the color filter 104b on the substrate at least partially covers the orthographic projection of the first opening K1 of the pixel defining layer 103b on the substrate.

[0148] In one exemplary embodiment, as shown in FIG13 , the sub-pixel region includes a pixel-defining layer 103b and a color filter structure layer 104 disposed on the pixel-defining layer 103b. The color filter structure layer 104 includes a black matrix 104a and a discrete color filter 104b. The black matrix 104a includes at least one first sub-side 1041. In the third direction, the color filter 104b has a maximum thickness greater than the maximum thickness of the first sub-side 1041 of the black matrix, and the color filter 104b at least partially covers the first sub-side 1041 of the black matrix.

[0149] In one exemplary embodiment, as shown in FIG13 , the edge of the black matrix 104a near the color filter 104b has a stepped structure. Exemplarily, the stepped structure is a single-step structure, i.e., includes only one stepped surface. Because the edge of the black matrix 104a near the color filter 104b has a stepped structure, the color filter 104b can be tightly attached to the edge of the black matrix 104a near the color filter 104b.

[0150] In an exemplary embodiment, as shown in FIG14 , the color filter 104b may have a first sub-portion 10421 and a second sub-portion 10422. The first sub-portion 10421 is connected to the first sub-side 1041 of the black matrix. The orthographic projection of the second sub-portion 10422 on the substrate covers the orthographic projection of the first sub-portion 10421 on the substrate. In other words, the second sub-portion 10422 may have a protruding structure on a plane parallel to the substrate relative to the first sub-portion 10421. In this embodiment, by setting the orthographic projection of the second sub-portion 10422 on the substrate to cover the orthographic projection of the first sub-portion 10421 on the substrate, the light purity of the display substrate is improved.

[0151] In an exemplary embodiment, as shown in FIG15 , the first signal line 1021 also has a zigzag shape with angles. Within any sub-pixel region, the number of angles of the first signal line 1021 is less than the number of angles of the first sub-side of the black matrix. Exemplarily, the number of angles of the first signal line 1021 is less than the number of angles of the first sub-side (or second sub-side) of the black matrix, and greater than the number of angles of the third sub-side (or fourth sub-side), which facilitates process implementation.

[0152] In an exemplary embodiment, the color filter 104 b covers the folded line structure of the first signal line 1021 .

[0153] In an exemplary embodiment, as shown in FIG15 , the orthographic projection of the first signal line 1021 on the substrate and the orthographic projection of the first sub-side 1041 of the black matrix 104a on the substrate form a first overlap 202, and the first overlap 202 is covered by the color filter 104b. Because the first signal line 1021 is metallic and has a high reflectivity, the first overlap 202 and the small width l3 of the first overlap, combined with FIG14 , ensure that the sub-color filter covers the first signal line 1021, thereby reducing reflections and improving light purity.

[0154] In an exemplary embodiment, the first signal line 1021 has a fold line structure, the black matrix has multiple sub-sides (sub-side I, sub-side II, sub-side III, sub-side IV), and the number of fold corners of the first signal line 1021 in any sub-pixel area is less than the number of fold corners of at least one sub-side of the black matrix (exemplarily, sub-side II or sub-side IV), and greater than the number of fold corners of at least one other sub-side of the black matrix (exemplarily, sub-side I or sub-side III).

[0155] In an exemplary embodiment, as shown in FIG16 , the first sub-side 1041 of the black matrix 104a has a plurality of third sub-segments. The plurality of third sub-segments are neither parallel nor perpendicular to the first direction and the second direction. Furthermore, the plurality of third sub-segments are disposed separately from one another and are separated from one another by other sub-segments that are either parallel to the first direction or parallel to the second direction.

[0156] For example, as shown in FIG16 , the first sub-side 1041 of the black matrix 104a has four third sub-segments 10411 to 10414. The four third sub-segments 10411 to 10414 are neither parallel nor perpendicular to the first direction and the second direction. Furthermore, the four third sub-segments 10411 to 10414 are disposed separately from one another and are separated by other sub-segments parallel to the second direction.

[0157] In an exemplary embodiment, as shown in FIG17 , the black matrix 104a has a second sub-side 1042 disposed opposite the first sub-side 1041. As shown in FIG17 , the sub-pixel 10 ′ has another side, namely, a second side II, disposed opposite the fourth side IV, and the black matrix has a second sub-side 1042.

[0158] In Figure 17 , a first reference line B and a fifth reference line B' may be set at a distance k from the center line A. The sub-pixel region may further include a second reference line C, a third reference line D, a fourth reference line E, a sixth reference line C', a seventh reference line D', and an eighth reference line E'. The fifth reference line B', the sixth reference line C', the seventh reference line D', and the eighth reference line E' are symmetrical structures of the first reference line B, the second reference line C, the third reference line D, and the fourth reference line E, respectively, about the center line A. That is, the center line A and the fifth reference line B' are also at a distance k, and the distances between the fifth reference line B' and the sixth reference line C', the sixth reference line C' and the seventh reference line D', and the seventh reference line D' and the eighth reference line E' are also n. The second sub-side 1042 of the black matrix 104a also has a fold line structure with a fold angle.

[0159] In an exemplary embodiment, the number x' of folded corners between the center line A and the fifth reference line B', the number y' of folded corners between the fifth reference line B' and the sixth reference line C', and the number z' of folded corners between the sixth reference line C' and the seventh reference line D' satisfy the following conditions: x=x', y≠y', z≠z'.

[0160] Because x is relatively small, x' is also relatively small, meaning the fold line structure near the subpixel centerline A has fewer fold angles. y≠y', z≠z', meaning the first sub-side 1041 and the second sub-side 1042 are asymmetrically arranged. This achieves a better display effect, meaning less interference and diffraction structures.

[0161] In an exemplary embodiment, within a sub-pixel area, the number of corners x' of the second sub-side 1042 between the center line A and the fifth reference line B', the number of corners y' between the fifth reference line B' and the sixth reference line C', and the number of corners z' between the sixth reference line C' and the seventh reference line D' satisfy the following condition: x'≤y'≤z'.

[0162] In an exemplary embodiment, the number of corners of the second sub-side 1042 between the center line A and the fifth reference line B' is ≥2; the number of corners of the second sub-side 1042 between the fifth reference line B' and the sixth reference line C' is ≥3; the number of corners of the second sub-side 1042 between the sixth reference line C' and the seventh reference line D' is ≥3.

[0163] Exemplarily, as shown in FIG18 , within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the fifth reference line B'), the second sub-side 1042 includes a number of folded corners x'=2. Within a range where the vertical distance from the center line A is between k and (k+(L / 2-k) / 3) (i.e., between the fifth reference line B' and the sixth reference line C'), the second sub-side 1042 includes a number of folded corners y'=3; within a range where the vertical distance from the center line A is between (k+(L / 2-k) / 3) and (k+2(L / 2-k) / 3) (i.e., between the sixth reference line C' and the seventh reference line D'), the second sub-side 1042 includes a number of folded corners z'=6.

[0164] In an exemplary embodiment, the second sub-side 1042 has at least two approximately equal folding angles between the center line A and the fifth reference line B'; the second sub-side 1042 has at least two approximately equal folding angles between the fifth reference line B' and the sixth reference line C'; and the second sub-side 1042 has at least two approximately equal folding angles between the sixth reference line C' and the seventh reference line D'.

[0165] Exemplarily, the second sub-side 1042 has two fold angles x2' and x3' between the center line A and the fifth reference line B', and x2' and x3' are approximately equal. The second sub-side 1042 has three fold angles y1', y2' and y3' between the fifth reference line B' and the sixth reference line C', wherein y2' and y3' are approximately equal. The second sub-side 1042 has six fold angles z1', z2', z3', z4', z5' and z6' between the sixth reference line C' and the seventh reference line D', wherein z3' and z4' are approximately equal.

[0166] In an exemplary embodiment, the second sub-side 1042 has at least one fourth fold angle between the center line A and the fifth reference line B'; the second sub-side 1042 has at least one fifth fold angle between the fifth reference line B' and the sixth reference line C'; the second sub-side 1042 has at least one sixth fold angle between the sixth reference line C' and the seventh reference line D', and the angles of the fourth fold angle, the fifth fold angle and the sixth fold angle are approximately equal.

[0167] Exemplarily, the fold angle x2' between the center line A and the fifth reference line B', the fold angle y2' between the fifth reference line B' and the sixth reference line C', and the fold angle z3' between the sixth reference line C' and the seventh reference line D' of the second sub-side 1042 satisfy: x2', y2' and z3' are approximately equal.

[0168] In an exemplary embodiment, as shown in Figure 19, the black matrix 104a includes a third sub-side and a fourth sub-side, the third sub-side connects the first sub-side and the second sub-side, the fourth sub-side connects the first sub-side and the second sub-side, and the first sub-side, the third sub-side, the fourth sub-side and the second sub-side are connected end to end to form a second opening.

[0169] In an exemplary embodiment, as shown in FIG. 19 , the third sub-side is parallel to the first direction, and the fourth sub-side is parallel to the first direction.

[0170] In an exemplary embodiment, as shown in Figure 19, a pixel unit in a display substrate may include a first sub-pixel 301, a second sub-pixel 302, and a third sub-pixel 303. Any two adjacent sub-pixels have different black matrix sides. In this way, a better display effect can be achieved, that is, less interference and diffraction structure. Exemplarily, the first sub-pixel 301, the second sub-pixel 302, and the third sub-pixel 303 can be a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, which is not limited in this disclosure.

[0171] In another exemplary embodiment, as shown in FIG20 , a pixel unit in a display substrate may include a first sub-pixel 301, a second sub-pixel 302, a third sub-pixel 303, and a fourth sub-pixel 304. In this case, the sub-sides of the black matrix in each sub-pixel may be different, thereby achieving a better display effect, that is, reducing interference and diffraction structures.

[0172] In an exemplary embodiment, the pixel arrangement may be in accordance with the layout shown in FIG20 , where two sub-pixels are arranged along a first direction and another two sub-pixels are arranged along a second direction. Of course, the sub-pixels may be arranged in other pixel structures.

[0173] Exemplarily, the first sub-pixel 301 , the second sub-pixel 302 , the third sub-pixel 303 and the fourth sub-pixel 304 may be red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels and white (W) sub-pixels, which is not limited in the present disclosure.

[0174] In an exemplary embodiment, the number of corners of the first sub-side of the black matrix in the green (G) sub-pixel is less than the number of corners of the first sub-side of the black matrix in the blue (B) sub-pixel.

[0175] In an exemplary embodiment, the areas of the second openings formed by the black matrices of different sub-pixels may be different, and the areas of the second openings formed by the black matrices of each sub-pixel may be set according to brightness requirements. For example, the area of ​​the second opening formed by the green (G) sub-pixel is the smallest, and the area of ​​the second opening formed by the white (W) sub-pixel is the largest.

[0176] In an exemplary embodiment, when the sub-pixel includes a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel, the white (W) sub-pixel may not have a color filter.

[0177] For example, as shown in FIG21 , the green (G) sub-pixel, the red (R) sub-pixel, and the blue (B) sub-pixel all include color filters, and the white (W) sub-pixel may not have a color filter.

[0178] In an exemplary embodiment, as shown in FIG22 , the display substrate may further include an encapsulation layer 105 disposed on a side of the color filter structure layer away from the light-emitting structure layer 103. The encapsulation layer 105 may include a first encapsulation layer and a second encapsulation layer stacked together. The first encapsulation layer may be made of an organic material, and the second encapsulation layer may be made of an inorganic material, thereby preventing external moisture from entering the light-emitting structure layer and the color filter structure layer.

[0179] Since the white (W) sub-pixel does not need a color filter, the first encapsulation layer can cover and fill the white (W) sub-pixel. In other words, the filling structure on the white (W) sub-pixel is made of the same material as the first encapsulation layer, forming an integrated structure.

[0180] In an exemplary embodiment, as shown in FIG. 23 , the display substrate may further include a blank structure 305 , and the orthographic projection of the blank structure 305 on the substrate does not overlap with the orthographic projection of the driving circuit on the substrate, which helps to improve transmittance.

[0181] In an exemplary embodiment, the blank structure may occupy ≥45% of the area of ​​the display region. For example, the blank structure may occupy 46% of the area of ​​the display region.

[0182] In one exemplary embodiment, the blank structures have a width l5 in the first direction, where width is defined as the distance between two substantially parallel side edges along the second direction. Here, the width l5 can be equal to or substantially equal to the total length of the fold line structures of the black matrix sub-side edges 1041 in the first direction. This allows the blank structures 305 to be arranged more uniformly on the display substrate, achieving a better display effect.

[0183] In one exemplary embodiment, the blank structure has a first sub-edge adjacent to the first sub-side of the white sub-pixel region and the first sub-side of the red sub-pixel region, and the shape of the first sub-edge is conformal to the shapes of the first sub-side of the white sub-pixel region and the first sub-side of the red sub-pixel region. In the disclosed embodiments, "conformal" between A and B means that the shapes of the adjacent edges of A and B are completely consistent, or that A and B share a common edge as the edge between A and B.

[0184] In one exemplary embodiment, the blank structure 305 is not necessarily rectangular; it can also be the area between two sub-side edges of the black matrix 104a along the first direction. In other words, the side edges of the blank structure 305 also have a fold line structure and a fold angle. This can further eliminate regular lines, reduce diffraction and interference effects, and improve display quality.

[0185] In one exemplary embodiment, as shown in FIG24 , the subpixel may include a first power line VDD, which continuously provides a high voltage. In conjunction with FIG15 , the aforementioned first signal line 1021 may be the first power line VDD. In this embodiment, the color filter between the black matrix completely covers the first power line VDD, reducing reflectivity and improving light purity.

[0186] In one exemplary embodiment, as shown in FIG24 , the subpixel may include a second power line VSS, which continuously provides a low voltage. In conjunction with FIG15 , the aforementioned first signal line 1021 may serve as the second power line VSS. In this embodiment, the color filter between the black matrix completely covers the first power line VDD, reducing reflectivity and improving light purity.

[0187] In an exemplary embodiment, as shown in Figure 24, a sub-pixel may include a repair structure 401. The repair structure 401 may be electrically connected to a plurality of pixel electrodes.

[0188] In one exemplary embodiment, a repair structure 401 can be electrically connected to the first electrodes of two sub-pixels. Here, the light-emitting layer can include an electroluminescent layer between the first and second electrodes. Exemplarily, the first electrode is an anode and the second electrode is a cathode. The anodes of adjacent sub-pixels can be separate block structures, while the cathodes of adjacent sub-pixels can be solid-surface structures.

[0189] In an exemplary embodiment, the plurality of sub-pixel regions include a red sub-pixel region and a blue sub-pixel region, and the repair structures of the red sub-pixel region and the blue sub-pixel region are at least partially symmetrical and at least partially asymmetrical.

[0190] In an exemplary embodiment, the orthographic projection of the color filter on the substrate can cover the orthographic projection of the corresponding driving circuit layer on the substrate, which can further reduce reflection, improve light extraction efficiency, and enhance display effects.

[0191] In an exemplary embodiment, the light emitting structure layer further includes an anode, the first opening at least partially exposes the anode, and at least one sub-pixel region includes a plurality of discretely arranged sub-anode blocks.

[0192] In one exemplary embodiment, as shown in FIG25 , the anode of the display substrate includes at least two discrete sub-anode blocks. This means the anode is a discrete structure, and the edge of at least one sub-anode may include a folded line structure. This can reduce diffraction effects and improve display quality.

[0193] In an exemplary embodiment, as shown in FIG25 , taking any two adjacent sub-pixels 301 and 302 as an example, each sub-pixel can include at least two discrete sub-anodes. For example, sub-pixel 301 includes a separate first sub-anode block 5011 and a separate second sub-anode block 5012, both of which have a zigzag structure to enhance display quality. Sub-pixel 302 includes a separate third sub-anode block 5021 and a separate fourth sub-anode block 5022, both of which have a zigzag structure to enhance display quality.

[0194] In an exemplary embodiment, the multiple sub-anode blocks have different morphologies. In this embodiment, the multiple sub-anode blocks have different morphologies, which means that the orthographic projections of the multiple sub-anode blocks on the substrate have different shapes, or that the orthographic projections of the multiple sub-anode blocks on the substrate have the same shape but are stacked in different directions.

[0195] For example, as shown in FIG25 , the shape of the orthographic projection of the first sub-anode block 5011 on the substrate may be different from the shape of the orthographic projection of the second sub-anode block 5012 on the substrate.

[0196] In an exemplary embodiment, the orthographic projections of the sub-anode blocks in adjacent sub-pixels on the substrate may have different shapes. For example, as shown in FIG25 , the orthographic projections of the plurality of sub-anode blocks 5011, 5012, 5021, and 5022 on the substrate all have different shapes. The different orthographic projection shapes described in the disclosed embodiment mean that the orthographic projection of one sub-anode block on the substrate cannot overlap with the orthographic projection of another sub-anode block on the substrate after translation.

[0197] In an exemplary embodiment, multiple sub-anode blocks in the same sub-pixel are respectively connected to the connection structure. For example, as shown in FIG25 , the first sub-anode block 5011 and the second sub-anode block 5012 are respectively electrically connected to the first connection structure 601. The third sub-anode block 5021 and the fourth sub-anode block 5022 are respectively electrically connected to the second connection structure 602.

[0198] As shown in FIG26 , the first connection structure 601 may include: a first connection electrode CE1 extending from a first end of the first sub-anode block 5011 in a first direction; a second connection electrode CE2 extending from a first end of the second sub-anode block 5012 in the first direction; a third connection electrode CE3 electrically connected to a drive transistor (for example, the second transistor T2 in FIG8 ) and extending in the first direction; and a fourth connection electrode CE4 having a first end in contact with the first connection electrode CE1 and a second end in contact with the second connection electrode CE2 , the fourth connection electrode CE4 being in contact with the third connection electrode CE3 between the first and second ends. In this case, the fourth connection electrode CE4 is arranged in a different layer from at least one of the first to third connection electrodes CE1 to CE3 and is in contact with the first to third connection electrodes CE1 to CE3.

[0199] The first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 are spaced apart from each other and arranged in parallel. The first connection electrode CE1 may be formed integrally with the first sub-anode block 5011, and the second connection electrode CE2 may be formed integrally with the second sub-anode block 5012. The third connection electrode CE3 is spaced apart from the first sub-anode block 5011 and the second sub-anode block 5012 and arranged between the first sub-anode block 5011 and the second sub-anode block 5012.

[0200] The third connection electrode CE3 may be made of the same material as that constituting at least one of the first sub-anode block 5011, the second sub-anode block 5012, the first connection electrode CE1, and the second connection electrode CE2, or the third connection electrode CE3 may be arranged in the same layer as at least one of the first sub-anode block 5011, the second sub-anode block 5012, the first connection electrode CE1, and the second connection electrode CE2. The third connection electrode CE3 connected to the driving transistor may be electrically connected to the first connection electrode CE1 and the second connection electrode CE2 to drive the first sub-light emitting unit corresponding to the first sub-anode block 5011 and the second sub-light emitting unit corresponding to the second sub-anode block 5012 through a single driving transistor.

[0201] The connection electrode CE4 may be arranged in a second direction different from or perpendicular to the first direction in which the first to third connection electrodes CE1 to CE3 are arranged, and the connection electrode CE4 electrically connects the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 to each other. The fourth connection electrode CE4 is arranged in a layer different from at least one of the first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3. The fourth connection electrode CE4 connects the first connection electrode CE1 to the third connection electrode CE3 via a bridge, or connects the second connection electrode CE2 to the third connection electrode CE3 via a bridge.

[0202] The fourth connection electrode CE4 may be arranged in the same layer as the active layer constituting the driving thin film transistor. The first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 contact the fourth connection electrode CE4 through via holes extending through the insulating layer disposed on the fourth connection electrode CE4. The fourth connection electrode CE4 may be made of the same material as the active layer constituting the driving thin film transistor.

[0203] 8 , a driving transistor and at least two switching transistors may be required to drive a sub-pixel. A gate electrode of one switching transistor (the first transistor T1 in FIG8 ) is connected to the first scan signal line Sn to provide a signal of the data signal line Dn connected to the source / drain electrodes of the switching transistor to the gate electrode of the driving transistor (the second transistor T2 in FIG8 ).

[0204] The driving transistor applies a voltage VDD connected to the source / drain electrode on one side of the driving transistor to the first sub-anode block 5011 and the second sub-anode block 5012 in response to a signal from the gate electrode. At this time, the first connection structure 601 is electrically connected between the source / drain electrode on the other side of the driving transistor and the first sub-anode block 5011 and the second sub-anode block 5012, so that the voltage or current of the source / drain electrode on the other side of the driving transistor is applied to the first sub-anode block 5011 and the second sub-anode block 5012 through the first connection structure 601. Another switching transistor (the third transistor T3 in FIG8 ) is connected to the source / drain electrode on the other side of the driving transistor, the gate electrode of the switching transistor is connected to the second scan signal line Sn, and the reference voltage VRef is connected to one side of the source / drain electrode of the switching transistor.

[0205] If a dark spot or a bright spot appears in any sub-pixel of the display panel, a portion of the fourth connection electrode CE4 of the first connection structure 601 can be laser cut, so that the first sub-anode block 5011 or the second sub-anode block 5012 from a sub-pixel can be electrically connected to the driving transistor.

[0206] For example, laser cutting may be performed on the fourth connection electrode CE4 between the second connection electrode CE2 and the third connection electrode CE3, thereby electrically disconnecting the second sub-anode block 5012 connected to the second connection electrode CE2 from the driving transistor, and causing the second light emitting unit corresponding to the second sub-anode block 5012 to become a floating state. At this time, the first sub-anode block 5011 may be electrically connected to the driving transistor through the third connection electrode CE3, and thus may drive the first sub-anode block 5011, wherein the third connection electrode CE3 is electrically connected to the driving transistor through the first connection electrode CE1 and the fourth connection electrode CE4.

[0207] That is, even if a dark spot or a bright spot appears in one sub-pixel, laser cutting may be performed with respect to the fourth link electrode CE4 to float one sub-light emitting unit, thereby enabling the sub-pixel to be normally driven.

[0208] Although it is shown that the laser cutting is performed with respect to the fourth connection electrode CE4 between the second connection electrode CE2 and the third connection electrode CE3 , the laser cutting may also be formed with respect to the fourth connection electrode CE4 between the first connection electrode CE1 and the third connection electrode CE3 .

[0209] If dark spots or bright spots appear in the first sub-light-emitting cell region corresponding to the first sub-anode block 5011, laser cutting may be performed on the fourth connection electrode CE4 between the first connection electrode CE1 and the third connection electrode CE3, thereby electrically disconnecting the first sub-anode block 5011 connected to the first connection electrode CE1 from the drive transistor, and causing the first sub-light-emitting cell corresponding to the first sub-anode block 5011 to become a floating state. At this time, the second sub-anode block 5012 may be electrically connected to the drive transistor through the third connection electrode CE3, which is electrically connected to the drive transistor through the second connection electrode CE2 and the fourth connection electrode CE4, and thus may drive the second sub-anode block 5012.

[0210] Even if a dark spot or a bright spot occurs in one sub-pixel, laser cutting may be performed with respect to the fourth link electrode CE4 to drive the second sub-light emitting unit, thereby making it possible to normally drive the sub-pixel.

[0211] If a dark spot or a bright spot appears in one sub-pixel, the first connection electrode CE1 and the fourth connection electrode CE4 arranged on a different layer from the third connection electrode CE3 can be separated from each other between the first connection electrode CE1 and the third connection electrode CE3, and the second connection electrode CE2 and the fourth connection electrode CE4 arranged on a different layer from the third connection electrode CE3 can be separated from each other between the second connection electrode CE2 and the third connection electrode CE3.

[0212] If a dark spot or a bright spot does not occur in one sub-pixel, the fourth link electrode CE4 electrically connects the first link electrode CE1, the second link electrode CE2, and the third link electrode CE3 to each other as described above.

[0213] In an exemplary embodiment, when a fault such as a short circuit occurs in the sub-pixel driving circuit corresponding to a sub-pixel, the sub-pixel can be electrically connected to the adjacent sub-pixel driving circuit by ablating the repair structure and the connection structure, thereby enabling the sub-pixel to be illuminated. For example, when a fault such as a short circuit occurs in the sub-pixel driving circuit corresponding to sub-pixel 301, the sub-pixel can be electrically connected to the first repair structure 4011 and the first connection structure 601 by ablating the repair structure, thereby enabling the sub-pixel 301 to be electrically connected to the adjacent sub-pixel driving circuit, thereby enabling the sub-pixel to be illuminated.

[0214] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0215] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0216] (1) First, a driving circuit layer 102 pattern is prepared on a substrate 101. The driving circuit layer 102 includes a plurality of gate lines and a plurality of data signal lines. The plurality of gate lines and the plurality of data signal lines intersect to define a plurality of pixel units arranged in a matrix. Each pixel unit includes at least three sub-pixels, and each sub-pixel includes a thin film transistor (TFT). In this embodiment, a pixel unit includes three sub-pixels, namely a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, this embodiment is also applicable to the case where a pixel unit includes four sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W).

[0217] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking a stacked structure as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer again, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate 101.

[0218] In an exemplary embodiment, the preparation process of the driving circuit layer 102 may include:

[0219] A first insulating film and an active layer film are sequentially deposited on the substrate 101, and the active layer film is patterned through a patterning process to form a first insulating layer covering the entire substrate 101, and an active layer pattern arranged on the first insulating layer, wherein the active layer pattern includes at least a first active layer.

[0220] Subsequently, a second insulating film and a first metal film are deposited in sequence, and the first metal film is patterned through a patterning process to form a second insulating layer covering the active layer pattern, and a first gate metal layer pattern arranged on the second insulating layer. The first gate metal layer pattern includes at least a first gate electrode, a first capacitor electrode, multiple gate lines and multiple gate leads.

[0221] Subsequently, a third insulating film and a second metal film are deposited in sequence, and the second metal film is patterned through a patterning process to form a third insulating layer covering the first gate metal layer, and a second gate metal layer pattern arranged on the third insulating layer, the second gate metal layer pattern includes at least a second capacitor electrode and a second gate lead, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.

[0222] Subsequently, a fourth insulating film is deposited and patterned through a patterning process to form a fourth insulating layer pattern covering the second gate metal layer. A plurality of first via holes are opened on the fourth insulating layer, and the positions of the plurality of first via holes correspond to the two end positions of the first active layer respectively. The fourth insulating layer, the third insulating layer and the second insulating layer in the plurality of first via holes are etched away to expose the surfaces of the first active layer respectively.

[0223] Subsequently, a third metal film is deposited and patterned through a patterning process to form a source / drain metal layer pattern on the fourth insulating layer. The source / drain metal layer is formed in the display area and includes at least a first source electrode, a first drain electrode, a low voltage (VSS) line, multiple data signal lines, and multiple data lead patterns. The first source electrode and the first drain electrode are each connected to the first active layer through a first via. In one exemplary embodiment, the source / drain metal layer may further include any one or more of a power supply line (VDD), a compensation line, and an auxiliary cathode, depending on actual needs. The source / drain metal layer is also referred to as a first source / drain metal layer (SD1).

[0224] Subsequently, a fifth insulating film is deposited to form a fifth insulating layer pattern covering the source / drain metal layer.

[0225] A first flat film is coated on the substrate 101 on which the aforementioned pattern is formed to form a first flat (PLN) layer covering the entire substrate 101. A second via is formed on the first flat layer through a patterning process. The second via is formed in the display area. The first flat layer and the fifth insulating layer in the second via are etched away to expose the surface of the first drain electrode of the first transistor 102a.

[0226] At this point, the pattern of the driving structure layer 102 is completed on the substrate 101. The first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first transistor 102a. The first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102b. The multiple gate leads and data leads constitute the drive leads of the gate driver on array (GOA) of the array substrate. In one exemplary embodiment, the first transistor 102a can be a driving transistor in a pixel driving circuit, and the driving transistor can be a thin film transistor (TFT).

[0227] (2) A light emitting structure layer 103 pattern is prepared on the substrate 101 on which the aforementioned pattern is formed. In an exemplary embodiment, the preparation process of the light emitting structure layer 103 may include:

[0228] Depositing a transparent conductive film on the substrate 101 having the aforementioned pattern, and patterning the transparent conductive film through a patterning process to form an anode 103a pattern. The anode 103a is formed in the display area and connected to the first drain electrode of the first transistor 102a through a second via hole;

[0229] A pixel definition film is coated on the substrate 101 having the aforementioned pattern formed thereon, and a pixel definition layer (PDL) 103b pattern is formed through masking, exposure, and development processes. The pixel definition layer 103b has pixel openings, and the pixel definition film in the pixel openings is developed away to expose the surface of the anode 103a.

[0230] Coating an organic material thin film on the substrate with the aforementioned pattern formed thereon, and forming a plurality of spacer (PS) patterns through masking, exposure, and development processes;

[0231] An organic light-emitting layer 103c and a cathode 103d are sequentially formed on the patterned substrate. The organic light-emitting layer 103c may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The organic light-emitting layer 103c is formed in the display area to connect the organic light-emitting layer 103c to the anode 103a. Since the anode 103a is connected to the drain electrode of the first transistor 102a, light emission from the organic light-emitting layer 103c is controlled. The cathode 103d is connected to the organic light-emitting layer 103c.

[0232] (4) A second flat film is coated on the substrate 101 on which the aforementioned pattern is formed, and a second flat layer pattern is formed on the light emitting structure layer 103 through masking, exposure, and development processes.

[0233] (5) A color filter structure layer 104 pattern is prepared on the substrate 101 on which the aforementioned pattern is formed. In an exemplary embodiment, the preparation process of the color filter structure layer 104 may include:

[0234] First, a polymer photoresist layer mixed with a black matrix material is coated on the second flat layer, and after exposure and development, a pattern of the black matrix 104a is formed. Then, a polymer photoresist layer mixed with a red pigment is coated on the second flat layer, and after exposure and development, a pattern of the red area is formed. The same method and steps are used to sequentially form patterns of the green area and the blue area, and finally a color film pattern of the three primary colors of red, green, and blue arranged according to a certain rule is formed.

[0235] (4) An encapsulation layer 105 is formed on the substrate 101 on which the aforementioned pattern is formed. The encapsulation layer 105 is formed in the display area and adopts a stacked structure of organic material / inorganic material, as shown in FIG. 27 and FIG. 28 .

[0236] In an exemplary embodiment, when preparing a flexible display substrate, the preparation process of the display substrate may include processes such as peeling off a glass carrier, attaching a back film, and cutting, which are not limited in the present disclosure.

[0237] The structure of the display substrate and its preparation process of the exemplary embodiment of the present disclosure show that the exemplary embodiment of the present disclosure reduces grating effects such as diffraction effect, interference effect, and scattered color separation by setting the black matrix with a folded line structure, thereby improving the display effect; the use of the black matrix and color filter reduces reflectivity and improves light purity; and the absence of polarizers reduces costs, reduces the thickness of the display panel, and improves the bendability of the display panel. The preparation method of the display substrate of the exemplary embodiment of the present disclosure has good process compatibility, simple process implementation, easy implementation, high production efficiency, low production cost, and high yield rate.

[0238] The structure and preparation process shown in the exemplary embodiments of the present disclosure are merely exemplary. In the exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the transistor in the driving circuit layer can be a top-gate structure, or a bottom-gate structure, or a single-gate structure, or a double-gate structure. For another example, other film layer structures, electrode structures, or lead structures can also be provided in the driving circuit layer and the light-emitting structure layer. For another example, the substrate can be a glass substrate, which is not specifically limited in the present disclosure.

[0239] The present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the method may include:

[0240] forming a driving circuit layer on the substrate;

[0241] forming a light-emitting structure layer on a side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel region and overlapping with the first opening of the pixel defining layer;

[0242] A color film structure layer is formed on a side of the light-emitting structure layer away from the substrate, the color film structure layer includes a color film and a black matrix, the black matrix has a second opening that at least partially exposes the first opening, the color film is arranged in the second opening, the black matrix includes a first sub-side, and the first sub-side has a fold line structure.

[0243] There are a few points to note:

[0244] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0245] In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to form new embodiments.

[0246] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: substrate; a driving circuit layer disposed on the substrate; a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light-emitting structure layer comprising a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel region and overlapping with the first opening of the pixel defining layer; And a color film structure layer is arranged on the side of the light-emitting structure layer away from the substrate, the color film structure layer includes a color film and a black matrix, the black matrix has a second opening that at least partially exposes the first opening, the color film is arranged in the second opening, the black matrix includes a first sub-side, and the first sub-side has a broken line structure.

2. The display substrate according to claim 1, wherein The first sub-side has a plurality of folded corners, and the farther away from the center line of the sub-pixel area the region is, the more folded corners the first sub-side has.

3. The display substrate according to claim 1, wherein The sub-pixel area includes a center line, a first reference line, a second reference line, a third reference line, and a fourth reference line in sequence along the first direction, wherein the fourth reference line coincides with the farthest boundary of the first sub-side away from the center line, wherein: The distance between the first reference line and the center line of the sub-pixel area is k, the distance between the first reference line and the second reference line is n1, the distance between the second reference line and the third reference line is n2, and the distance between the third reference line and the fourth reference line is n3; k+n1+n2+n3=L / 2, where L is the length of the sub-pixel area along the first direction; The number of corners x between the center line and the first reference line, the number of corners y between the first reference line and the second reference line, and the number of corners z between the second reference line and the third reference line of the first sub-side satisfy the following condition: x≤y≤z.

4. The display substrate according to claim 3, wherein: n1=n2=n3.

5. The display substrate according to claim 3, wherein: The number x of the corners of the first sub-side between the center line and the first reference line is ≥3; The number of corners y of the first sub-side between the first reference line and the second reference line is ≥3; The number of corners z of the first sub-side between the second reference line and the third reference line is ≥3. The display substrate according to claim 3 , wherein: The first sub-side has at least two substantially equal fold angles between the center line and the first reference line; The first sub-side has at least two substantially equal fold angles between the first reference line and the second reference line; The first sub-side has at least two substantially equal fold angles between the second reference line and the third reference line.

7. The display substrate according to claim 3, wherein: The first sub-side has at least one first fold angle between the center line and the first reference line, the first sub-side has at least one second fold angle between the first reference line and the second reference line, and the first sub-side has at least one third fold angle between the second reference line and the third reference line, and the angles of the first fold angle, the second fold angle and the third fold angle are approximately equal.

8. The display substrate according to claim 3, wherein: The number of folded corners x of the first sub-side between the center line and the first reference line is ≥3, the number of folded corners y of the first sub-side between the first reference line and the second reference line is ≥4, and the number of folded corners z of the first sub-side between the second reference line and the third reference line is ≥5.

9. The display substrate according to claim 3, wherein: The first sub-side includes at least three angles between the center line and the first reference line: x1, x2, and x3, wherein x2 and x3 are substantially equal, and x1+x2 is substantially equal to 360 degrees; The first sub-side includes at least four fold angles between the first reference line and the second reference line: y1, y2, y3, and y4, wherein y1 and y2 are substantially equal, and y3+y4 is substantially equal to 360 degrees; The first sub-side includes at least four corners between the second reference line and the third reference line: z1, z2, z3 and z4, wherein z1 is substantially equal to z2, and z3+z4 is substantially equal to 360 degrees.

10. The display substrate according to claim 3, wherein: The first sub-side has at least three fold angles with substantially equal angles between the center line and the first reference line.

11. The display substrate according to claim 10, wherein: An angle of the at least three folded corners of the first sub-side between the center line and the first reference line is equal to n times of 45 degrees, where n=3 or 5.

12. The display substrate according to claim 1, wherein The first sub-side has a first width along the first direction; the driving circuit layer includes at least one first signal line, the first signal line has a second width along the first direction, the orthographic projection of the first signal line on the substrate and the orthographic projection of the first sub-side on the substrate have a first overlap, and the first overlap has a third width along the first direction.

13. The display substrate according to claim 12, wherein: The orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate, and the orthographic projection of the color filter on the substrate have a first overlap.

14. The display substrate according to claim 12, wherein: The first signal line has a fold line structure, the black matrix has multiple sub-sides, and the number of fold corners of the first signal line in any sub-pixel area is less than the number of fold corners of at least one sub-side of the black matrix, and greater than the number of fold corners of at least one other sub-side of the black matrix.

15. The display substrate according to claim 12, wherein: The first width is l1, the second width is l2, the sub-pixel area includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel area is k, and the length of the sub-pixel area along the first direction is L, then: 10*l1≤L≤10*l2; 2*k<L≤3*k.

16. The display substrate according to claim 12, wherein: The first width is l1, the second width is l2, the third width is l3, the sub-pixel area includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel area is k, and the length of the sub-pixel area along the first direction is L, then: 6*l2<L<7*l2; 20*l3<L<35*l3; 3.5*l3<l2≤4*l3.

17. The display substrate according to claim 1, wherein The orthographic projection of the color filter on the substrate at least partially covers the orthographic projection of the first opening of the pixel defining layer on the substrate; In the third direction, the maximum thickness of the color filter is greater than the maximum thickness of the first sub-side, and the color filter at least partially covers the first sub-side. The third direction is along the base substrate toward the color filter structure layer.

18. The display substrate according to claim 1, wherein The black matrix has a second thickness l4 in a third direction, and the second thickness is between 0.9 micrometers and 1.2 micrometers. The third direction is a direction along the base substrate toward the color filter structure layer.

19. The display substrate according to claim 1, wherein The first sub-side includes a third sub-line segment that is neither parallel to the first direction nor perpendicular to the second direction, and the black matrix includes a plurality of the third sub-line segments.

20. The display substrate according to claim 19, wherein The first sub-side includes four discretely arranged third sub-line segments, and the four third sub-line segments are spaced apart from each other.

21. The display substrate according to claim 1, wherein The first sub-side has a step structure.

22. The display substrate according to claim 1, wherein The black matrix further includes a second sub-side opposite to the first sub-side, and the second sub-side has a fold line structure. The first sub-side and the second sub-side are asymmetrically arranged relative to a center line of the sub-pixel area.

23. The display substrate according to claim 22, wherein: The sub-pixel area includes, in order along the first direction, an eighth reference line, a seventh reference line, a sixth reference line, a fifth reference line, a center line, a first reference line, a second reference line, a third reference line, and a fourth reference line, wherein the fourth reference line coincides with a farthest boundary of the first sub-side away from the center line, and the eighth reference line coincides with a farthest boundary of the second sub-side away from the center line, wherein: The distance between the first reference line and the center line of the sub-pixel area is k, the distance between the fifth reference line and the center line of the sub-pixel area is k, the distance between the first reference line and the second reference line is n1, the distance between the sixth reference line and the fifth reference line is n1, the distance between the second reference line and the third reference line is n2, the distance between the seventh reference line and the sixth reference line is n2, the distance between the third reference line and the fourth reference line is n3, and the distance between the eighth reference line and the seventh reference line is n3; k+n1+n2+n3=L / 2, where L is the length of the sub-pixel area along the first direction; The number of corners x of the first sub-side between the center line and the first reference line, the number of corners y of the first sub-side between the first reference line and the second reference line, the number of corners z of the first sub-side between the second reference line and the third reference line, the number of corners x' of the second sub-side between the center line and the fifth reference line, the number of corners y' of the second sub-side between the fifth reference line and the sixth reference line, and the number of corners z' of the second sub-side between the sixth reference line and the seventh reference line satisfy the following conditions: x=x', y≠y', z≠z'.

24. The display substrate according to claim 22, wherein: The black matrix also includes a third sub-side and a fourth sub-side arranged opposite to each other, the first sub-side, the third sub-side, the second sub-side and the fourth sub-side are connected end to end, and the third sub-side and the fourth sub-side have a straight bar shape or a roughly straight bar shape.

25. The display substrate according to claim 1, wherein The sub-pixel area includes a first sub-pixel area, a second sub-pixel area and a third sub-pixel area, the first sub-pixel area includes a first light-emitting unit and a first color filter, the second sub-pixel area includes a second light-emitting unit and a second color filter, the third sub-pixel area includes a third light-emitting unit and a third color filter, the orthographic projection of the first color filter on the substrate covers the orthographic projection of the first light-emitting unit on the substrate, the orthographic projection of the second color filter on the substrate covers the orthographic projection of the second light-emitting unit on the substrate, and the orthographic projection of the third color filter on the substrate covers the orthographic projection of the third light-emitting unit on the substrate.

26. The display substrate according to claim 25, wherein: The second light-emitting unit includes two discrete sub-light-emitting units, and the second color filter includes two discrete sub-color filters, the orthographic projection of one sub-color filter on the substrate covers the orthographic projection of one sub-light-emitting unit on the substrate, and the orthographic projection of the other sub-color filter on the substrate covers the orthographic projection of the other sub-light-emitting unit on the substrate.

27. The display substrate according to claim 1, wherein: The display substrate further includes an encapsulation layer disposed on a side of the color filter structure layer away from the light-emitting structure layer, and an orthographic projection of the encapsulation layer on the base covers an orthographic projection of the color filter structure layer on the substrate.

28. The display substrate according to claim 1, wherein The sub-pixel area includes a first sub-pixel area, a second sub-pixel area, a third sub-pixel area and a fourth sub-pixel area, the first sub-pixel area includes a first light-emitting unit and a first color filter, the second sub-pixel area includes a second light-emitting unit and a second color filter, the third sub-pixel area includes a third light-emitting unit and a third color filter, the fourth sub-pixel area includes a fourth light-emitting unit and a fourth color filter, the orthographic projection of the first color filter on the substrate covers the orthographic projection of the first light-emitting unit on the substrate, the orthographic projection of the second color filter on the substrate covers the orthographic projection of the second light-emitting unit on the substrate, the orthographic projection of the third color filter on the substrate covers the orthographic projection of the third light-emitting unit on the substrate, and the orthographic projection of the fourth color filter on the substrate covers the orthographic projection of the fourth light-emitting unit on the substrate.

29. The display substrate according to claim 28, wherein: It also includes an encapsulation layer covering the color filter structure layer, the encapsulation layer covers the first color filter, the second color filter and the third color filter, and the fourth color filter is provided in the same layer and the same material as at least part of the encapsulation layer.

30. The display substrate according to claim 28, wherein The first sub-pixel region is a red sub-pixel region, the second sub-pixel region is a green sub-pixel region, the third sub-pixel region is a blue sub-pixel region, and the fourth sub-pixel region is a white sub-pixel region.

31. The display substrate according to claim 30, wherein: The first sub-side of the white sub-pixel region is connected to the first sub-side of the red sub-pixel region, and the morphology of the first sub-side of the white sub-pixel region is different from the morphology of the first sub-side of the red sub-pixel region.

32. The display substrate according to claim 30, wherein: The black matrix also includes a second sub-side arranged opposite to the first sub-side, the second sub-side of the green sub-pixel area is adjacent to the second sub-side of the blue sub-pixel area, and the number of folding angles of the second sub-side of the green sub-pixel area is greater than the number of folding angles of the second sub-side of the blue sub-pixel area.

33. The display substrate according to claim 30, wherein: The black matrix between two adjacent sub-pixel regions is conformal.

34. The display substrate according to claim 30, wherein: The number of folding angles of the black matrix between the white sub-pixel region and the green sub-pixel region is greater than the number of folding angles of the black matrix between the red sub-pixel region and the blue sub-pixel region.

35. The display substrate according to claim 30, wherein: The areas of sub-pixel regions of different colors are different.

36. The display substrate according to claim 1, wherein: The display substrate further includes a blank structure, and an orthographic projection of the blank structure on the substrate does not overlap with an orthographic projection of the sub-pixel region on the substrate.

37. The display substrate according to claim 36, wherein: The ratio of the area of ​​the blank structure to the area of ​​the sub-pixel region is greater than or equal to 45%.

38. The display substrate according to claim 37, wherein: The ratio of the area of ​​the blank structure to the area of ​​the sub-pixel region is equal to 46%.

39. The display substrate according to claim 36, wherein: The blank structure has a fifth width along the first direction, and the fifth width is equal to or substantially equal to the total length of all the fold line structures of the first sub-side.

40. The display substrate according to claim 36, wherein The multiple sub-pixel areas include a white sub-pixel area and a red sub-pixel area, and the blank structure has a first sub-edge adjacent to the first sub-side of the white sub-pixel area and the first sub-side of the red sub-pixel area, and the shape of the first sub-edge is conformal to the shape of the first sub-side of the white sub-pixel area and the first sub-side of the red sub-pixel area.

41. The display substrate according to claim 36, wherein The driving circuit layer further includes a repair structure, and an orthographic projection of the repair structure on the substrate at least partially overlaps with an orthographic projection of the blank structure on the substrate.

42. The display substrate according to claim 41, wherein The multiple sub-pixel regions include a red sub-pixel region and a blue sub-pixel region, and the repair structures of the red sub-pixel region and the repair structures of the blue sub-pixel region are at least partially symmetrical and at least partially asymmetrical.

43. The display substrate according to claim 1, wherein The light emitting structure layer further includes an anode, the first opening at least partially exposes the anode, and at least one sub-pixel region includes a plurality of discretely arranged sub-anode blocks.

44. The display substrate according to claim 43, wherein: The plurality of discretely arranged sub-anode blocks includes two.

45. The display substrate according to claim 44, wherein The two sub-anode blocks have different morphologies.

46. ​​The display substrate according to claim 45, wherein: The driving circuit layer includes anode holes, and the anode holes are electrically connected to the two sub-anode blocks respectively.

47. The display substrate according to claim 46, wherein: The driving circuit layer further includes a repair structure, and the two sub-anode blocks are electrically connected to each other and to the repair structure.

48. A display device comprising the display substrate according to any one of claims 1 to 47.

49. A method for preparing a display substrate, comprising: forming a driving circuit layer on the substrate; forming a light-emitting structure layer on a side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, the organic light-emitting layer being located in the sub-pixel region and overlapping with the first opening of the pixel defining layer; A color film structure layer is formed on a side of the light-emitting structure layer away from the substrate, the color film structure layer includes a color film and a black matrix, the black matrix has a second opening that at least partially exposes the first opening, the color film is arranged in the second opening, the black matrix includes a first sub-side, and the first sub-side has a fold line structure.

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