DISPLAY PLATFORMS, DISPLAY PANELS, AND DISPLAY DEVICES

Abstract

The invention proposes a display substrate, a display panel, and a display device. None of the orthogonal projections, on the substrate, of the pixel holes of the first, second, and third color subpixels of the display substrate overlap with the orthogonal projections, on the substrate, of the conduction channels of the transistors controlling the subpixels.Or, the orthogonal projection, on the substrate, of the pixel hole of at least one superimposed subpixel aligns with the orthogonal projection, on the substrate, of the conduction channels of the control transistor of the subpixel; the orthogonal projections, in the first direction, of the pixel hole of at least one superimposed subpixel of the second color and the pixel holes of the first and third color subpixels align; none of the orthogonal projections, in the second direction, of the pixel holes of the second, first, and third color subpixels align; and the first direction intersects the second direction.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) have the advantages of self-luminescence, high efficiency, bright colors, light weight, power saving, and a wide operating temperature range. They have gradually been used in large-area displays, lighting, and automotive displays.

[0003] Summary of the Invention

[0004] According to a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate;

[0005] The plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels; the human eye is more sensitive to the first color than to the third color, and the human eye is more sensitive to the third color than to the second color; the sub-pixels include an organic light-emitting element and a pixel circuit for driving the organic light-emitting element; the organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting material located between the first electrode and the second electrode; the first electrode of the sub-pixel is electrically connected to the pixel circuit; and the pixel circuit includes a driving transistor;

[0006] The display substrate further comprises an active semiconductor layer and a pixel defining layer, wherein the active semiconductor layer comprises a channel and a source / drain region of a driving transistor of each sub-pixel; the pixel defining layer is provided with pixel openings corresponding to the sub-pixels one by one;

[0007] The orthographic projection of the pixel opening of the first color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the substrate substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the substrate substrate, and the orthographic projection of the pixel opening of the third color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the substrate substrate; or

[0008] The orthographic projection of the pixel opening of at least one sub-pixel on the substrate overlaps with the orthographic projection of the channel of its driving transistor on the substrate, the orthographic projection of the pixel opening of at least one second-color sub-pixel in the first direction overlaps with the orthographic projection of the pixel opening of the first color sub-pixel in the first direction and the orthographic projection of the pixel opening of the third color sub-pixel in the first direction, and the orthographic projection of the pixel opening of the second color sub-pixel in the second direction does not overlap with the orthographic projection of the pixel opening of the first color sub-pixel in the second direction and the orthographic projection of the pixel opening of the third color sub-pixel in the second direction, and the first direction intersects with the second direction.

[0009] In one embodiment, the orthographic projection of the pixel opening of the first color sub-pixel on the substrate overlaps with the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the substrate overlaps with the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the substrate, and the orthographic projection of the pixel opening of the third color sub-pixel on the substrate overlaps with the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the substrate.

[0010] In one embodiment, the multiple sub-pixels are divided into multiple pixel groups, each of the pixel groups includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; at least one of the pixel groups includes two rows of sub-pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction includes the first color sub-pixels and the third color sub-pixels arranged alternately, and the other row of sub-pixels arranged along the first direction includes the second color sub-pixels.

[0011] In one embodiment, in at least one of the pixel groups, the orthographic projection of the pixel opening corresponding to each of the sub-pixels on the substrate does not overlap with the orthographic projection of the gate of the driving transistor of any of the sub-pixels on the substrate, or

[0012] An orthographic projection of the pixel opening corresponding to each sub-pixel on the substrate overlaps with an orthographic projection of the gate of the driving transistor of any sub-pixel on the substrate, and a ratio of an area of ​​the overlapping area to an area of ​​the gate is no more than 10%.

[0013] In one embodiment, the display substrate is further provided with a plurality of scanning signal lines extending along the first direction, and the scanning signal lines are configured to provide scanning signals to the pixel groups;

[0014] In at least one pixel group, in the second direction, a distance from a channel of a driving transistor of the second color sub-pixel to the scanning signal line is different from a distance from a channel of a driving transistor of the first color sub-pixel to the scanning signal line.

[0015] In one embodiment, in at least one pixel group, in the second direction, the distance from the channel of the driving transistor of the second color sub-pixel to the scanning signal line is greater than the distance from the channel of the driving transistor of the first color sub-pixel to the scanning signal line.

[0016] In one embodiment, the display substrate is further provided with a scanning signal line extending along the first direction, and the scanning signal line is configured to provide a scanning signal to the pixel group;

[0017] In at least one pixel group, an orthographic projection of the scanning signal line in a second direction overlaps with an orthographic projection of the gate of the driving transistor of the sub-pixel in the second direction, and the second direction is perpendicular to the first direction.

[0018] In one embodiment, the display substrate further comprises a scan signal line extending along the first direction, the scan signal line being configured to provide a scan signal to the sub-pixel; the scan signal line comprising a scan signal line main portion and a protruding portion protruding from one side of the scan signal line main portion; the scan signal line main portion comprising a first sub-scan line, a second sub-scan line, and a connecting portion, the first sub-scan line and the second sub-scan line being connected via the connecting portion; the first sub-scan line being connected to a pixel circuit of a first color sub-pixel, and the second sub-scan line being connected to a pixel circuit of a second color sub-pixel; and an extending direction of a portion of the connecting portion intersecting with an extending direction of the first sub-scan line;

[0019] The pixel circuit includes a compensation transistor, which includes a first gate and a second gate; in the compensation transistor, the first gate is a portion of the connecting portion that overlaps with the orthographic projection of the active semiconductor layer on the base substrate, and the second gate is a portion of the protruding portion that overlaps with the orthographic projection of the active semiconductor layer on the base substrate.

[0020] In one embodiment, the connection portion includes a first sub-connection portion, a second sub-connection portion, and a third sub-connection portion connected in sequence, the first sub-connection portion and the third sub-connection portion intersect with an extension direction of the first sub-scan line, and the second sub-connection portion and the first sub-scan line extend in the same direction;

[0021] The first gate is a portion of the second sub-connecting portion that overlaps with an orthographic projection of the active semiconductor layer on the base substrate.

[0022] In one embodiment, the active semiconductor layer includes a first segment, a second segment, a third segment, and a fourth segment connected in sequence; the second segment, the fourth segment, and the main portion of the scanning signal line extend along the first direction, the first segment and the third segment extend along a second direction, and the second direction intersects the first direction; the display substrate further includes a reset control signal line extending along the first direction and disposed on the same layer as the scanning signal line; the pixel circuit includes a reset transistor, and the reset transistor includes a gate;

[0023] The second gate is a portion of the protrusion overlapping with the orthographic projection of the fourth segment on the substrate; the gate of the reset transistor includes a portion of the reset control signal line overlapping with the orthographic projection of the first segment on the substrate.

[0024] In one embodiment, the pixel circuit further includes a threshold compensation transistor, wherein the threshold compensation transistor includes a gate; the display substrate further includes a connection structure, wherein one end of the connection structure is connected to the gate of the driving transistor, and the other end of the connection structure is connected to the source and drain region of the threshold compensation transistor;

[0025] The connecting structure includes a first part and a second part connected to the first part, the orthographic projection of the first part on the base substrate and the orthographic projection of the protrusion on the base substrate are located on the same side of the orthographic projection of the main body of the scanning signal line on the base substrate; the length of the first part in the second direction is greater than the length of the protrusion in the second direction.

[0026] In one embodiment, a size of the connection structure in the second direction ranges from 35 μm to 70 μm.

[0027] In one embodiment, the display substrate is further provided with a plurality of scanning signal lines and reset control signal lines extending along the first direction, the scanning signal lines are configured to provide scanning signals to the pixel groups, and the reset control signal lines are configured to provide reset control signals to the pixel groups;

[0028] The orthographic projection of the first electrode of at least one second color sub-pixel on the base substrate overlaps with the orthographic projection of the reset control signal line on the base substrate and the orthographic projection of the scan signal line on the base substrate.

[0029] In one embodiment, any one of the orthographic projections of the pixel opening of the first color sub-pixel on the substrate, the orthographic projections of the pixel opening of the second color sub-pixel on the substrate, and the orthographic projections of the pixel opening of the third color sub-pixel on the substrate does not overlap with any one of the orthographic projections of the channel of the driving transistor of the first color sub-pixel on the substrate, the orthographic projections of the channel of the driving transistor of the second color sub-pixel on the substrate, and the orthographic projections of the channel of the driving transistor of the third color sub-pixel on the substrate.

[0030] In one embodiment, the display substrate is further provided with a scanning signal line, which is configured to provide a scanning signal to the pixel group; the distance between the channel of the driving transistor of the sub-pixel and the scanning signal line in the second direction ranges from 1 μm to 50 μm.

[0031] In one embodiment, the pixel circuit further includes a capacitor, which includes a first plate and a second plate located on the side of the first plate facing away from the base substrate; the area of ​​the second plate of the second color sub-pixel is larger than the area of ​​the second plate of the first color sub-pixel, and the area of ​​the second plate of the second color sub-pixel is larger than the area of ​​the second plate of the third color sub-pixel.

[0032] In one embodiment, the display substrate further includes a first power line and a second power line located on a side of the first power line facing away from the base substrate; the first power line and the second power line are configured to provide a power signal to the pixel circuit; the first power line is electrically connected to the second power line;

[0033] The second power line includes a first sub-power line extending along the first direction and a second sub-power line extending along the second direction, and the first sub-power line intersects the second sub-power line.

[0034] In one embodiment, the pixel circuit further includes a light emitting control transistor and an electrode connection structure, wherein the electrode connection structure electrically connects the first electrode of the sub-pixel to the source and drain regions of the light emitting control transistor;

[0035] The areas of the electrode connection structures of at least two of the sub-pixels are different.

[0036] In one embodiment, the electrode connection structure includes at least a first sub-electrode connection structure and a second sub-electrode connection structure located on the side of the first sub-electrode connection structure away from the base substrate; the areas of the first sub-electrode connection structure and / or the second sub-electrode connection structure of at least two of the sub-pixels are different.

[0037] In one embodiment, the display substrate further includes a shielding line and a reset power signal line, wherein the reset power signal line is configured to provide a reset power signal to the sub-pixel; and the shielding line is electrically connected to the reset power signal line.

[0038] In one embodiment, the size range of the first color sub-pixel in the first direction is 35μm to 110μm, and the size range in the second direction is 20μm to 60μm; the size range of the second color sub-pixel in the first direction is 35μm to 120μm, and the size range in the second direction is 20μm to 80μm; the size range of the third color sub-pixel in the first direction is 35μm to 70μm, and the size range in the second direction is 20μm to 60μm.

[0039] According to a second aspect of an embodiment of the present application, a display panel is provided, comprising the above-mentioned display substrate.

[0040] According to a third aspect of the embodiments of the present application, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a circuit diagram of a pixel circuit provided by an exemplary embodiment of the present application;

[0042] 2 to 7 are partial schematic diagrams of various layers of a display substrate provided by an exemplary embodiment of the present application; FIG. 2A is a partial enlarged view of FIG. 2 ;

[0043] 7A is a schematic diagram of a portion of film layers of a plurality of pixel groups of a display substrate provided by an exemplary embodiment of the present application;

[0044] FIG8 is a partial cross-sectional view of a position of a display substrate provided by an exemplary embodiment of the present application;

[0045] FIG9 is a partial cross-sectional view of another position of a display substrate provided by an exemplary embodiment of the present application;

[0046] FIG10 is a partial schematic diagram of multiple film layers of a display substrate provided by another exemplary embodiment of the present application;

[0047] FIG10A is a partial enlarged view of the scanning signal line in FIG10;

[0048] FIG11 is a partial schematic diagram of a portion of film layers of a display substrate provided by an exemplary embodiment of the present application;

[0049] 12 to 16 are partial schematic diagrams of various layers of a display substrate provided by yet another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0051] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0052] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0053] The embodiments of the present application provide a display substrate, a display panel, and a display device. The display substrate, display panel, and display device in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.

[0054] The embodiments of the present application provide a display substrate, a display panel, and a display device. The display substrate, display panel, and display device in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.

[0055] An embodiment of the present application provides a display substrate. The display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate. The plurality of sub-pixels are arranged at intervals on the base substrate.

[0056] The plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels. The human eye is more sensitive to the first color than to the third color, and the human eye is more sensitive to the third color than to the second color. The color of a sub-pixel refers to the color of light emitted by the sub-pixel. In some embodiments, the first color is green, the second color is blue, and the third color is red.

[0057] The subpixel includes an organic light-emitting element and a pixel circuit for driving the organic light-emitting element; the organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting material located between the first electrode and the second electrode. The first electrode of the subpixel is electrically connected to the pixel circuit. In some embodiments, the first electrode may be an anode, and the second electrode may be a cathode.

[0058] In one embodiment, the display substrate further includes a pixel defining layer having pixel openings corresponding one-to-one with the sub-pixels. The pixel defining layer is disposed between adjacent sub-pixels, and the pixel openings are used to define the light-emitting area of ​​each color sub-pixel. The orthographic projection of the pixel opening of the pixel defining layer on the base substrate is located within the orthographic projection of the first electrode of the corresponding sub-pixel on the base substrate.

[0059] In some embodiments, the organic light-emitting material is located on a side of the first electrode away from the substrate. The first electrode of each color sub-pixel contacts the organic light-emitting material at the pixel opening of the pixel defining layer, and the pixel opening of the pixel defining layer defines the shape of the sub-pixel light-emitting area. For example, the first electrode (e.g., an anode) of the organic light-emitting element can be disposed below the pixel defining layer, and the pixel opening of the pixel defining layer exposes a portion of the first electrode. When the organic light-emitting material is formed in the pixel opening in the above-mentioned pixel defining layer, the organic light-emitting material contacts the first electrode, so that this portion of the first electrode can drive the organic light-emitting material to emit light.

[0060] In some embodiments, the orthographic projection of the pixel opening of the pixel defining layer on the base substrate is located within the orthographic projection of the corresponding organic light-emitting material on the base substrate, that is, the organic light-emitting material covers the pixel opening of the pixel defining layer. For example, the area of ​​the organic light-emitting material is larger than the area of ​​the corresponding pixel opening, that is, in addition to the portion located inside the pixel opening, the organic light-emitting material also includes at least a portion covering the physical structure of the pixel defining layer. Typically, the physical structure of the pixel defining layer at each boundary of the pixel opening is covered with organic light-emitting material. It should be noted that the above description of the pattern of the organic light-emitting material is based on the organic light-emitting material of each sub-pixel patterned by, for example, the FMM process. In addition to the FMM manufacturing process, some organic light-emitting materials use an open mask process to form an integral film layer in the entire display area. The orthographic projection of its shape on the base substrate is continuous, so there must be a portion located inside the pixel opening and a portion located on the physical structure of the pixel defining layer.

[0061] In one embodiment, the plurality of sub-pixels are divided into a plurality of pixel groups, and the organic light-emitting elements of the plurality of pixel groups are arranged along a first direction and a second direction on the substrate, and the first direction and the second direction intersect. The pixel group includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. In some embodiments, the first direction and the second direction are perpendicular. In some embodiments, the first direction is a row direction, and the second direction is a column direction. In some embodiments, the pixel circuits of the sub-pixels in each of the pixel groups are arranged in an alternating manner in the first direction.

[0062] In one embodiment, the area covered by the orthographic projection of the pixel circuit of the sub-pixel on the substrate is roughly located within a rectangular frame. The orthographic projection of the pixel circuit on the substrate mainly includes the orthographic projection of the structures of various components such as transistors and capacitors on the substrate. The display substrate also includes a plurality of signal lines, which are used to drive the pixel circuit. It should be noted that some signal lines include a portion located within the rectangular frame and a portion extending outside the rectangular frame. The pixel circuit also includes an electrode connection structure, which electrically connects the pixel circuit of the sub-pixel to the first electrode.

[0063] 1 , the pixel circuit 221 includes a driving circuit 222. The driving circuit 222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current to the organic light emitting element 220 to drive the organic light emitting element 220 to emit light.

[0064] In one embodiment, as shown in FIG1 , the pixel circuit 221 includes a first light emission control circuit 223 and a second light emission control circuit 224. For example, the first light emission control circuit 223 is connected to a first terminal of the driving circuit 222 and a first voltage terminal VDD, and is configured to connect or disconnect the driving circuit 222 and the first voltage terminal VDD. The second light emission control circuit 224 is electrically connected to a second terminal of the driving circuit 222 and a first electrode of the organic light emitting element 220, and is configured to connect or disconnect the driving circuit 222 and the organic light emitting element 220.

[0065] In one embodiment, as shown in FIG1 , the pixel circuit 221 further includes a data write circuit 226, a storage circuit 227, a threshold compensation circuit 228, and a reset circuit 229. The data write circuit 226 is electrically connected to a first terminal of the driver circuit 222 and is configured to write a data signal into the storage circuit 227 under the control of a scan signal. The storage circuit 227 is electrically connected to a control terminal and a first voltage terminal VDD of the driver circuit 222 and is configured to store the data signal. The threshold compensation circuit 228 is electrically connected to a control terminal and a second terminal of the driver circuit 222 and is configured to perform threshold compensation for the driver circuit 222. The reset circuit 229 is electrically connected to the control terminal of the driver circuit 222 and the first electrode of the organic light-emitting element 220 and is configured to reset the control terminal of the driver circuit 222 and the first electrode of the organic light-emitting element 220 under the control of a reset control signal.

[0066] In one embodiment, as shown in FIG1 , the driving circuit 222 includes a driving transistor T1 , the control end of the driving circuit 222 includes the gate of the driving transistor T1 , the first end of the driving circuit 222 includes the first electrode of the driving transistor T1 , and the second end of the driving circuit 222 includes the second electrode of the driving transistor T1 .

[0067] In one embodiment, as shown in Figure 1, the data write circuit 226 includes a data write transistor T2, the storage circuit 227 includes a capacitor C, the threshold compensation circuit 228 includes a threshold compensation transistor T3, the first light-emitting control circuit 223 includes a first light-emitting control transistor T4, the second light-emitting control circuit 224 includes a second light-emitting control transistor T5, the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0068] In one embodiment, as shown in FIG1 , a first electrode of the data write transistor T2 is electrically connected to a first electrode of the drive transistor T1, a second electrode of the data write transistor T2 is configured to be electrically connected to a data line Vd to receive a data signal, and a gate of the data write transistor T2 is configured to be electrically connected to a scan signal line Ga1 to receive a scan signal; a first electrode of the capacitor C is electrically connected to a first power supply terminal VDD, and a second electrode of the capacitor C is electrically connected to the gate of the drive transistor T1; a first electrode of the threshold compensation transistor T3 is electrically connected to a second electrode of the drive transistor T1, a second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the drive transistor T1, and a gate of the threshold compensation transistor T3 is configured to be electrically connected to a scan signal line Ga2 to receive a compensation control signal; a first electrode of the first reset transistor T6 is configured to be electrically connected to a reset power supply terminal Vinit1 to receive a first reset signal, a second electrode of the first reset transistor T6 is electrically connected to the gate of the drive transistor T1, and a gate of the first reset transistor T6 is configured to be electrically connected to a reset control signal line Rst1 to receive a first sub-reset control signal. a first electrode of the second reset transistor T7 is configured to be electrically connected to the reset power supply terminal Vinit2 to receive the second reset signal, a second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organic light emitting element 220, and a gate of the second reset transistor T7 is configured to be electrically connected to the reset control signal line Rst2 to receive the second sub-reset control signal; a first electrode of the first emission control transistor T4 is electrically connected to the first power supply terminal VDD, a second electrode of the first emission control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and a gate of the first emission control transistor T4 is configured to be electrically connected to the emission control signal line EM1 to receive the first emission control signal; a first electrode of the second emission control transistor T5 is electrically connected to the second electrode of the driving transistor T1, a second electrode of the second emission control transistor T5 is electrically connected to the second electrode of the organic light emitting element 220, and a gate of the second emission control transistor T5 is configured to be electrically connected to the emission control signal line EM2 to receive the second emission control signal; and a first electrode of the organic light emitting element 220 is electrically connected to the second power supply terminal VSS.

[0069] In one embodiment, one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. In the embodiment shown in FIG1 , the first power supply terminal VDD is a voltage source that outputs a constant first voltage, which is a positive voltage; and the second power supply terminal VSS is a voltage source that outputs a constant second voltage, which is a negative voltage, etc. In some exemplary embodiments, the second power supply terminal VSS can be grounded.

[0070] In one embodiment, as shown in FIG1 , the scan signal and the compensation control signal can be the same, that is, the gate of the data write transistor T2 and the gate of the threshold compensation transistor T3 can be electrically connected to the same signal line, such as the scan signal line Ga1, to receive the same signal (e.g., the scan signal). In this case, the display substrate 1000 can be provided with no scan signal line Ga2, thereby reducing the number of signal lines. For another example, the gate of the data write transistor T2 and the gate of the threshold compensation transistor T3 can also be electrically connected to different signal lines, that is, the gate of the data write transistor T2 is electrically connected to the scan signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the scan signal line Ga2, and the scan signal line Ga1 and the scan signal line Ga2 transmit the same signal.

[0071] It should be noted that the scanning signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately and independently, thereby increasing the flexibility of controlling the pixel circuit.

[0072] In one embodiment, as shown in FIG1 , the first emission control signal and the second emission control signal can be the same. That is, the gate of the first emission control transistor T4 and the gate of the second emission control transistor T5 can be electrically connected to the same signal line, such as the emission control signal line EM1, to receive the same signal (e.g., the first emission control signal). In this case, the display substrate 1000 can be provided with no emission control signal line EM2, thereby reducing the number of signal lines. In other embodiments, the gate of the first emission control transistor T4 and the gate of the second emission control transistor T5 can also be electrically connected to different signal lines, that is, the gate of the first emission control transistor T4 is electrically connected to the emission control signal line EM1, and the gate of the second emission control transistor T5 is electrically connected to the emission control signal line EM2, and the emission control signal line EM1 and the emission control signal line EM2 transmit the same signal.

[0073] It should be noted that when the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are different types of transistors, for example, the first light-emitting control transistor T4 is a P-type transistor and the second light-emitting control transistor T5 is an N-type transistor, the first light-emitting control signal and the second light-emitting control signal may also be different, and the embodiments of the present application do not limit this.

[0074] In one embodiment, the first sub-reset control signal and the second sub-reset control signal can be the same. That is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 can be electrically connected to the same signal line, such as the reset control signal line Rst1, to receive the same signal (e.g., the first sub-reset control signal). In this case, the display substrate 1000 can be provided with no reset control signal line Rst2, thereby reducing the number of signal lines. For another example, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 can also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the reset control signal line Rst2, and the reset control signal line Rst1 and the reset control signal line Rst2 transmit the same signal. It should be noted that the first sub-reset control signal and the second sub-reset control signal can also be different. In another embodiment, the first sub-reset control signal is different from the second sub-reset control signal. The pulse width of the reset control signal line Rst2 is greater than the pulse width of the reset control signal line Rst1, and the pulse width of the reset control signal line Rst2 is less than the pulse width of the light-emitting control signal line EM2 when the second light-emitting control transistor T5 is turned off. This helps to extend the lifespan of the organic light-emitting element of the sub-pixel.

[0075] In one embodiment, the second sub-reset control signal may be the same as the scan signal, ie, the gate of the second reset transistor T7 may be electrically connected to the scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.

[0076] In one embodiment, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2, respectively. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be DC reference voltage terminals to output a constant DC reference voltage. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same, for example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first reset signal and the second reset signal to reset the gate of the driving transistor T1 and the first electrode of the light-emitting element 220. This application does not limit this.

[0077] It should be noted that the driving circuit 222, data writing circuit 226, storage circuit 227, threshold compensation circuit 228 and reset circuit 229 in the pixel circuit shown in Figure 1 are only schematic. The specific structures of circuits such as the driving circuit 222, data writing circuit 226, storage circuit 227, threshold compensation circuit 228 and reset circuit 229 can be set according to actual application requirements, and the embodiments of the present application do not make specific limitations on this.

[0078] According to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present application take the transistor as a P-type transistor (for example, a P-type MOS transistor) as an example to explain the technical solution of the present application in detail. That is, in the description of the present application, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6, the second reset transistor T7, etc. can all be P-type transistors. Of course, the transistors in the embodiments of the present application are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present application according to actual needs.

[0079] It should be noted that the transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present application, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present application can be interchangeable as needed.

[0080] It should be noted that in the embodiment of the present application, in addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown in Figure 1, the pixel circuit of the sub-pixel can also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiment of the present application is not limited to this.

[0081] FIG2-7 is a schematic diagram of each layer of a pixel circuit provided by an embodiment of the present application. The following describes the positional relationship of each circuit in the pixel circuit on the backplane in conjunction with FIG2-7. The example shown in FIG2-7 takes the pixel circuit 221 of a pixel group as an example, and illustrates the position of each transistor of the pixel circuit included in the first color sub-pixel 110. The components included in the pixel circuits of the second color sub-pixel 120 and the third color sub-pixel 130 are roughly the same as the positions of the transistors included in the first color sub-pixel. As shown in FIG2, the pixel circuit 221 of the first color sub-pixel 110 includes the driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, second reset transistor T7 and capacitor C shown in FIG1.

[0082] 2-7 also illustrate the scanning signal line Ga1, reset control signal line Rst1, reset power signal line Init1, light emission control signal line EM1, data line Vd, power signal lines (including a first power signal line VDD1, a second power signal line VDD3, and a third power signal line VDD2 connected to a first power supply terminal VDD), and shielding line 344, which are electrically connected to the pixel circuit 121 of each color sub-pixel. The first power signal line VDD1 and the second power signal line VDD3 are electrically connected to each other, and the first power signal line VDD1 and the third power signal line VDD2 are electrically connected to each other. The second power line VDD3 includes a first sub-power line VDD31 extending along the first direction Y and a second sub-power line VDD32 extending along the second direction X, with the first sub-power line VDD31 and the second sub-power line VDD32 intersecting.

[0083] The scanning signal line Ga1 is configured to provide a scanning signal to the pixel group; the reset control signal line Rst1 is configured to provide a reset control signal to the pixel group; the reset power signal line Init1 is configured to provide a reset power signal to the pixel group; the light-emitting control signal line EM1 is configured to provide a light-emitting control signal to the pixel group; the data line Vd is configured to provide a light-emitting data signal to the pixel group; the first power signal line VDD1, the second power signal line VDD3 and the third power signal line VDD2 are configured to provide power signals to the pixel group.

[0084] For example, FIG2 shows an active semiconductor layer 310 of a pixel circuit in the display substrate. The active semiconductor layer 310 can be formed by patterning a semiconductor material. The active semiconductor layer 310 can be used to make the channels of the above-mentioned drive transistor T1, data write transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7. The active semiconductor layer 310 includes the channel and source-drain region of each transistor of each sub-pixel (i.e., the source region s and drain region d shown in the second color sub-pixel), and the channel and source-drain region of each transistor in the same pixel circuit are arranged in one piece. The active semiconductor layer 310 shown in FIG2 includes a channel 301 of the first color sub-pixel, a channel 302 of the second color sub-pixel, and a channel 303 of the third color sub-pixel.

[0085] It should be noted that the active semiconductor layer may include an integrally formed low-temperature polysilicon layer, wherein the source and drain regions may be made conductive through doping, etc., to achieve electrical connection between the various structures. In other words, the active semiconductor layer of each transistor in each sub-pixel is a monolithic pattern formed of p-silicon, and each transistor in the same pixel circuit includes a source and drain region (i.e., a source region s and a drain region d) and a channel, with the channels of different transistors separated by the source and drain regions.

[0086] In one embodiment, the active semiconductor layers in the pixel circuits of sub-pixels of different colors arranged along the first direction are not connected and are disconnected from each other. The active semiconductor layers in the pixel circuits of sub-pixels of the same color arranged along the second direction can be integrated or disconnected from each other.

[0087] In one embodiment, the active semiconductor layer 310 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0088] For example, the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer. A gate insulating layer 103 (as shown in Figures 8 and 9) is formed on the active semiconductor layer 310 to protect the active semiconductor layer 310. The active semiconductor layer 310 is located on the base substrate 100. Figure 3 shows the first conductive layer 320 included in the display substrate. The first conductive layer 320 is disposed on the gate insulating layer to be insulated from the active semiconductor layer 310. The first conductive layer 320 may include the second plate CC2 of the capacitor C, the scan signal line Ga1, the reset control signal line Rst1, the emission control signal line EM1, and the gates of the drive transistor T1, the data write transistor T2, the threshold compensation transistor T3, the first emission control transistor T4, the second emission control transistor T5, the first reset transistor T6, and the second reset transistor T7. The scan signal line Ga1 includes a scan signal line main portion Ga11 and a protrusion P protruding from one side of the scan signal line main portion Ga11.

[0089] For example, as shown in FIG3 , the gate of the data write transistor T2 may be the portion where the scan signal line Ga1 overlaps with the active semiconductor layer 310; the gate of the first emission control transistor T4 may be the first portion where the emission control signal line EM1 overlaps with the active semiconductor layer 310, and the gate of the second emission control transistor T5 may be the second portion where the emission control signal line EM1 overlaps with the active semiconductor layer 310; the gate of the first reset transistor T6 may be the first portion where the reset control signal line Rst1 overlaps with the active semiconductor layer 310, and the gate of the second reset transistor T7 may be the second portion where the reset control signal line Rst1 overlaps with the active semiconductor layer 310; the threshold compensation transistor T3 may be a dual-gate thin-film transistor, the first gate of the threshold compensation transistor T3 may be the portion where the scan signal line Ga1 overlaps with the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 may be the portion where the protrusion P of the scan signal line Ga1 overlaps with the active semiconductor layer 310. As shown in FIG1 and FIG3 , the gate of the drive transistor T1 may be the second plate CC2 of the capacitor C.

[0090] It should be noted that the dashed rectangular frames in FIG. 2 represent overlapping portions of the first conductive layer 320 and the active semiconductor layer 310 .

[0091] For example, as shown in FIG3 , the scan signal line Ga1, the reset control signal line Rst1, and the emission control signal line EM1 are arranged along the second direction X. The scan signal line Ga1 is located between the reset control signal line Rst1 and the emission control signal line EM1. The signal lines extending along the first direction refer to the entire row of signal lines extending along the first direction, with the area of ​​the portion of the signal lines extending in the first direction being much larger than the area of ​​the portion extending in the second direction; the signal lines extending along the second direction refer to the entire row of signal lines extending along the second direction, with the area of ​​the portion of the signal lines extending in the second direction being much larger than the area of ​​the portion extending in the first direction.

[0092] For example, in the second direction X, the second plate CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scanning signal line Ga1 and the emission control signal line EM1. The protrusion P of the scanning signal line Ga1 is located on a side of the scanning signal line Ga1 away from the emission control signal line EM1.

[0093] For example, as shown in FIG2 , in the second direction X, the gate of the data write transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all located on a first side of the gate of the drive transistor T1, and the gates of the first emission control transistor T4 and the second emission control transistor T5 are all located on a second side of the gate of the drive transistor T1. For example, in the example shown in FIG2-7 , the first side and the second side of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel are two opposite sides of the gate of the drive transistor T1 in the second direction X. For example, as shown in FIG2-7 , in the XY plane, the first side of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel can be the upper side of the gate of the drive transistor T1, and the second side of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel can be the lower side of the gate of the drive transistor T1. The lower side, for example, the side of the display substrate used for bonding the driver chip is the lower side of the display substrate, and the lower side of the gate of the drive transistor T1 is the side of the gate of the drive transistor T1 closer to the driver chip. The upper side is an opposite side to the lower side, for example, a side of the gate of the driving transistor T1 that is farther away from the driving chip.

[0094] For example, in some embodiments, as shown in FIG2-7 , in the first direction Y, the gate of the data write transistor T2 and the gate of the first emission control transistor T4 are both located on the third side of the gate of the drive transistor T1, and the first gate of the threshold compensation transistor T3, the gate of the second emission control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the drive transistor T1. For example, in the example shown in FIG2-7 , the third side and the fourth side of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel are opposite sides of the gate of the drive transistor T1 in the first direction Y. For example, as shown in FIG2-7 , the third side of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel can be to the left of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel, and the fourth side of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel can be to the right of the gate of the drive transistor T1 in the pixel circuit of the first color subpixel. The left and right sides, for example, in the same pixel circuit, are where the data line is to the left of the first power signal line VDD1 and the first power signal line VDD1 is to the right of the data line.

[0095] For example, a first insulating layer 104 (as shown in Figures 8 and 9) is formed on the first conductive layer 320 to protect the first conductive layer 320. Figure 4 shows the second conductive layer 330 of the pixel circuit. The second conductive layer 330 includes a first plate CC1 of the capacitor C, a reset power signal line Init1, a third power signal line VDD2, and a light shielding portion S. The third power signal line VDD2 is integrally formed with the first plate CC1 of the capacitor C. The first plate CC1 of the capacitor C and the second plate CC2 of the capacitor C at least partially overlap to form the capacitor C.

[0096] For example, a second insulating layer 105 (as shown in Figures 8 and 9) is formed on the second conductive layer 330 to protect the second conductive layer 330. Figure 5 shows the source-drain metal layer 340 of the pixel circuit. The source-drain metal layer 340 includes a data line Vd, a first power signal line VDD1, and a shielding line 344. The data line Vd, the first power signal line VDD1, and the shielding line 344 all extend along the second direction X. The shielding line 344 is provided in the same layer and material as the data line Vd, so that the shielding line can be formed simultaneously with the data line in the same patterning process, avoiding the addition of an additional patterning process to form the shielding line, thereby simplifying the production process of the display substrate and saving production costs. For example, the source-drain metal layer 340 also includes a connecting structure 341, a connecting portion 342, and a first sub-electrode connecting structure 343 of the electrode connecting structure. One end of the connecting structure 341 is connected to the gate of the driving transistor T1, and the other end of the connecting structure 341 is connected to the source and drain region of the threshold compensation transistor T3.

[0097] FIG5 also shows exemplary locations of multiple vias, through which the source / drain metal layer 340 is connected to multiple film layers located between the source / drain metal layer 340 and the substrate. For example, the source / drain metal layer 340 is connected to the active semiconductor layer 310 shown in FIG2 through vias 381, 382, ​​384, 387, and 352. The source / drain metal layer 340 is connected to the second conductive layer 330 shown in FIG4 through vias 3832, 386, 385, 331, and 332. The specific film layers where the vias are located and the specific connection relationships will be described in detail in the subsequent diagram shown in FIG7.

[0098] For example, a third insulating layer 106 and a fourth insulating layer 107 (as shown in FIG8 and FIG9 ) are formed on the source / drain metal layer 340 to protect the source / drain metal layer 340. The organic light-emitting element of each sub-pixel can be disposed on a side of the third insulating layer and the fourth insulating layer away from the base substrate.

[0099] Figure 6 shows the third conductive layer 350 of the pixel circuit. The third conductive layer 350 includes a second sub-electrode connection structure 353 of the electrode connection structure and a second power signal line VDD3 distributed along the second direction X and the first direction Y. Figure 6 also shows exemplary locations of multiple vias 351 and 354. The third conductive layer 350 is connected to the source-drain metal layer 340 through the multiple vias 351 and 354 shown.

[0100] Figure 7 is a schematic diagram illustrating the stacking relationship of the active semiconductor layer 310, first conductive layer 320, second conductive layer 330, source / drain metal layer 340, and third conductive layer 350. As shown in Figures 2-7, the data line Vd is connected to the source region of the data write transistor T2 in the active semiconductor layer 310 via at least one via (e.g., via 381) in the gate insulating layer, the first insulating layer, and the second insulating layer. The first power signal line VDD1 is connected to the source region of the corresponding first emission control transistor T4 in the active semiconductor layer 310 via at least one via (e.g., via 382) in the gate insulating layer, the first insulating layer, and the second insulating layer.

[0101] As shown in FIG2-7 , one end of the connection structure 341 is connected to the drain region of the corresponding threshold compensation transistor T3 in the active semiconductor layer 310 through at least one via (e.g., via 384) in the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the connection structure 341 is connected to the gate of the driving transistor T1 in the first conductive layer 320 (i.e., the second plate CC2 of the capacitor C) through at least one via (e.g., via 385) in the first insulating layer and the second insulating layer. One end of the connection portion 342 is connected to the reset power signal line Init1 through a via (e.g., via 386) in the second insulating layer. The other end of the connection portion 342 is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310 through at least one via (e.g., via 387) in the gate insulating layer, the first insulating layer, and the second insulating layer. The first sub-electrode connection structure 343 is connected to the drain region of the second light emission control transistor T5 in the active semiconductor layer 310 through at least one via (e.g., via 352) in the gate insulating layer, the first insulating layer, and the second insulating layer. It should be noted that the source region and the drain region of the transistor used in the embodiments of the present disclosure can be structurally identical, so there is no structural difference between the source region and the drain region, and therefore the two can be interchangeable as needed.

[0102] For example, as shown in FIG. 2-7 , the first power signal line VDD1 is connected to the first plate CC1 of the capacitor C in the second conductive layer 330 through at least one via (eg, via 3832 ) in the second insulating layer between the second conductive layer 330 and the source / drain metal layer 340 .

[0103] For example, as shown in FIG2-7 , the shielding line 344 extends along the second direction X, and its orthographic projection on the substrate is located between the orthographic projection of the drive transistor and the orthographic projection of the data line on the substrate. For example, the shielding line in the pixel circuit of the first color sub-pixel can reduce the impact of the signal transmitted on the data line in the pixel circuit of the second color sub-pixel on the performance of the threshold compensation transistor T3 of the first color sub-pixel, thereby reducing the impact of the coupling between the gate of the drive transistor of the first color sub-pixel and the data line of the second color sub-pixel, thereby alleviating crosstalk problems.

[0104] For example, as shown in Figure 2-7, the shielding line 344 is connected to the reset power signal line Init1 through at least one via (such as via 332) in the second insulating layer. In addition to making the shielding line have a fixed potential, it also makes the voltage of the initialization signal transmitted on the reset power signal line more stable, which is more conducive to the working performance of the pixel driving circuit.

[0105] For example, as shown in FIG2-7 , shielding line 344 is electrically connected to a reset power signal line, so that the shielding line has a fixed potential. Shielding line 344 can be electrically connected to two reset power signal lines Init1 extending along the Y direction, with these two reset power signal lines Init1 located on either side of shielding line 344 along the X direction. For example, these two reset power signal lines correspond to the nth row of pixel circuits and the n+1th row of pixel circuits, respectively.

[0106] For example, the shielding line 344 in the same column may be a whole shielding line, which includes a plurality of sub-portions located between two adjacent reset power signal lines, and each sub-portion is located in each pixel circuit area of ​​the column.

[0107] For example, in addition to coupling the shield line 344 to the reset power signal line, the shield line 344 may also be coupled to the first power signal line so that the shield line 344 has the same fixed potential as the power signal transmitted by the first power signal line.

[0108] For example, the orthographic projection of the shielding line 344 on the substrate is located between the orthographic projection of the threshold compensation transistor T3 on the substrate and the orthographic projection of the data line Vd on the substrate, so that the shielding line 344 can reduce the impact of the signal changes transmitted on the data line on the performance of the threshold compensation transistor T3, thereby reducing the impact of the coupling between the gate of the driving transistor and the data signal line Vd(n+1), solving the problem of vertical crosstalk, and enabling the display substrate to obtain better display effects when used for display.

[0109] For example, the orthographic projection of the shielding line 344 on the substrate can be located between the orthographic projection of the connecting structure 341 on the substrate and the orthographic projection of the data line on the substrate; the orthographic projection of the shielding line 344 on the substrate is located between the orthographic projection of the driving transistor T1 on the substrate and the orthographic projection of the data line on the substrate.

[0110] This arrangement effectively reduces the first crosstalk between the data line and the threshold compensation transistor, as well as the second crosstalk between the data line and the connection structure, thereby reducing the indirect crosstalk to the drive transistor caused by the first and second crosstalk. Furthermore, this arrangement also reduces the direct crosstalk between the data line and the drive transistor, thereby better ensuring the operating performance of the display substrate.

[0111] For example, the shielding line 344 is not limited to the above-described configuration. The shielding line 344 can also be coupled only to the reset power signal line corresponding to the nth row of pixel circuits, or only to the reset power signal line corresponding to the (n+1)th row of pixel circuits. Furthermore, the extension length of the shielding line 344 in the second direction X can also be set according to actual needs.

[0112] For example, the pixel circuit of each color sub-pixel further includes a light shielding portion S, which is disposed on a different layer from the shielding line 344, and whose orthographic projection on the substrate overlaps with the orthographic projection of the shielding line 344. The shielding line 344 is connected to the light shielding portion S in the second conductive layer 330 via a via 331 in the second insulating layer, giving the light shielding portion S a fixed potential. This effectively reduces coupling between the threshold compensation transistor T3 and other nearby conductive patterns, thereby ensuring more stable operating performance of the display substrate.

[0113] For example, the light shielding portion S overlaps with the active semiconductor layer 310 between the two gates of the threshold compensation transistor T3 to prevent the active semiconductor layer 310 between the two gates from being illuminated by light and changing its characteristics, such as preventing the voltage of the active semiconductor layer from changing, thereby preventing crosstalk.

[0114] This example schematically shows that the shading portion is connected to the shielding line, but is not limited thereto, and the two may also be disconnected.

[0115] For example, as shown in Figure 2-7, the second power signal line VDD3 is connected to the first power signal line VDD1 through at least one via 351 in the third insulating layer and the fourth insulating layer, and the second sub-electrode connection structure 353 is connected to the first sub-electrode connection structure 343 through the via 354 in the third insulating layer and the fourth insulating layer.

[0116] For example, the third insulating layer may be a passivation layer, the fourth insulating layer may be a planarization layer, the third insulating layer is located between the fourth insulating layer and the base substrate, and the fourth insulating layer may be an organic layer thicker than inorganic layers such as the passivation layer.

[0117] For example, via 351 and via 354 are both nested vias, that is, via 351 includes a first via in the third insulating layer and a second via in the fourth insulating layer, the first via in the third insulating layer is opposite to the second via in the fourth insulating layer, and the orthographic projection of the second via in the fourth insulating layer on the base substrate is located within the orthographic projection of the first via in the third insulating layer on the base substrate.

[0118] For example, the second power signal line VDD3 is distributed in a grid pattern, and the orthographic projection of the second sub-power line VDD32 of the second power signal line VDD3 extending along the X direction on the base substrate roughly coincides with the orthographic projection of the first power signal line VDD1 on the base substrate, or the orthographic projection of the first power signal line VDD1 on the base substrate is located within the orthographic projection of the second sub-power line VDD32 on the base substrate. Moreover, the electrical connection between the second power signal line VDD3 and the first power signal line VDD1 can reduce the voltage drop of the first power signal line VDD1, thereby improving the uniformity of the display device.

[0119] For example, the second power signal line VDD3 may be made of the same material as the source / drain metal layer.

[0120] For example, as shown in Figure 5, the first sub-electrode connection structures 343 of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are all block structures. The first electrode of each color sub-pixel formed subsequently will be connected to the corresponding second sub-electrode connection structure 353 through a via hole to achieve connection with the drain region of the second light-emitting control transistor T5.

[0121] This embodiment includes but is not limited to this. The position of the second sub-electrode connection structure in each color sub-pixel is determined according to the arrangement rule of the organic light-emitting elements and the position of the light-emitting area.

[0122] For example, FIG8 is a schematic diagram of a partial cross-sectional structure of the display substrate in FIG7 , wherein FIG7 illustrates only a portion of the film layers in FIG8 . As shown in FIG7 and FIG8 , a gate insulating layer 103 is provided on the side of the second electrode (e.g., drain electrode T5d) of the second emission control transistor T5 in the active semiconductor layer in the pixel circuit of the second color sub-pixel 120 away from the substrate 100. A light emission control signal line EM1 is provided on the side of the gate insulating layer 103 away from the substrate 100. A first insulating layer 104 is provided on the side of the light emission control signal line EM1 away from the substrate 100. A third power supply signal line VDD2 is provided on the side of the first insulating layer 104 away from the substrate 100. A second insulating layer 105 is provided on the side of the third power supply signal line VDD2 away from the substrate 100. A first sub-electrode connection structure 343 is provided on the side of the second insulating layer 105 away from the substrate 100. The first sub-electrode connection structure 343 of the second color sub-pixel 120 is connected to the second electrode T5d of the second emission control transistor T5 in the active semiconductor layer 310 through a via 352 in the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105. The first sub-electrode connection structure 343 overlaps both the third power signal line VDD2 and the emission control signal line EM1. The third insulating layer 106 and the fourth insulating layer 107 are sequentially provided on the side of the first sub-electrode connection structure 343 facing away from the base substrate 100. The second sub-electrode connection structure 353 and the second power signal line VDD3 are provided on the side of the fourth insulating layer 107 facing away from the base substrate 100. The second power signal line VDD3 overlaps the third power signal line VDD2. The second sub-electrode connection structure 353 is connected to the first sub-electrode connection structure 343 through nested vias 354 in the third insulating layer 106 and the fourth insulating layer 107, thereby connecting to the second emission control transistor.

[0123] For example, as shown in Figure 8, the data line Vd is connected to the source T2s of the data writing transistor T2 through the via 381 in the gate insulating layer 103, the first insulating layer 104 and the second insulating layer 105; one end of the connecting structure 341 is connected to the drain T3d of the threshold compensation transistor T3 through the via 384 in the gate insulating layer 103, the first insulating layer 104 and the second insulating layer 105, and the other end of the connecting structure 341 is connected to the gate of the driving transistor T1 (that is, the second plate CC2 of the capacitor C) through the via 385 in the first insulating layer 104 and the second insulating layer 105; the channel T1c of the driving transistor T1 is located on the side of its gate facing the base substrate 100, and does not overlap with the via 385, and the source T1d of the driving transistor T1 overlaps with its gate and the first plate CC1 of the capacitor C.

[0124] For example, Figure 9 is a schematic diagram of a partial cross-sectional structure of the display substrate shown in Figure 7 , where Figure 7 only illustrates a portion of the film layers shown in Figure 9 . As shown in Figures 7-9 , the difference between the first color sub-pixel 110 and the second color sub-pixel 120 is that the orthographic projection of the second sub-electrode connection structure 353 in the second color sub-pixel 120 on the substrate 100 does not overlap with the orthographic projection of the second electrode T5d of its second emission control transistor T5 on the substrate 100, while the orthographic projection of the second sub-electrode connection structure 353 in the first color sub-pixel 130 on the substrate 100 does overlap with the orthographic projection of the second electrode T5d of its second emission control transistor T5 on the substrate 100. In the first color sub-pixel 110, the first sub-electrode connection structure 343 does not overlap with either the third power supply signal line VDD2 or the emission control signal line EM1. In the first color sub-pixel 110, the channel T1c of the driving transistor T1 is located on the side of its gate facing the substrate 100 and overlaps with the via 385. It can be seen from this that the channel width of the driving transistor of the first color sub-pixel is greater than the channel width of the second color sub-pixel.

[0125] For example, as shown in Figure 2-7, in the second direction X, the scanning signal line Ga1, the reset control signal line Rst1 and the reset power signal line Init1 are all located on the first side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel, and the light-emitting control signal line EM1 is located on the second side of the driving transistor T1 of the pixel circuit of the first color sub-pixel.

[0126] For example, the scan signal line Ga1 , the reset control signal line Rst1 , the light emitting control signal line EM1 , and the reset power signal line Init1 all extend along the first direction Y, and the data line Vd extends along the second direction X.

[0127] It should be noted that the positional arrangement relationship of the driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit in each pixel circuit is not limited to the examples shown in Figures 2-7. According to actual application requirements, the positions of the driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit can be specifically set.

[0128] For example, as shown in Figures 2-9, the first electrode 11 of the first color sub-pixel is connected to the second sub-electrode connection structure 353 through a via hole (not shown) in the fifth insulating layer, thereby connecting to the drain region of the second emission control transistor T5. Similarly, the first electrode 13 of the organic light-emitting element of the third color sub-pixel is connected to the second sub-electrode connection structure 353 through a via hole (not shown) in the fifth insulating layer, thereby connecting to the drain region of the second emission control transistor T5. The first electrode 12 of the second color sub-pixel is connected to the second sub-electrode connection structure 353 through a via hole in the fifth insulating layer, and then connected to the second sub-electrode connection structure 343, thereby connecting to the drain region of the second emission control transistor T5.

[0129] The embodiment of the present application provides a new pixel arrangement, which will be introduced below. As shown in Figure 7, the orthographic projection of the pixel opening 21 of the first color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel 301 of the driving transistor of the first color sub-pixel on the substrate substrate, the orthographic projection of the pixel opening 22 of the second color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel 302 of the driving transistor of the second color sub-pixel on the substrate substrate, and the orthographic projection of the pixel opening 23 of the third color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel 303 of the driving transistor of the third color sub-pixel on the substrate substrate. The above-mentioned pixel arrangement is different from the pixel arrangement in the existing display panel.

[0130] In one embodiment, the plurality of sub-pixels are divided into a plurality of pixel groups, each of which includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. At least one of the pixel groups includes two rows of sub-pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction includes alternating first color sub-pixels and third color sub-pixels, and another row of sub-pixels arranged along the first direction includes the second color sub-pixels. The row of sub-pixels arranged along the first direction means that the organic light-emitting elements of the sub-pixels are arranged along the first direction.

[0131] In one embodiment, a plurality of sub-pixels can be divided into a plurality of pixel groups based on the first electrode or the pixel opening of the sub-pixel. In other embodiments, the pixel groups can also be divided based on the pixel circuit of the sub-pixel. Figure 7A shows a schematic diagram of a portion of the film layer of a plurality of pixel groups 101 in the display substrate of Figure 7 , and illustrates the arrangement of the pixel openings of the plurality of pixel groups 101. Referring to Figure 7A , the pixel openings of the same pixel group 101 are divided into two rows, wherein one row of first electrodes arranged along the first direction includes pixel openings 21 of first color sub-pixels and pixel openings 23 of third color sub-pixels arranged alternately; the other row of first electrodes arranged along the first direction includes pixel openings 22 of second color sub-pixels. In the embodiment shown in Figure 7A , the pixel circuits of the same pixel group 101 are located in the same row. In other embodiments, the pixel circuits of the same pixel group 101 may also be located in different rows.

[0132] In one embodiment, referring to Figure 7, any one of the orthographic projections of the pixel opening 21 of the first color sub-pixel on the substrate, the orthographic projections of the pixel opening 22 of the second color sub-pixel on the substrate, and the orthographic projections of the pixel opening 23 of the third color sub-pixel on the substrate, does not overlap with any one of the orthographic projections of the channel 301 of the driving transistor of the first color sub-pixel on the substrate, the orthographic projections of the channel 302 of the driving transistor of the second color sub-pixel on the substrate, and the orthographic projections of the channel 303 of the driving transistor of the third color sub-pixel on the substrate.

[0133] Existing display panels have a shorter lifespan when used at high temperatures and exhibit color shift during display. The inventors have discovered that this problem occurs because the current of the blue sub-pixel's drive transistor is higher when the display panel is displaying. For example, the current of the blue sub-pixel's drive transistor is 2.15 times that of the green sub-pixel's drive transistor. The channel of the blue sub-pixel's drive transistor overlaps with the organic light-emitting element of the green sub-pixel, causing the temperature of the green sub-pixel's organic light-emitting element to rise significantly. This in turn causes the green sub-pixel to decay too quickly, shortening its lifespan. Furthermore, the brightness decay rates of sub-pixels of different colors vary significantly, causing color shift in the displayed image. The above-mentioned sub-pixel arrangement can prevent the driving transistor of the second color sub-pixel from causing the temperature of the organic light-emitting element of the first color sub-pixel or the third color sub-pixel to rise too much, thereby causing the brightness of the organic light-emitting element to decay too quickly and shorten the lifespan. This helps to improve the service life of the sub-pixels, and can reduce the difference in brightness decay speed of sub-pixels of different colors, thereby improving the color deviation problem of the display substrate. Since the pixel opening of each color sub-pixel and the channel of the driving transistor do not overlap, the temperature of the organic light-emitting element of each color sub-pixel can be kept low, which further helps to improve the service life and color deviation problem of the display panel.

[0134] In one embodiment, in at least one pixel group, the distance between the channel of the driving transistor of the sub-pixel and the scanning signal line in the second direction X is in the range of 1 μm to 50 μm. Specifically, the distance between the channel 301 of the driving transistor of the first color sub-pixel and the scanning signal line Ga1 in the second direction is in the range of 1 μm to 50 μm; the distance between the channel 302 of the driving transistor of the second color sub-pixel and the scanning signal line Ga1 in the second direction is in the range of 1 μm to 50 μm; and the distance between the channel 303 of the driving transistor of the third color sub-pixel and the scanning signal line Ga1 in the second direction is in the range of 1 μm to 50 μm.

[0135] Furthermore, in at least one pixel group, a distance between a channel of the sub-pixel driving transistor and the scanning signal line in the second direction ranges from 10 μm to 50 μm. For example, the distance between the channel of the sub-pixel driving transistor and the scanning signal line in the second direction is 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.

[0136] In one embodiment, as shown in FIG7 , in at least one pixel group, the orthogonal projection of the pixel opening corresponding to each sub-pixel on the substrate substrate does not overlap with the orthogonal projection of the gate of the driving transistor of any sub-pixel on the substrate substrate; or, the orthogonal projection of the pixel opening corresponding to each sub-pixel on the substrate substrate overlaps with the orthogonal projection of the gate of the driving transistor of any sub-pixel on the substrate substrate, and the ratio of the area of ​​the overlapping area to the area of ​​the gate is no more than 10%. Since when the temperature of the driving transistor rises, the heat generated by it is mainly transferred to the organic light-emitting element of the sub-pixel through the gate. When the orthogonal projection of the pixel opening corresponding to each sub-pixel on the substrate substrate does not overlap with the orthogonal projection of the gate of the driving transistor of any sub-pixel on the substrate substrate, or when the orthogonal projection of the pixel opening corresponding to each sub-pixel on the substrate substrate overlaps with the orthogonal projection of the gate of the driving transistor of any sub-pixel on the substrate substrate is small, the amount of heat generated by the driving transistor transferred to the organic light-emitting element can be effectively reduced, thereby avoiding excessive temperature rise of the organic light-emitting element, which may lead to rapid degradation of the organic light-emitting element and shortened service life, thereby helping to extend the service life of the sub-pixel and improve the basic color shift problem of the display.

[0137] Furthermore, in the embodiment shown in FIG7 , the distance between the gate of the sub-pixel driving transistor and the scanning signal line Ga1 in the second direction ranges from 2 μm to 10 μm. The distance between the gate of the sub-pixel driving transistor and the scanning signal line Ga1 in the second direction can be, for example, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, etc.

[0138] In one embodiment, referring to FIG10 , in at least one pixel group, the orthogonal projection of the scan signal line Ga1 in the second direction X overlaps with the orthogonal projection of the gate of the subpixel's drive transistor in the second direction X, where the second direction X is perpendicular to the first direction Y. The orthogonal projections of the scan signal line and the gate of the drive transistor in the second direction X refer to their orthogonal projections on a line extending along the second direction X. As shown in FIG10 , the orthogonal projection of the scan signal line Ga1 in the second direction X overlaps with the orthogonal projection of the gate 321 of the drive transistor of the first color subpixel in the second direction X; the orthogonal projection of the scan signal line Ga1 in the second direction X overlaps with the orthogonal projection of the gate 322 of the drive transistor of the second color subpixel in the second direction X; and the orthogonal projection of the scan signal line Ga1 in the second direction X overlaps with the orthogonal projection of the gate 323 of the drive transistor of the third color subpixel in the second direction X. This configuration allows for a more compact structural arrangement within the display substrate, helping to increase the density of subpixels within the display substrate.

[0139] In one embodiment, as shown in FIG10 , the scan signal line Ga1 includes a scan signal line main portion Ga11 and a protrusion P protruding from one side of the scan signal line main portion Ga11. The scan signal line main portion Ga11 extends entirely along a first direction Y, and the protrusion P extends along a second direction X. The threshold compensation transistor T3 of the sub-pixel includes a first gate and a second gate. In the threshold compensation transistor, the first gate is the portion of the scan signal line main portion Ga11 that overlaps with the orthographic projection of the active semiconductor layer on the base substrate, and the second gate is the portion of the protrusion P that overlaps with the orthographic projection of the active semiconductor layer on the base substrate.

[0140] Furthermore, as shown in Figures 10 and 10A, the scan signal line main body Ga11 includes a first sub-scan line 324, a second sub-scan line 326, and a connecting portion 325. The first sub-scan line 324 and the second sub-scan line 326 are connected by the connecting portion 325. The first sub-scan line 324 and the second sub-scan line 326 extend generally along the first direction Y. Within the same scan signal line, the protrusion P and the connecting portion 325 are located on either side of the first sub-scan line 324 in the first direction. In the illustrated embodiment, the protrusion P is located on the side of the first sub-scan line 324 closer to the first reset control signal line Rst1, and the connecting portion 325 is located on the side of the first sub-scan line 324 facing away from the first reset control signal line Rst1. In other embodiments, the connecting portion 325 may be located on the side of the first sub-scan line 324 closer to the first reset control signal line Rst1, and the protrusion P may be located on the side of the first sub-scan line 324 facing away from the first reset control signal line Rst1.

[0141] The first sub-scan line 324 is connected to the pixel circuit of the first color sub-pixel, and the second sub-scan line 326 is connected to the pixel circuit of the second color sub-pixel. The extending direction of part of the connecting portion 325 intersects the extending direction of the first sub-scan line 324. In the threshold compensation transistor, the first gate is the portion of the connecting portion 325 that overlaps with the orthographic projection of the active semiconductor layer on the base substrate.

[0142] Furthermore, the orthographic projection of the connecting portion 325 in the second direction X overlaps with the orthographic projection of the gate of the driving transistor of the sub-pixel in the second direction X. As shown in FIG10 , the orthographic projection of the connecting portion 325 in the second direction X overlaps with the orthographic projection of the gate 321 of the first color sub-pixel in the second direction X, the orthographic projection of the gate 322 of the second color sub-pixel in the second direction X, and the orthographic projection of the gate 323 of the third color sub-pixel in the second direction X.

[0143] In one embodiment, as shown in Figures 10 and 10A, the connection portion 325 includes a first sub-connection portion 3251, a second sub-connection portion 3252, and a third sub-connection portion 3253, which are sequentially connected. The first sub-connection portion 3251 and the third sub-connection portion 3253 intersect with the extension direction of the first sub-scan line 324. The second sub-connection portion 3252 and the first sub-scan line 324 extend in the same direction. The third sub-connection portion 3253 is connected to the first sub-scan line 324, and the first sub-connection portion 3251 is connected to the second sub-scan line 326. In the threshold compensation transistor, the first gate is the portion of the second sub-connection portion 3252 that overlaps with the orthographic projection of the active semiconductor layer on the substrate.

[0144] In one embodiment, as shown in Figures 2 and 2A, the active semiconductor layer 310 includes a first segment 311, a second segment 312, a third segment 313, and a fourth segment 314, which are sequentially connected. The second segment 312, the fourth segment 314, and the main portion of the scan signal line Ga11 extend along the first direction Y, while the first segment 311 and the third segment 313 extend along the second direction X. The second gate of the threshold compensation transistor T3 is the portion of the protrusion P that overlaps with the orthographic projection of the fourth segment 314 on the substrate. The gate of the reset transistor includes the portion of the reset control signal line Rst1 that overlaps with the orthographic projection of the first segment 311 on the substrate. Specifically, the first reset transistor T6 includes two gates, one of which includes the portion of the reset control signal line Rst1 that overlaps with the orthographic projection of the first segment 311 on the substrate. This configuration facilitates forming a dual-gate structure for the threshold compensation transistor T3 and the first reset transistor T6.

[0145] Furthermore, as shown in FIG10 , in at least one pixel group, the orthographic projection of the gate electrode of the driving transistor of at least one sub-pixel on the substrate overlaps with the orthographic projection of its corresponding pixel opening on the substrate. Specifically, the orthographic projection of the gate electrode 321 of the driving transistor of the first color sub-pixel on the substrate overlaps with the orthographic projection of its corresponding pixel opening 21 on the substrate; and the orthographic projection of the gate electrode 323 of the driving transistor of the third color sub-pixel on the substrate overlaps with the orthographic projection of its corresponding pixel opening 23 on the substrate.

[0146] Furthermore, at least the portion where the orthographic projection of the gate of the sub-pixel overlaps the corresponding pixel opening on the substrate has a size in the second direction X ranging from 0 to 30 μm. In the embodiment shown in FIG10 , the portions where the orthographic projection of the gate of the first color sub-pixel, the gate of the second color sub-pixel, and the gate of the third color sub-pixel overlaps the corresponding pixel opening on the substrate have a size in the second direction X greater than 0.

[0147] In one embodiment, as shown in FIG11 , the connecting structure 341 includes a first portion 3411 and a second portion 3412 connected to the first portion 3411. The orthographic projection of the first portion 3411 on the substrate and the orthographic projection of the protrusion P on the substrate are located on the same side as the orthographic projection of the scanning signal line main portion Ga11 on the substrate. The length of the first portion 3411 in the second direction X is greater than the length of the protrusion P in the second direction X. In the second direction X, the orthographic projection of the scanning signal line main portion Ga11 on the substrate includes two opposite sides (e.g., an upper side and a lower side). The orthographic projection of the first portion 3411 on the substrate and the orthographic projection of the protrusion P on the substrate are located on the same side as the orthographic projection of the scanning signal line main portion Ga11 on the substrate means that the orthographic projection of the first portion 3411 on the substrate and the orthographic projection of the protrusion P on the substrate are both located above or below the orthographic projection of the scanning signal line main portion Ga11 on the substrate. In the illustrated embodiment, the orthographic projection of the first portion 3411 on the substrate and the orthographic projection of the protrusion P on the substrate are both located above the orthographic projection of the scanning signal line main portion Ga11 on the substrate. This arrangement facilitates connection of the end of the first portion 3411 to the gate of the driving transistor T1.

[0148] Furthermore, the size of the connection structure 341 in the second direction X ranges from 35 μm to 70 μm. This configuration ensures that both ends of the connection structure 341 are electrically connected to the gate of the driving transistor T1 in the first conductive layer 320 and the source and drain regions of the threshold compensation transistor T3 in the active semiconductor layer 310. In some embodiments, the size of the connection structure 341 in the second direction X ranges from 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc.

[0149] In one embodiment, as shown in Figures 7 and 10 , the orthographic projection of the first electrode 12 of at least one second-color sub-pixel on the substrate overlaps with the orthographic projection of the reset control signal line Rst1 and the orthographic projection of the scan signal line Ga1 on the substrate. In some embodiments, the orthographic projection of the first electrode 12 of each second-color sub-pixel of the display panel on the substrate overlaps with the orthographic projection of a reset control signal line Rst1 and the orthographic projection of a scan signal line Ga1 on the substrate. This configuration helps improve the pixel density of the display substrate.

[0150] In one embodiment, the size of the first color subpixel in the first direction Y ranges from 35 μm to 110 μm, and the size in the second direction X ranges from 20 μm to 60 μm; the size of the second color subpixel in the first direction Y ranges from 35 μm to 120 μm, and the size in the second direction X ranges from 20 μm to 80 μm; the size of the third color subpixel in the first direction Y ranges from 35 μm to 70 μm, and the size in the second direction X ranges from 20 μm to 60 μm. The size of a subpixel in the first direction refers to its maximum dimension in the first direction Y, and the maximum dimension of a subpixel in the first direction Y refers to the maximum dimension in the first direction Y of the overlap between the orthographic projection of the subpixel's pixel opening on the substrate and the orthographic projection of its first electrode on the substrate. The size of a subpixel in the second direction X refers to its maximum dimension in the second direction X, and the maximum dimension of a subpixel in the second direction X refers to the maximum dimension in the first direction Y of the overlap between the orthographic projection of the subpixel's pixel opening on the substrate and the orthographic projection of its first electrode on the substrate.

[0151] In some exemplary embodiments, the size of the first color sub-pixel in the first direction Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, 95 μm, 105 μm, 110 μm, etc., and the size of the first color sub-pixel in the second direction X is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, etc.; the size of the second color sub-pixel in the first direction Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, 95 μm, The size of the second color sub-pixel in the second direction X is, for example, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, etc.; the size range of the third color sub-pixel in the first direction Y is 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, and the size of the third color sub-pixel in the second direction X is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, etc.

[0152] Furthermore, the area of ​​the second color sub-pixel is larger than the area of ​​the first color sub-pixel, and the area of ​​the first color sub-pixel is larger than the area of ​​the third color sub-pixel. This configuration helps to reduce the difference in the lifespan of each color sub-pixel.

[0153] The embodiment of the present application also provides another new pixel arrangement. Referring to Figures 12 to 16, the orthographic projection of the pixel opening of at least one sub-pixel on the substrate overlaps with the orthographic projection of the channel of its driving transistor on the substrate, the orthographic projection of the pixel opening 22 of at least one second-color sub-pixel in the first direction overlaps with the orthographic projection of the pixel opening 21 of the first color sub-pixel in the first direction Y, and the orthographic projection of the pixel opening 23 of the third color sub-pixel in the first direction Y, and the orthographic projection of the pixel opening 22 of at least one second-color sub-pixel in the second direction X does not overlap with the orthographic projection of the pixel opening 21 of the first color sub-pixel in the second direction X, and the orthographic projection of the pixel opening 23 of the third color sub-pixel in the second direction X, and the first direction Y intersects with the second direction X. The pixel arrangement provided by the embodiment of the present application is different from the pixel arrangement in the existing display panel.

[0154] The orthographic projection of the pixel opening in the first direction Y refers to the orthographic projection of the pixel opening on a straight line extending along the first direction Y.

[0155] In one embodiment, as shown in Figure 16, the orthographic projection of the pixel opening 21 of the first color sub-pixel on the substrate overlaps with the orthographic projection of the channel 301 of its driving transistor on the substrate, the orthographic projection of the pixel opening 23 of the third color sub-pixel on the substrate overlaps with the orthographic projection of the channel 303 of its driving transistor on the substrate, and the orthographic projection of the pixel opening 22 of the second color sub-pixel on the substrate overlaps with the orthographic projection of the channel 302 of its driving transistor on the substrate.

[0156] Further, as shown in Figure 16, the orthographic projection of the channel 301 of the driving transistor of the first color sub-pixel on the substrate falls within the orthographic projection of the pixel opening 21 on the substrate, the orthographic projection of the channel 302 of the driving transistor of the second color sub-pixel on the substrate falls within the orthographic projection of the pixel opening 22 on the substrate, and the orthographic projection of the channel 303 of the driving transistor of the third color sub-pixel on the substrate falls within the orthographic projection of the pixel opening 23 on the substrate.

[0157] In other embodiments, among the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel, only one color sub-pixel or two color sub-pixels have their pixel openings overlapped with the orthographic projections of their driving transistor channels on the substrate.

[0158] In one embodiment, as shown in FIG16 , the orthogonal projection of the pixel opening 21 of the first color sub-pixel on the substrate does not overlap with the orthogonal projection of the channel 302 of the driving transistor of the second color sub-pixel on the substrate, nor does the orthogonal projection of the channel 303 of the driving transistor of the third color sub-pixel on the substrate; the orthogonal projection of the pixel opening 22 of the second color sub-pixel on the substrate does not overlap with the orthogonal projection of the channel 301 of the driving transistor of the first color sub-pixel on the substrate, nor does the orthogonal projection of the channel 303 of the driving transistor of the third color sub-pixel on the substrate; the orthogonal projection of the pixel opening 23 of the third color sub-pixel on the substrate does not overlap with the orthogonal projection of the channel 301 of the driving transistor of the first color sub-pixel on the substrate, nor does the orthogonal projection of the channel 302 of the driving transistor of the second color sub-pixel on the substrate. In this configuration, the orthogonal projection of the channel of the driving transistor of each sub-pixel on the substrate only overlaps with the orthogonal projection of its pixel opening on the substrate, and does not overlap with the orthogonal projections of the pixel openings of other sub-pixels on the substrate. This is helpful to reduce the difference in brightness decay speed of the organic light emitting elements of each sub-pixel, thereby improving the color shift problem of the display substrate.

[0159] In another embodiment of the present application, the orthographic projection of the channel of the driving transistor of the first color sub-pixel and the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the substrate are located within the orthographic projection of the pixel opening corresponding to the second color sub-pixel on the substrate; and the orthographic projection of the channel of the driving transistor of the third color on the substrate is located within the orthographic projection of the pixel opening corresponding to the third color sub-pixel on the substrate. This arrangement can avoid the problem that the driving transistor of the second color sub-pixel with a larger driving current causes the temperature of the organic light-emitting element of the first color sub-pixel to rise excessively, thereby causing the brightness of the first color sub-pixel to decay too quickly and shorten its lifespan. It can also avoid a large difference in the brightness decay rate of the first color sub-pixel from the brightness decay rates of the second color sub-pixel and the third color sub-pixel, thereby improving the color cast phenomenon of the display substrate.

[0160] In yet another embodiment of the present application, the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the substrate does not overlap with the orthographic projection of the pixel opening corresponding to the first color sub-pixel, the orthographic projection of the pixel opening corresponding to the second color sub-pixel on the substrate, and the orthographic projection of the pixel opening corresponding to the third color sub-pixel on the substrate. With this arrangement, the driving transistor of the second color sub-pixel, which has a larger driving current, has a smaller impact on the organic light-emitting elements of each color sub-pixel, further helping to improve the service life of the display substrate and reduce color shift issues of the display substrate.

[0161] Furthermore, the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the substrate and the orthographic projection of the channel of the driving transistor of the third color on the substrate are both located within the orthographic projection of the pixel opening corresponding to the second color sub-pixel on the substrate. Alternatively, the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the substrate is located within the orthographic projection of the pixel opening corresponding to the second color sub-pixel on the substrate, and the orthographic projection of the channel of the driving transistor of the third color on the substrate is located within the orthographic projection of the pixel opening corresponding to the third color sub-pixel on the substrate.

[0162] In one embodiment, the multiple sub-pixels are divided into multiple pixel groups, each of the pixel groups includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; at least one of the pixel groups includes two rows of sub-pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction includes the first color sub-pixels and the third color sub-pixels arranged alternately, and the other row of sub-pixels arranged along the first direction includes the second color sub-pixels.

[0163] In one embodiment, as shown in FIG16 , in at least one pixel group, in the second direction X, the distance between the channel 302 of the driving transistor of the second color sub-pixel and the scan signal line Ga1 is different from the distance between the channel 301 of the driving transistor of the first color sub-pixel and the scan signal line Ga1. Furthermore, in the second direction X, the distance between the channel 303 of the driving transistor of the third color sub-pixel and the scan signal line Ga1 can be substantially the same as the distance between the channel 301 of the driving transistor of the first color sub-pixel and the scan signal line Ga1. This configuration further helps prevent the orthographic projection of the channel 302 of the driving transistor of the second color sub-pixel from overlapping with the pixel opening of the first color sub-pixel on the substrate.

[0164] Furthermore, in at least one pixel group, in the second direction X, the distance between the channel 302 of the driving transistor of the second color sub-pixel and the scanning signal line Ga1 is greater than the distance between the channel 301 of the driving transistor of the first color sub-pixel and the scanning signal line Ga1. This arrangement helps to prevent the problem of heat generated by the driving transistor of the second color sub-pixel causing the brightness of the second color sub-pixel to decay too quickly and shorten the lifespan of the second color sub-pixel.

[0165] Furthermore, in at least one pixel group, in the second direction X, the distance between the channel 302 of the driving transistor of the second color sub-pixel and the scanning signal line Ga1 ranges from 1 μm to 60 μm, the distance between the channel 301 of the driving transistor of the first color sub-pixel and the scanning signal line Ga1 ranges from 1 μm to 50 μm, and the distance between the channel 301 of the driving transistor of the third color sub-pixel and the scanning signal line Ga1 ranges from 1 μm to 50 μm. In the second direction X, the distance from the channel 302 of the driving transistor of the second color sub-pixel to the scanning signal line Ga1 is, for example, 1μm, 10μm, 20μm, 30μm, 40μm, 50μm, or 60μm, the distance from the channel 301 of the driving transistor of the first color sub-pixel to the scanning signal line Ga1 and the distance from the channel 301 of the driving transistor of the third color sub-pixel to the scanning signal line Ga1 are, for example, 1μm, 10μm, 20μm, 30μm, 40μm, 50μm, etc.

[0166] In one embodiment, referring to FIG13 , the area of ​​the second plate CC12 of the second color sub-pixel is larger than the area of ​​the second plate CC11 of the first color sub-pixel, and the area of ​​the second plate CC12 of the second color sub-pixel is larger than the area of ​​the second plate CC13 of the third color sub-pixel. Generally, the channel width-to-length ratio of the driving transistor of the second color sub-pixel is larger than the channel width-to-length ratio of the driving transistor of the first color sub-pixel or the second color sub-pixel to prevent insufficient brightness of the second color when the white light displayed by the display substrate is at the highest grayscale, thereby causing the white balance color coordinates of the white light at the highest grayscale to deviate from the designed value. By setting the area of ​​the second plate CC12 of the second color sub-pixel to be larger than the area of ​​the second plate CC11 of the first color sub-pixel and the area of ​​the second plate CC13 of the third color sub-pixel, it is ensured that the second plate CC12 of the second color sub-pixel covers the channel of its driving transistor.

[0167] In one embodiment, the areas of the electrode connection structures of at least two of the sub-pixels are different.

[0168] 14 and 15 , the electrode connection structure includes a first sub-electrode connection structure 343 and a second sub-electrode connection structure 353. The areas of the first sub-electrode connection structure 343 and / or the second sub-electrode connection structure 353 of at least two sub-pixels are different.

[0169] Further, as shown in Figure 15, the area of ​​the second sub-electrode connection structure 3532 of the second color sub-pixel is smaller than the area of ​​the second sub-electrode connection structure 3531 of the first color sub-pixel, and the area of ​​the second sub-electrode connection structure 3532 of the second color sub-pixel is smaller than the area of ​​the second sub-electrode connection structure 3533 of the third color sub-pixel.

[0170] In one embodiment, referring to FIG. 16 , the orthographic projection of the first electrode 12 of at least one second color sub-pixel on the base substrate overlaps with the orthographic projection of the reset control signal line Rst1 on the base substrate and the orthographic projection of the scanning signal line Ga1 on the base substrate.

[0171] In one embodiment, the connecting structure 341 includes a first portion and a second portion connected to the first portion. The orthographic projection of the first portion on the base substrate and the orthographic projection of the protrusion P on the base substrate are located on the same side as the orthographic projection of the scanning signal line main portion Ga11 on the base substrate. The length of the first portion in the second direction X is greater than the length of the protrusion P in the second direction X. This arrangement facilitates connection of the end of the first portion to the gate of the driving transistor T1.

[0172] Furthermore, the size of the connection structure 341 in the second direction X ranges from 35 μm to 70 μm. This configuration ensures that both ends of the connection structure 341 are electrically connected to the gate of the driving transistor T1 in the first conductive layer 320 and the source and drain regions of the threshold compensation transistor T3 in the active semiconductor layer 310. In some embodiments, the size of the connection structure 341 in the second direction X ranges from 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc.

[0173] In one embodiment, the size of the first color subpixel in the first direction Y ranges from 35 μm to 110 μm, and the size in the second direction X ranges from 20 μm to 60 μm; the size of the second color subpixel in the first direction Y ranges from 35 μm to 120 μm, and the size in the second direction X ranges from 20 μm to 80 μm; the size of the third color subpixel in the first direction Y ranges from 35 μm to 70 μm, and the size in the second direction X ranges from 20 μm to 60 μm. The size of a subpixel in the first direction refers to its maximum dimension in the first direction Y, and the maximum dimension of a subpixel in the first direction Y refers to the maximum dimension in the first direction Y of the overlap between the orthographic projection of the subpixel's pixel opening on the substrate and the orthographic projection of its first electrode on the substrate. The size of a subpixel in the second direction X refers to its maximum dimension in the second direction X, and the maximum dimension of a subpixel in the second direction X refers to the maximum dimension in the first direction Y of the overlap between the orthographic projection of the subpixel's pixel opening on the substrate and the orthographic projection of its first electrode on the substrate.

[0174] In some exemplary embodiments, the size of the first color sub-pixel in the first direction Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, 95 μm, 105 μm, 110 μm, etc., and the size of the first color sub-pixel in the second direction X is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, etc.; the size of the second color sub-pixel in the first direction Y is, for example, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, 95 μm, The size of the second color sub-pixel in the second direction X is, for example, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, etc.; the size range of the third color sub-pixel in the first direction Y is 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, and the size of the third color sub-pixel in the second direction X is, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, etc.

[0175] It should be noted that the features described in different embodiments of this application can complement each other if they do not conflict. For example, if they do not conflict, the features of the embodiments shown in Figures 2 to 10 can also have the same features in the embodiment shown in Figure 11 and the embodiment shown in Figures 12 to 16; and the features of the embodiment shown in Figures 12 to 16 can also have the same features in the embodiment shown in Figures 2 to 10.

[0176] An embodiment of the present application further provides a display panel, which includes the display substrate described in any of the above embodiments.

[0177] The display panel may further include a glass cover located on a side of the display substrate facing away from the substrate.

[0178] The embodiment of the present application further provides a display device, which includes the display panel described above. The display device may further include a housing, in which the display panel may be embedded.

[0179] The display device in this embodiment can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, or a car display device.

[0180] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0181] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0182] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that: The display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate; The plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels; the human eye is more sensitive to the first color than to the third color, and the human eye is more sensitive to the third color than to the second color; the sub-pixels include an organic light-emitting element and a pixel circuit for driving the organic light-emitting element; the organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting material located between the first electrode and the second electrode; the first electrode of the sub-pixel is electrically connected to the pixel circuit; and the pixel circuit includes a driving transistor; The display substrate further comprises an active semiconductor layer and a pixel defining layer, wherein the active semiconductor layer comprises a channel and a source / drain region of a driving transistor of each sub-pixel; the pixel defining layer is provided with pixel openings corresponding to the sub-pixels one by one; The orthographic projection of the pixel opening of the first color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the substrate substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the substrate substrate, and the orthographic projection of the pixel opening of the third color sub-pixel on the substrate substrate does not overlap with the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the substrate substrate; or, The orthographic projection of the pixel opening of at least one sub-pixel on the substrate overlaps with the orthographic projection of the channel of its driving transistor on the substrate, the orthographic projection of the pixel opening of at least one second-color sub-pixel in the first direction overlaps with the orthographic projection of the pixel opening of the first color sub-pixel in the first direction and the orthographic projection of the pixel opening of the third color sub-pixel in the first direction, and the orthographic projection of the pixel opening of the second color sub-pixel in the second direction does not overlap with the orthographic projection of the pixel opening of the first color sub-pixel in the second direction and the orthographic projection of the pixel opening of the third color sub-pixel in the second direction, and the first direction intersects with the second direction.

2. The display substrate according to claim 1, wherein: The orthographic projection of the pixel opening of the first color sub-pixel on the substrate overlaps with the orthographic projection of the channel of the driving transistor of the first color sub-pixel on the substrate, the orthographic projection of the pixel opening of the second color sub-pixel on the substrate overlaps with the orthographic projection of the channel of the driving transistor of the second color sub-pixel on the substrate, and the orthographic projection of the pixel opening of the third color sub-pixel on the substrate overlaps with the orthographic projection of the channel of the driving transistor of the third color sub-pixel on the substrate.

3. The display substrate according to claim 1, wherein The multiple sub-pixels are divided into multiple pixel groups, each of the pixel groups includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; at least one of the pixel groups includes two rows of sub-pixels arranged along the first direction, wherein one row of sub-pixels arranged along the first direction includes the first color sub-pixels and the third color sub-pixels arranged alternately, and the other row of sub-pixels arranged along the first direction includes the second color sub-pixels.

4. The display substrate according to claim 3, wherein: In at least one of the pixel groups, an orthographic projection of a pixel opening corresponding to each of the sub-pixels on the substrate does not overlap with an orthographic projection of a gate of a driving transistor of any of the sub-pixels on the substrate, or An orthographic projection of the pixel opening corresponding to each sub-pixel on the substrate overlaps with an orthographic projection of the gate of the driving transistor of any sub-pixel on the substrate, and a ratio of an area of ​​the overlapping area to an area of ​​the gate is no more than 10%.

5. The display substrate according to claim 3, wherein: The display substrate is further provided with a plurality of scanning signal lines extending along the first direction, wherein the scanning signal lines are configured to provide scanning signals to the pixel groups; In at least one pixel group, in the second direction, a distance from a channel of a driving transistor of the second color sub-pixel to the scanning signal line is different from a distance from a channel of a driving transistor of the first color sub-pixel to the scanning signal line.

6. The display substrate according to claim 5, wherein: In at least one pixel group, in the second direction, a distance from a channel of a driving transistor of the second color sub-pixel to the scanning signal line is greater than a distance from a channel of a driving transistor of the first color sub-pixel to the scanning signal line.

7. The display substrate according to claim 3, wherein: The display substrate is further provided with a scanning signal line extending along the first direction, wherein the scanning signal line is configured to provide a scanning signal to the pixel group; In at least one pixel group, an orthographic projection of the scanning signal line in a second direction overlaps with an orthographic projection of the gate of the driving transistor of the sub-pixel in the second direction, and the second direction is perpendicular to the first direction.

8. The display substrate according to claim 3, wherein: The display substrate is further provided with a scan signal line extending along the first direction, the scan signal line being configured to provide a scan signal to the sub-pixel; the scan signal line comprising a scan signal line main body and a protruding portion protruding from one side of the scan signal line main body; the scan signal line main body comprising a first sub-scan line, a second sub-scan line, and a connecting portion, the first sub-scan line and the second sub-scan line being connected via the connecting portion; the first sub-scan line being connected to a pixel circuit of a first color sub-pixel, and the second sub-scan line being connected to a pixel circuit of a second color sub-pixel; and an extending direction of a portion of the connecting portion intersecting with an extending direction of the first sub-scan line; The pixel circuit includes a compensation transistor, which includes a first gate and a second gate; in the compensation transistor, the first gate is a portion of the connecting portion that overlaps with the orthographic projection of the active semiconductor layer on the base substrate, and the second gate is a portion of the protruding portion that overlaps with the orthographic projection of the active semiconductor layer on the base substrate.

9. The display substrate according to claim 8, wherein: The connection portion includes a first sub-connection portion, a second sub-connection portion, and a third sub-connection portion connected in sequence, wherein the first sub-connection portion and the third sub-connection portion intersect with an extension direction of the first sub-scan line, and the second sub-connection portion and the first sub-scan line extend in the same direction; The first gate is a portion of the second sub-connecting portion that overlaps with an orthographic projection of the active semiconductor layer on the base substrate.

10. The display substrate according to claim 8, wherein The active semiconductor layer includes a first section, a second section, a third section, and a fourth section connected in sequence; the second section, the fourth section, and the main portion of the scanning signal line extend along the first direction, and the first section and the third section extend along a second direction, the second direction intersecting the first direction; the display substrate further includes a reset control signal line extending along the first direction and disposed on the same layer as the scanning signal line; the pixel circuit includes a reset transistor, and the reset transistor includes a gate; The second gate is a portion of the protrusion overlapping with the orthographic projection of the fourth segment on the substrate; the gate of the reset transistor includes a portion of the reset control signal line overlapping with the orthographic projection of the first segment on the substrate.

11. The display substrate according to claim 8, wherein The pixel circuit further includes a threshold compensation transistor, wherein the threshold compensation transistor includes a gate; the display substrate further includes a connection structure, wherein one end of the connection structure is connected to the gate of the driving transistor, and the other end of the connection structure is connected to the source and drain region of the threshold compensation transistor; The connecting structure includes a first portion and a second portion connected to the first portion, wherein an orthographic projection of the first portion on the base substrate and an orthographic projection of the protruding portion on the base substrate are located on the same side as an orthographic projection of the main body of the scanning signal line on the base substrate; A length of the first portion in the second direction is greater than a length of the protrusion in the second direction.

12. The display substrate according to claim 11, wherein: The size of the connection structure in the second direction ranges from 35 μm to 70 μm.

13. The display substrate according to claim 3, wherein: The display substrate is further provided with a plurality of scanning signal lines and reset control signal lines extending along the first direction, the scanning signal lines are configured to provide scanning signals to the pixel groups, and the reset control signal lines are configured to provide reset control signals to the pixel groups; The orthographic projection of the first electrode of at least one second color sub-pixel on the base substrate overlaps with the orthographic projection of the reset control signal line on the base substrate and the orthographic projection of the scan signal line on the base substrate.

14. The display substrate according to claim 1, wherein Any one of the orthographic projections of the pixel opening of the first color sub-pixel on the substrate, the orthographic projections of the pixel opening of the second color sub-pixel on the substrate, and the orthographic projections of the pixel opening of the third color sub-pixel on the substrate does not overlap with any one of the orthographic projections of the channel of the driving transistor of the first color sub-pixel on the substrate, the orthographic projections of the channel of the driving transistor of the second color sub-pixel on the substrate, and the orthographic projections of the channel of the driving transistor of the third color sub-pixel on the substrate.

15. The display substrate according to claim 14, wherein: The display substrate is further provided with a scanning signal line, which is configured to provide a scanning signal to the pixel group; the distance between the channel of the driving transistor of the sub-pixel and the scanning signal line in the second direction ranges from 1 μm to 50 μm.

16. The display substrate according to claim 1, wherein The pixel circuit also includes a capacitor, which includes a first plate and a second plate located on the side of the first plate facing away from the base substrate; the area of ​​the second plate of the second color sub-pixel is larger than the area of ​​the second plate of the first color sub-pixel, and the area of ​​the second plate of the second color sub-pixel is larger than the area of ​​the second plate of the third color sub-pixel.

17. The display substrate according to claim 1, wherein The display substrate further includes a first power line and a second power line located on a side of the first power line away from the base substrate; the first power line and the second power line are configured to provide a power signal to the pixel circuit; the first power line is electrically connected to the second power line; The second power line includes a first sub-power line extending along the first direction and a second sub-power line extending along the second direction, and the first sub-power line intersects the second sub-power line.

18. The display substrate according to claim 1, wherein The pixel circuit further includes a light emitting control transistor and an electrode connection structure, wherein the electrode connection structure electrically connects the first electrode of the sub-pixel to the source and drain regions of the light emitting control transistor; The areas of the electrode connection structures of at least two of the sub-pixels are different.

19. The display substrate according to claim 18, wherein The electrode connection structure includes at least a first sub-electrode connection structure and a second sub-electrode connection structure located on the side of the first sub-electrode connection structure away from the base substrate; the areas of the first sub-electrode connection structure and / or the second sub-electrode connection structure of at least two sub-pixels are different.

20. The display substrate according to claim 1, wherein The display substrate further includes a shielding line and a reset power signal line. The reset power signal line is configured to provide a reset power signal to the sub-pixel. The shielding line is electrically connected to the reset power signal line.

21. The display substrate according to any one of claims 1 to 20, characterized in that: The size range of the first color sub-pixel in the first direction is 35μm to 110μm, and the size range in the second direction is 20μm to 60μm; the size range of the second color sub-pixel in the first direction is 35μm to 120μm, and the size range in the second direction is 20μm to 80μm; the size range of the third color sub-pixel in the first direction is 35μm to 70μm, and the size range in the second direction is 20μm to 60μm.

22. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 21.

23. A display device, characterized in that: Includes the display panel according to claim 22.

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