Display platforms and display devices

Abstract

The display background consists of a display area and a non-display area. The non-display area is created with a gate control circuit; the gate control circuit has a cascaded shift register assembly; and the shift register assemblies are connected to at least one power supply line. The shift register assemblies include a first output circuit and a second output circuit. The first output circuit is connected to the first clock signal line group, and the second output circuit is connected to both the first and second clock signal line groups. In the first direction, the first clock signal line group and at least one power supply line are placed between the first and second output circuits, and the second clock signal line group is placed on the second output circuit side away from the first clock signal line group.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-Dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.

[0006] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a display area and a non-display area. The non-display area is provided with a gate drive circuit. The gate drive circuit comprises: a plurality of cascaded shift register units; the shift register unit is connected to at least one power line. The shift register unit comprises: a first output circuit and a second output circuit. The first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second group of clock signal lines is located on a side of the second output circuit away from the first group of clock signal lines.

[0007] In some exemplary embodiments, the at least one power line includes a first power line and a second power line. The first power line is connected to the first output circuit, and the second power line is connected to the second output circuit. In the first direction, the first power line is located between the first output circuit and the first group of clock signal lines, and the second power line is located between the first group of clock signal lines and the second output circuit.

[0008] In some exemplary embodiments, the non-display area is further provided with a third power line and a fourth power line. The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit. In the first direction, the fourth power line is located on a side of the first output circuit away from the first power line, and the third power line is located between the second power line and the second group of clock signal lines.

[0009] In some exemplary embodiments, the non-display area is further provided with an initial signal line. In the first direction, the initial signal line is located on a side of the fourth power line away from the first output circuit.

[0010] In some exemplary embodiments, the first output circuit includes: a first node control subcircuit, a second node control subcircuit, and a first output subcircuit. The first node control subcircuit is connected to the input terminal, the first output terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power terminal, the second power terminal, the first node, and the second node, and is configured to control the potentials of the first node and the second node under the control of the first clock terminal, the third clock terminal, and the input terminal. The second node control subcircuit is connected to the first node, the second node, the second power terminal, and the first output terminal, and is configured to maintain the potentials of the first node and the second node. The first output subcircuit is connected to the first node, the second node, the second clock terminal, the second power terminal, and the first output terminal, and is configured to control the first output terminal to output a first output signal under the control of the first node and the second node. The second node control subcircuit, the first output subcircuit, and the first node control subcircuit are arranged sequentially along a first direction.

[0011] In some exemplary embodiments, the first node control subcircuit includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor. The first control transistor has a control electrode connected to the first clock terminal, a first electrode connected to the input terminal, and a second electrode connected to the fourth node. The second control transistor has a control electrode connected to the first clock terminal, a first electrode connected to the fourth node, and a second electrode connected to the first node. The third control transistor has a control electrode connected to the third clock terminal, a first electrode connected to the first power supply terminal, and a second electrode connected to the second node. The fourth control transistor has a control electrode connected to the second node, a first electrode connected to the second power supply terminal, and a second electrode connected to the third node. The fifth control transistor has a control electrode connected to the second node, a first electrode connected to the third node, and a second electrode connected to the first node. The sixth control transistor has a control electrode connected to the first node, a first electrode connected to the first power supply terminal, and a second electrode connected to the third node. The seventh control transistor has a control electrode connected to the input terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the second node. The control electrode of the eighth control transistor is connected to the first output terminal, the first electrode is connected to the second clock terminal, and the second electrode is connected to the fourth node. The second node control subcircuit includes: a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first node, and the second electrode is connected to the first output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode is connected to the second power supply terminal. The first output subcircuit includes: a first output transistor and a second output transistor. The control electrode of the first output transistor is connected to the first node, the first electrode is connected to the second clock terminal, and the second electrode is connected to the first output terminal. The control electrode of the second output transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first output terminal.

[0012] In some exemplary embodiments, the first capacitor and the first output transistor are adjacent in the first direction, and the second capacitor and the second output transistor are adjacent in the first direction. The first capacitor and the second capacitor are adjacent in a second direction, and the first output transistor and the second output transistor are adjacent in the second direction. The second direction intersects the first direction.

[0013] In some exemplary embodiments, the active layers of the first control transistor, the second control transistor, and the eighth control transistor are an integrated structure, the active layers of the fourth control transistor and the fifth control transistor are an integrated structure; and the active layers of the first output transistor and the second output transistor are an integrated structure.

[0014] In some exemplary embodiments, in the first direction, the active layer of the sixth control transistor is located between the active layer of the fifth control transistor and the active layer of the second control transistor, and the active layer of the seventh control transistor is located between the active layer of the fourth control transistor and the active layer of the third control transistor.

[0015] In some exemplary embodiments, the second output circuit includes a denoising control subcircuit, a second output subcircuit, and a third output subcircuit. The denoising control subcircuit is connected to the first output terminal, the first clock terminal, the third clock terminal, the first power terminal, the second power terminal, and the first denoising control node. Under the control of the third clock signal terminal, the denoising control subcircuit is configured to rectify charge from the first power terminal to the first denoising control node, maintaining the first denoising control node at a voltage that turns on the second output subcircuit. Furthermore, under the control of the first output terminal, the denoising control subcircuit transmits a signal from the second power terminal to the first denoising control node, maintaining the first denoising control node at a voltage that turns off the second output subcircuit. The second output subcircuit is connected to the first denoising control node, the second output terminal, and the first power terminal. Under the control of the first denoising control node, the denoising control subcircuit transmits a signal from the first power terminal to the second output terminal. The third output subcircuit is connected to the first node, the fourth clock terminal, and the second output terminal. Under the control of the first node, the denoising control subcircuit transmits a signal from the fourth clock terminal to the second output terminal. The second and third output subcircuits are adjacent in the second direction. In the first direction, the denoising control subcircuit is located between the first group of clock signal lines and the second output subcircuit. The second direction intersects the first direction.

[0016] In some exemplary embodiments, the de-noising control subcircuit includes: a first de-noising control transistor, a second de-noising control transistor, a third de-noising control transistor, a fourth de-noising control transistor, a third capacitor, and a fourth capacitor. The first de-noising control transistor has a control electrode connected to the first output terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the second de-noising control node. The second de-noising control transistor has a control electrode connected to the third clock terminal, a first electrode connected to the first power supply terminal, and a second electrode connected to the second de-noising control node. The third de-noising control transistor has a control electrode and a first electrode connected to the second de-noising control node, and a second electrode connected to the first de-noising control node. The fourth de-noising control transistor has a control electrode connected to the first output terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the first de-noising control node. The third capacitor has a first electrode connected to the second de-noising control node, and a second electrode connected to the first clock terminal. The fourth capacitor has a first electrode connected to the first de-noising control node, and a second electrode connected to the first power supply terminal. The second output subcircuit includes: a third output transistor. The third output transistor has a control electrode connected to the first de-noising control node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second output terminal. The third output sub-circuit includes a fourth output transistor. The fourth output transistor has a control electrode connected to the first node, a first electrode connected to the fourth clock terminal, and a second electrode connected to the second output terminal.

[0017] In some exemplary embodiments, the third output transistor and the fourth output transistor are adjacent to each other in the second direction, and the first and second de-noising control transistors are adjacent to each other in the second direction. In the first direction, the third capacitor is located between the second and third de-noising control transistors, and the fourth de-noising control transistor is located between the first de-noising control transistor and the fourth capacitor.

[0018] In some exemplary embodiments, the active layers of the first and second de-noising control transistors are an integral structure, and the active layers of the third and fourth output transistors are an integral structure.

[0019] In some exemplary embodiments, the first group of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line; and the second group of clock signal lines includes a fourth clock signal line and a fifth clock signal line. The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the third clock signal provided by the third clock signal line have the same duty cycle. The fourth clock signal provided by the fourth clock signal line and the fifth clock signal provided by the fifth clock signal line have the same duty cycle, and the duty cycle of the fourth clock signal is less than the duty cycle of the first clock signal. The second clock signal is delayed by a set time period relative to the first clock signal, and the third clock signal is delayed by a set time period relative to the second clock signal, so that the first, second, and third clock signals are not simultaneously at the first voltage; the fourth and fifth clock signals are not simultaneously at the second voltage; and the first voltage is different from the second voltage.

[0020] In some exemplary embodiments, in the first direction, the first clock signal line, the second clock signal line, and the third clock signal line are arranged in sequence in a direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are arranged in sequence in a direction away from the second output circuit.

[0021] In some exemplary embodiments, the first output circuit of any stage of the shift register unit is connected to the first clock signal line, the second clock signal line, and the third clock signal line, and the second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

[0022] In some exemplary embodiments, the first clock terminal of the 6n+1th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock terminal of the 6n+2th stage shift register unit is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. The first clock terminal of the 6n+3th stage shift register unit is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock terminal of the 6n+4th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. The first clock terminal of the 6n+5th stage shift register unit is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock terminal of the 6n+6th stage shift register unit is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. Where n is a natural number.

[0023] In some exemplary embodiments, the first output terminal of the 2k-1th stage shift register unit is connected to the input terminal of the 2k+1th stage shift register unit, and the input terminal of the first stage shift register unit is connected to the first initial signal line. The first output terminal of the 2kth stage shift register unit is connected to the input terminal of the 2k+2th stage shift register unit, and the input terminal of the second stage shift register unit is connected to the second initial signal line, where k is a positive integer. The first group of clock signal lines includes: a first grouped clock signal line and a second grouped clock signal line, and the second group of clock signal lines includes: a third grouped clock signal line and a fourth grouped clock signal line. The 2k-1th stage shift register unit is connected to the first grouped clock signal line and the third grouped clock signal line, and the 2kth stage shift register unit is connected to the second grouped clock signal line and the fourth grouped clock signal line.

[0024] In some exemplary embodiments, in the first direction, the first grouped clock signal lines and the second grouped clock signal lines are arranged at intervals, and the third grouped clock signal lines and the fourth grouped clock signal lines are arranged at intervals.

[0025] In some exemplary embodiments, in a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes: a base substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the base substrate. The first semiconductor layer includes at least: an active layer of multiple transistors of the shift register unit. The first conductive layer includes at least: control electrodes of the multiple transistors of the shift register unit and first electrodes of multiple capacitors. The second conductive layer includes at least: second electrodes of the multiple capacitors of the shift register unit. The third conductive layer includes at least: first and second electrodes of the multiple transistors of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, and multiple power supply lines. The fourth conductive layer includes at least: a connection electrode of a third output subcircuit connecting the first node and the second output circuit.

[0026] On the other hand, an embodiment of the present disclosure provides a display device including the display substrate as described above.

[0027] On the other hand, an embodiment of the present disclosure provides a method for preparing a display substrate, which is used to prepare the display substrate as described above, the preparation method comprising: providing a base substrate; forming a gate drive circuit in a non-display area. The gate drive circuit comprises: a plurality of cascaded shift register units. The shift register unit is connected to at least one power line. The shift register unit comprises: a first output circuit and a second output circuit; the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second group of clock signal lines is located on a side of the second output circuit away from the first group of clock signal lines.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0031] FIG2 is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0032] FIG3 is a timing diagram of the operation of the shift register unit shown in FIG2 ;

[0033] FIG4 is a schematic diagram of a cascade connection of shift register units according to at least one embodiment of the present disclosure;

[0034] FIG5 is a top view of a shift register unit according to at least one embodiment of the present disclosure;

[0035] FIG6 is a schematic partial cross-sectional view along the QQ direction in FIG5 ;

[0036] 7A is a top view of a shift register unit after forming a first semiconductor layer according to at least one embodiment of the present disclosure;

[0037] 7B is a top view of the shift register unit after the first conductive layer is formed according to at least one embodiment of the present disclosure;

[0038] FIG7C is a top view of the shift register unit after forming the second conductive layer according to at least one embodiment of the present disclosure;

[0039] 7D is a top view of the shift register unit after forming the fourth insulating layer according to at least one embodiment of the present disclosure;

[0040] FIG7E is a top view of the shift register unit after forming the third conductive layer according to at least one embodiment of the present disclosure;

[0041] 7F is a top view of the shift register unit after forming the fourth conductive layer according to at least one embodiment of the present disclosure;

[0042] FIG8 is another schematic diagram of cascade connection of shift register units according to at least one embodiment of the present disclosure;

[0043] FIG9 is a timing diagram of a clock signal according to at least one embodiment of the present disclosure;

[0044] FIG10 is another top view of the shift register unit according to at least one embodiment of the present disclosure;

[0045] 11A is another top view of the shift register unit after forming the first semiconductor layer according to at least one embodiment of the present disclosure;

[0046] 11B is another top view of the shift register unit after the first conductive layer is formed according to at least one embodiment of the present disclosure;

[0047] 11C is another top view of the shift register unit after the second conductive layer is formed according to at least one embodiment of the present disclosure;

[0048] FIG11D is another top view of the shift register unit after the third conductive layer is formed according to at least one embodiment of the present disclosure;

[0049] FIG11E is another top view of the shift register unit after the fourth conductive layer is formed according to at least one embodiment of the present disclosure;

[0050] FIG. 12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The following will describe in detail the embodiments of the present disclosure in conjunction with the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0052] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0053] In the present disclosure, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In the present disclosure, "plurality" refers to a number of two or more.

[0054] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0055] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0056] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0057] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate electrode of the transistor is referred to as the control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0058] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0059] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0060] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0061] An embodiment of the present disclosure provides a display substrate, comprising: a display area and a non-display area. The non-display area is provided with a gate drive circuit. The gate drive circuit comprises: a plurality of cascaded shift register units; the shift register unit is connected to at least one power line. The shift register unit comprises: a first output circuit and a second output circuit; the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first group of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second group of clock signal lines is located on a side of the second output circuit away from the first group of clock signal lines.

[0062] The display substrate provided in this embodiment can save wiring space by setting the first output circuit and the second output circuit to share the first group of clock signal lines, and setting the power line and the shared first group of clock signal lines between the first output circuit and the second output circuit, which is conducive to realizing a display substrate with a narrow bezel design.

[0063] In some exemplary embodiments, the output signals of the first output circuit and the second output circuit have opposite phases.

[0064] In some exemplary embodiments, the at least one power line includes a first power line and a second power line, the first power line being connected to the first output circuit, and the second power line being connected to the second output circuit. In a first direction, the first power line is located between the first output circuit and the first set of clock signal lines, and the second power line is located between the first set of clock signal lines and the second output circuit. In some examples, the first power line continuously provides a low-level signal, and the second power line continuously provides a high-level signal. However, this embodiment is not limited to this.

[0065] In some exemplary embodiments, the non-display area is further provided with a third power line and a fourth power line. The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit. In the first direction, the fourth power line is located on a side of the first output circuit away from the first power line, and the third power line is located between the second power line and the second group of clock signal lines. In some examples, the third power line continuously provides a low-level signal, and the fourth power line continuously provides a high-level signal. However, this embodiment is not limited to this.

[0066] In some exemplary embodiments, the non-display area is further provided with an initial signal line. In the first direction, the initial signal line is located on a side of the fourth power line away from the first output circuit. In some examples, the input of the first-stage shift register unit is connected to the initial signal line. In some examples, the initial signal line includes a first initial signal line and a second initial signal line, the first initial signal line being connected to the input of the first-stage shift register unit, and the second initial signal line being connected to the input of the second-stage shift register unit. However, this embodiment is not limited to this.

[0067] In some exemplary embodiments, the first output circuit includes a first node control subcircuit, a second node control subcircuit, and a first output subcircuit. The first node control subcircuit is connected to the input terminal, the first output terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power terminal, the second power terminal, the first node, and the second node, and is configured to control the potentials of the first and second nodes under the control of the first clock terminal, the third clock terminal, and the input terminal. The second node control subcircuit is connected to the first node, the second node, the second power terminal, and the first output terminal, and is configured to maintain the potentials of the first and second nodes. The first output subcircuit is connected to the first node, the second node, the second clock terminal, the second power terminal, and the first output terminal, and is configured to control the first output terminal to output a first output signal under the control of the first and second nodes. The second node control subcircuit, the first output subcircuit, and the first node control subcircuit are arranged sequentially along a first direction. In some examples, the first power terminal continuously provides a low-level signal, and the second power terminal continuously provides a high-level signal. This circuit arrangement can save wiring space.

[0068] In some exemplary embodiments, the first node control subcircuit includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor. The first control transistor has a control electrode connected to the first clock terminal, a first electrode connected to the input terminal, and a second electrode connected to the fourth node. The second control transistor has a control electrode connected to the first clock terminal, a first electrode connected to the fourth node, and a second electrode connected to the first node. The third control transistor has a control electrode connected to the third clock terminal, a first electrode connected to the first power supply terminal, and a second electrode connected to the second node. The fourth control transistor has a control electrode connected to the second node, a first electrode connected to the second power supply terminal, and a second electrode connected to the third node. The fifth control transistor has a control electrode connected to the second node, a first electrode connected to the third node, and a second electrode connected to the first node. The sixth control transistor has a control electrode connected to the first node, a first electrode connected to the first power supply terminal, and a second electrode connected to the third node. The seventh control transistor has a control electrode connected to the input terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the second node. The control electrode of the eighth control transistor is connected to the first output terminal, the first electrode is connected to the second clock terminal, and the second electrode is connected to the fourth node. The second node control subcircuit includes: a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first node, and the second electrode is connected to the first output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode is connected to the second power supply terminal. The first output subcircuit includes: a first output transistor and a second output transistor. The control electrode of the first output transistor is connected to the first node, the first electrode is connected to the second clock terminal, and the second electrode is connected to the first output terminal. The control electrode of the second output transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first output terminal.

[0069] In some exemplary embodiments, the first capacitor and the first output transistor are adjacent to each other in a first direction, and the second capacitor and the second output transistor are adjacent to each other in the first direction; the first capacitor and the second capacitor are adjacent to each other in a second direction, and the first output transistor and the second output transistor are adjacent to each other in the second direction. The second direction intersects the first direction. For example, the first direction and the second direction are located in the same plane and are perpendicular to each other.

[0070] In some exemplary embodiments, the active layers of the first control transistor, the second control transistor, and the eighth control transistor are integrally formed, the active layers of the fourth control transistor and the fifth control transistor are integrally formed, and the active layers of the first output transistor and the second output transistor are integrally formed. However, this embodiment is not limited thereto.

[0071] In some exemplary embodiments, in the first direction, the active layer of the sixth control transistor is located between the active layer of the fifth control transistor and the active layer of the second control transistor, and the active layer of the seventh control transistor is located between the active layer of the fourth control transistor and the active layer of the third control transistor. However, this embodiment is not limited to this.

[0072] In some exemplary embodiments, the second output circuit includes a de-noising control subcircuit, a second output subcircuit, and a third output subcircuit. The de-noising control subcircuit is connected to the first output terminal, the first clock terminal, the third clock terminal, the first power terminal, the second power terminal, and the first de-noising control node. Under the control of the third clock signal terminal, the de-noising control subcircuit is configured to rectify the charge from the first power terminal to the first de-noising control node, maintaining the first de-noising control node at a voltage that turns on the second output subcircuit. Furthermore, under the control of the first output terminal, the de-noising control subcircuit transmits a signal from the second power terminal to the first de-noising control node, maintaining the first de-noising control node at a voltage that turns off the second output subcircuit. The second output subcircuit is connected to the first de-noising control node, the second output terminal, and the first power terminal. Under the control of the first de-noising control node, the de-noising control subcircuit transmits a signal from the first power terminal to the second output terminal. The third output subcircuit is connected to the first node, the fourth clock terminal, and the second output terminal. Under the control of the first node, the de-noising control subcircuit transmits a signal from the fourth clock terminal to the second output terminal. In the second direction, the second output sub-circuit and the third output sub-circuit are adjacent to each other; in the first direction, the denoising control sub-circuit is located between the first group of clock signal lines and the second output sub-circuit. The second direction intersects the first direction.

[0073] In some exemplary embodiments, the noise reduction control subcircuit includes: a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor. The first noise reduction control transistor has a control electrode connected to the first output terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the second noise reduction control node. The second noise reduction control transistor has a control electrode connected to the third clock terminal, a first electrode connected to the first power supply terminal, and a second electrode connected to the second noise reduction control node. The third noise reduction control transistor has a control electrode and a first electrode connected to the second noise reduction control node, and a second electrode connected to the first noise reduction control node. The fourth noise reduction control transistor has a control electrode connected to the first output terminal, a first electrode connected to the second power supply terminal, and a second electrode connected to the first noise reduction control node. The third capacitor has a first electrode connected to the second noise reduction control node, and a second electrode connected to the first clock terminal. The fourth capacitor has a first electrode connected to the first noise reduction control node, and a second electrode connected to the first power supply terminal. The second output subcircuit includes: a third output transistor. The third output transistor has a control electrode connected to the first noise reduction control node, a first electrode connected to the first power supply terminal, and a second electrode connected to the second output terminal. The third output sub-circuit includes a fourth output transistor, wherein the control electrode of the fourth output transistor is connected to the first node, the first electrode is connected to the fourth clock terminal, and the second electrode is connected to the second output terminal.

[0074] In some exemplary embodiments, the third output transistor and the fourth output transistor are adjacent to each other in the second direction, and the first and second de-noising control transistors are adjacent to each other in the second direction. In the first direction, the third capacitor is located between the second and third de-noising control transistors, and the fourth de-noising control transistor is located between the first and fourth capacitors. However, this embodiment is not limited to this.

[0075] In some exemplary embodiments, the active layers of the first and second noise reduction control transistors are integrated, and the active layers of the third and fourth output transistors are integrated. However, this embodiment is not limited thereto.

[0076] In some exemplary embodiments, the first group of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line. The second group of clock signal lines includes a fourth clock signal line and a fifth clock signal line. The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the third clock signal provided by the third clock signal line have the same duty cycle. The fourth clock signal provided by the fourth clock signal line and the fifth clock signal provided by the fifth clock signal line have the same duty cycle, and the duty cycle of the fourth clock signal is less than the duty cycle of the first clock signal. The second clock signal is delayed by a set time period relative to the first clock signal, and the third clock signal is delayed by a set time period relative to the second clock signal, so that the first, second, and third clock signals are not simultaneously at the first voltage. The fourth and fifth clock signals are not simultaneously at the second voltage. The first voltage is different from the second voltage. For example, the first voltage is less than the second voltage. For example, the first voltage can be a low level, and the second voltage can be a high level. However, this embodiment is not limited to this.

[0077] In some exemplary embodiments, in a first direction, the first clock signal line, the second clock signal line, and the third clock signal line are sequentially arranged in a direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are sequentially arranged in a direction away from the second output circuit. However, this embodiment does not limit the arrangement order of the multiple clock signal lines in the first group of clock signal lines, nor does it limit the arrangement order of the multiple clock signal lines in the second group of clock signal lines.

[0078] In some exemplary embodiments, the first output circuit of any stage of the shift register unit is connected to the first clock signal line, the second clock signal line, and the third clock signal line, and the second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

[0079] In some exemplary embodiments, the first clock terminal of the 6n+1th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock terminal of the 6n+2th stage shift register unit is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. The first clock terminal of the 6n+3th stage shift register unit is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock terminal of the 6n+4th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. The first clock terminal of the 6n+5th shift register unit is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock terminal of the 6n+6th shift register unit is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fifth clock signal line. Where n is a natural number. In this example, six cascaded shift register units serve as a minimum period repeating unit and can drive six rows of sub-pixels in the display area.

[0080] In some exemplary embodiments, the first output terminal of the 2k-1th shift register unit is connected to the input terminal of the 2k+1th shift register unit, and the input terminal of the first shift register unit is connected to the first initial signal line. The first output terminal of the 2kth shift register unit is connected to the input terminal of the 2k+2th shift register unit, and the input terminal of the second shift register unit is connected to the second initial signal line, where k is a positive integer. The first group of clock signal lines includes: a first grouped clock signal line and a second grouped clock signal line, and the second group of clock signal lines includes: a third grouped clock signal line and a fourth grouped clock signal line. The 2k-1th shift register unit is connected to the first grouped clock signal line and the third grouped clock signal line, and the 2kth shift register unit is connected to the second grouped clock signal line and the fourth grouped clock signal line. In some examples, twelve shift register units can serve as a minimum period repeating unit to drive twelve rows of sub-pixels in a display area.

[0081] In some exemplary embodiments, in a first direction, the first and second grouped clock signal lines are arranged alternately, and the third and fourth grouped clock signal lines are arranged alternately. However, this embodiment is not limited to this. For example, the first and second grouped clock signal lines are arranged sequentially along the first direction, and the third and fourth grouped clock signal lines are arranged sequentially along the first direction.

[0082] In some exemplary embodiments, the first group of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line; the second group of clock signal lines includes a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line. The third group of clock signal lines includes a fourth clock signal line and a fifth clock signal line; and the fourth group of clock signal lines includes a ninth clock signal line and a tenth clock signal line. The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, the third clock signal provided by the third clock signal line, the sixth clock signal provided by the sixth clock signal line, the seventh clock signal provided by the seventh clock signal line, and the eighth clock signal provided by the eighth clock signal line all have the same duty cycle. The second clock signal is delayed by a first set time relative to the first clock signal, and the third clock signal is delayed by a first set time relative to the second clock signal, so that the first, second, and third clock signals are not simultaneously at the first voltage. The seventh clock signal is delayed by a first set time relative to the sixth clock signal, and the eighth clock signal is delayed by a first set time relative to the seventh clock signal, so that the sixth, seventh, and eighth clock signals are not simultaneously at the first voltage. The sixth clock signal is delayed by a second set time relative to the first clock signal, the seventh clock signal is delayed by a second set time relative to the second clock signal, and the eighth clock signal is delayed by a second set time relative to the third clock signal. The fourth clock signal provided by the fourth clock signal line, the fifth clock signal provided by the fifth clock signal line, the ninth clock signal provided by the ninth clock signal line, and the tenth clock signal provided by the tenth clock signal line have the same duty cycle. The duty cycle of the fourth clock signal is less than the duty cycle of the first clock signal. The fourth and fifth clock signals are not simultaneously at the second voltage, and the ninth and tenth clock signals are not simultaneously at the second voltage, and the second voltage is different from the first voltage. The ninth clock signal is delayed by a second set time relative to the fourth clock signal, and the tenth clock signal is delayed by a second set time relative to the fifth clock signal.

[0083] In some exemplary embodiments, in a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes: a base substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the base substrate. The first semiconductor layer includes at least an active layer of multiple transistors of the shift register unit. The first conductive layer includes at least control electrodes of the multiple transistors of the shift register unit and first electrodes of multiple capacitors. The second conductive layer includes at least second electrodes of the multiple capacitors of the shift register unit. The third conductive layer includes at least first and second electrodes of the multiple transistors of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, and multiple power supply lines. The fourth conductive layer includes at least a connection electrode of a third output subcircuit connecting the first node and the second output circuit.

[0084] The solution of this embodiment is illustrated below through some examples.

[0085] In some exemplary embodiments, the display substrate may include: a display area and a non-display area. For example, the non-display area may be located outside the display area. However, this embodiment is not limited to this. The display area includes at least a plurality of pixel circuits arranged in a regular pattern, a plurality of gate lines extending along a first direction (for example, including: scan lines, reset signal lines, and light-emitting control lines), and a plurality of data lines and power lines extending along a second direction. The first direction and the second direction are located in the same plane, and the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.

[0086] In some exemplary embodiments, a pixel unit within the display area may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0087] In some exemplary embodiments, the shape of the sub-pixels may be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0088] In some example embodiments, the non-display area may be provided with a timing controller, a data driver circuit, and a gate driver circuit. The gate driver circuit may be provided on opposite sides of the display area, for example, on the left and right sides of the display area; the timing controller and the data driver circuit may be provided on one side of the display area, for example, on the bottom side of the display area. However, this embodiment is not limited to this.

[0089] In some exemplary embodiments, the data driving circuit may provide a data signal to the sub-pixel through a data line. The gate driving circuit may provide a scan signal to the sub-pixel through a scan line, and provide a reset signal to the sub-pixel through a reset signal line, or provide a light-emitting control signal to the sub-pixel through a light-emitting control line. The timing controller may provide a driving signal to the data driving circuit and the gate driving circuit. The actions of the gate driving circuit and the data driving circuit may be controlled by the timing controller. The timing controller may provide the data driving circuit with grayscale data that specifies the grayscale to be displayed in the sub-pixel. The data driving circuit may provide a data signal of a potential corresponding to the grayscale data of the sub-pixel to the sub-pixel of the row selected by the gate driving circuit via the data line.

[0090] In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. However, this embodiment is not limited thereto. For example, the pixel driving circuit may include an N-type transistor and a P-type transistor. The N-type transistor may be, for example, an oxide thin film transistor, and the P-type transistor may be, for example, a low-temperature polycrystalline silicon thin film transistor. The active layer of the low-temperature polycrystalline silicon thin film transistor adopts low-temperature polycrystalline silicon (LTPS), and the active layer of the oxide thin film transistor adopts an oxide semiconductor (Oxide). Low-temperature polycrystalline silicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. By integrating low-temperature polycrystalline silicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, the advantages of both can be utilized, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0091] In some exemplary embodiments, the gate drive circuit includes a plurality of cascaded shift register units. For example, the input end of the first-stage shift register unit can be connected to the initial signal line; the first output end of the i-th stage shift register unit can be connected to the input end of the i+1-th stage shift register unit to provide an input signal to the i+1-th stage shift register unit, where i is a positive integer. The second output end of the shift register unit can provide a scan signal to the sub-pixel through a scan line, and provide a reset signal to the sub-pixel through a reset signal line. For example, the first output signal provided by the first output end of the shift register unit can be configured to control the opening of a P-type transistor (e.g., a low-temperature polysilicon thin-film transistor) in a pixel circuit, and the second output signal provided by the second output end of the shift register unit can be configured to control the opening of an N-type transistor (e.g., an oxide thin-film transistor) in the pixel circuit. However, this embodiment is not limited to this.

[0092] FIG1 is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG1 , the shift register unit provided by this exemplary embodiment includes: a first output circuit 10 and a second output circuit 20. The first output circuit 10 outputs a first output signal via a first output terminal OUT1, and the second output circuit 20 outputs a second output signal via a second output terminal OUT2. The first output signal and the second output signal have opposite phases.

[0093] In some exemplary embodiments, as shown in FIG1 , the first output circuit 10 includes a first node control subcircuit 11, a second node control subcircuit 12, and a first output subcircuit 13. The first node control subcircuit 11 is connected to an input terminal INPUT, a first output terminal OUT1, a first power supply terminal V1, a second power supply terminal V2, a first clock terminal CK1, a second clock terminal CK2, a third clock terminal CK3, a first node N1, and a second node N2. The first node control subcircuit 11 is configured to control the potentials of the first node N1 and the second node N2 under the control of the first clock terminal CK1, the input terminal INPUT, and the third clock terminal CK3. The second node control subcircuit 12 is connected to the first node N1, the second node N2, the second power supply terminal V2, and the first output terminal OUT1. The second node control subcircuit 12 is configured to maintain the potentials of the first node N1 and the second node N2. The first output subcircuit 13 is connected to the second clock terminal CK2, the second power supply terminal V2, the first node N1, the second node N2, and the first output terminal OUT1. The first output subcircuit 13 is configured to control the first output terminal OUT1 to output a first output signal under the control of the first node N1 and the second node N2.

[0094] In some exemplary embodiments, as shown in FIG1 , the second output circuit 20 includes a de-noising control sub-circuit 21, a second output sub-circuit 22, and a third output sub-circuit 23. The de-noising control sub-circuit 21 is connected to a first clock terminal CK1, a third clock terminal CK3, a first de-noising control node PD1, a first output terminal OUT1, a first power terminal V1, and a second power terminal V2. Under the control of the third clock terminal CK3, the de-noising control sub-circuit 21 is configured to rectify the charge from the first power terminal V1 to the first de-noising control node PD1, maintaining the first de-noising control node PD1 at a voltage that turns on the second output sub-circuit 22. Furthermore, under the control of the first output terminal OUT1, the de-noising control sub-circuit 21 transmits a signal from the second power terminal V2 to the first de-noising control node PD1, maintaining the first de-noising control node PD1 at a voltage that turns off the second output sub-circuit 22. The second output sub-circuit 22 is connected to the first de-noising control node PD1, the second output terminal OUT2, and the first power terminal V1, and is configured to transmit a signal from the first power terminal V1 to the second output terminal OUT2 under the control of the first de-noising control node PD1. The third output sub-circuit 23 is connected to the first node N1 , the fourth clock terminal CB and the second output terminal OUT2 , and is configured to transmit the signal of the fourth clock terminal CB to the second output terminal OUT2 under the control of the first node N1 .

[0095] In some examples, the first power supply terminal V1 may continuously provide a low-level signal, and the second power supply terminal V2 may continuously provide a high-level signal. However, this embodiment is not limited thereto.

[0096] In this exemplary embodiment, the first output signal outputted by the first output terminal OUT1 and the second output signal outputted by the second output terminal OUT2 have opposite phases. By providing a denoising control subcircuit in the second output circuit, continuous denoising can be achieved for the second output terminal OUT2 of the shift register unit, thereby improving display stability.

[0097] FIG2 is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure. As shown in FIG2 , the first node control subcircuit 11 includes a first control transistor M1, a second control transistor M2, a third control transistor M5, a fourth control transistor M6, a fifth control transistor M7, a sixth control transistor M8, a seventh control transistor M9, and an eighth control transistor M10.

[0098] The control electrode of the first control transistor M1 is connected to the first clock terminal CK1, the first electrode is connected to the input terminal INPUT, and the second electrode is connected to the fourth node N4. The control electrode of the second control transistor M2 is connected to the first clock terminal CK1, the first electrode is connected to the fourth node N4, and the second electrode is connected to the first node N1. The control electrode of the third control transistor M5 is connected to the third clock terminal CK3, the first electrode is connected to the first power supply terminal V1, and the second electrode is connected to the second node N2. The control electrode of the fourth control transistor M6 is connected to the second node N2, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the third node N3. The control electrode of the fifth control transistor M7 is connected to the second node N2, the first electrode is connected to the third node N3, and the second electrode is connected to the first node N1. The control electrode of the sixth control transistor M8 is connected to the first node N1, the first electrode is connected to the first power supply terminal V1, and the second electrode is connected to the third node N3. The control electrode of the seventh control transistor M9 is connected to the input terminal INPUT, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the second node N2. The control electrode of the eighth control transistor M10 is connected to the first output terminal OUT1 , the first electrode is connected to the second clock terminal CK2 , and the second electrode is connected to the fourth node N4 .

[0099] In this exemplary embodiment, the first control transistor M1 and the second control transistor M2 form a dual-gate transistor having a low leakage current. An eighth control transistor M10 is used to control the potential of the fourth node N4 to reduce the drain-source voltage of the first control transistor M1 and the second control transistor M2 during a set period of time, thereby reducing the leakage current of the first control transistor M1 and the second control transistor M2. The fourth control transistor M6 and the fifth control transistor M7 form a dual-gate transistor, and a sixth control transistor M8 is used to control the potential of the third node N3 to reduce the drain-source voltage of the fourth control transistor M6 and the drain-source voltage of the fifth control transistor M7 during a set period of time, thereby reducing the leakage current of the fourth control transistor M6 and the leakage current of the fifth control transistor M7.

[0100] The second node control subcircuit 12 includes a first capacitor C1 and a second capacitor C2. The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to the first output terminal OUT1. The first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the second power supply terminal V2.

[0101] The first output sub-circuit 13 includes a first output transistor M3 and a second output transistor M4. The first output transistor M3 has a control electrode connected to the first node N1, a first electrode connected to the second clock terminal CK2, and a second electrode connected to the first output terminal OUT1. The second output transistor M4 has a control electrode connected to the second node N2, a first electrode connected to the second power supply terminal V2, and a second electrode connected to the first output terminal OUT1.

[0102] In some exemplary embodiments, as shown in FIG. 2 , the denoising control subcircuit 21 includes: a first denoising control transistor M11 , a second denoising control transistor M12 , a third denoising control transistor M13 , a fourth denoising control transistor M14 , a third capacitor C3 , and a fourth capacitor C4 .

[0103] The control electrode of the first de-noising control transistor M11 is connected to the first output terminal OUT1, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the second de-noising control node PD2. The control electrode of the second de-noising control transistor M12 is connected to the third clock terminal CK3, the first electrode is connected to the first power supply terminal V1, and the second electrode is connected to the second de-noising control node PD2. The control electrode and the first electrode of the third de-noising control transistor M13 are connected to the second de-noising control node PD2, and the second electrode is connected to the first de-noising control node PD1. The control electrode of the fourth de-noising control transistor M14 is connected to the first output terminal OUT1, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the first de-noising control node PD1. The first electrode of the third capacitor C3 is connected to the second de-noising control node PD2, and the second electrode is connected to the first clock terminal CK1. The first electrode of the fourth capacitor C4 is connected to the first de-noising control node PD1, and the second electrode is connected to the first power supply terminal V1.

[0104] In this exemplary embodiment, the second de-noising control transistor M12, the third de-noising control transistor M13, the third capacitor C3 and the fourth capacitor C4 form a charge pump structure. The charge pump structure regulates the voltage so that the potential of the first de-noising control node PD1 is stabilized at a potential that can turn on the second output sub-circuit, thereby ensuring that the second output sub-circuit is continuously turned on during the holding phase of the driving process of a row of gate lines, thereby continuously de-noising the second output end.

[0105] In some exemplary embodiments, the second output sub-circuit includes a third output transistor M15. The third output transistor M15 has a control electrode connected to the first de-noising control node PD1, a first electrode connected to the first power supply terminal V1, and a second electrode connected to the second output terminal OUT2. The third output sub-circuit includes a fourth output transistor M16. The fourth output transistor M16 has a control electrode connected to the first node N1, a first electrode connected to the fourth clock terminal CB, and a second electrode connected to the second output terminal OUT2.

[0106] In this exemplary embodiment, the first denoising control node PD1, the second denoising control node PD2, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual components but rather represent junctions of related electrical connections in a circuit diagram. In other words, these nodes are equivalent to junctions of related electrical connections in the circuit diagram.

[0107] In this exemplary embodiment, FIG2 shows an exemplary structure of a first node control subcircuit, a second node control subcircuit, a first output subcircuit, a denoising control subcircuit, a second output subcircuit, and a third output subcircuit. Those skilled in the art will readily appreciate that the implementation of the first node control subcircuit, the second node control subcircuit, the first output subcircuit, the denoising control subcircuit, the second output subcircuit, and the third output subcircuit is not limited thereto, as long as the functions thereof are achieved.

[0108] The following further illustrates the technical solution of the disclosed embodiment through the operation of the shift register unit. The following description uses the operation of the first-stage shift register unit as an example, where the input terminal INPUT of the first-stage shift register unit is connected to the initial signal line STV. FIG3 is an operation timing diagram of the shift register unit shown in FIG2.

[0109] In this exemplary embodiment, during the driving process of a row of gate lines within a frame period, after the shift register unit outputs a scan signal through the second output terminal, the shift register unit outputs a non-working voltage to the gate line to which it is connected during the holding phase to ensure that the sub-pixel connected to the gate line is turned off.

[0110] The following description uses as an example a shift register unit in which all transistors are P-type transistors, a first power supply terminal V1 provides a low-level voltage, and a second power supply terminal V2 provides a high-level voltage. In this exemplary embodiment, the shift register unit is described by using as an example a first clock terminal CK1 connected to a first clock signal line GCK1, a second clock terminal CK2 connected to a second clock signal line GCK2, a third clock terminal CK3 connected to a third clock signal line GCK3, and a fourth clock terminal CB connected to a fourth clock signal line GCB1.

[0111] As shown in FIG3 , the driving process of the shift register unit provided by this exemplary embodiment for a row of gate lines includes at least the following stages: a pre-charge stage S1 , a bootstrap output stage S2 , a node pull-up stage S3 and a hold stage S4 .

[0112] During the pre-charge phase S1, the initial signal line STV provides a low-level signal, the first clock signal line GCK1 provides a low-level signal, the fourth clock signal line GCB1 provides a low-level signal, and the second clock signal line GCK2 and the third clock signal line GCK3 provide high-level signals. The first control transistor M1 and the second control transistor M2 are turned on under the control of the low-level signal provided by the first clock signal line GCK1. The initial signal line STV provides a low-level signal to the first node N1, pulling the potential of the first node N1 to a low potential of VGL+Vth. The first output transistor M3 is turned on under the control of the low potential of the first node N1, and the second clock signal line GCK2 provides a high-level signal to the first output terminal OUT1. The voltage stored across the first capacitor C1 is VGL+Vth-VGH. Vth is the threshold voltage of the first control transistor M1, and VGL is a low voltage.

[0113] In the precharge phase S1, the seventh control transistor M9 is turned on by a low-level signal provided by the input terminal INPUT, and the second power supply terminal V2 provides a high-level signal to the second node N2. The second output transistor M4, the fourth control transistor M6, and the fifth control transistor M7 are turned off by a high-level signal provided by the second node N2. The third control transistor M5 is turned off by a high-level signal provided by the third clock signal line GCK3. The sixth control transistor M8 is turned on by a low-level signal provided by the first node N1, and the first power supply terminal V1 provides a low-level signal to the third node N3. The eighth control transistor M10 is turned off by a high-level signal provided by the first output terminal OUT1.

[0114] During the precharge phase S1, the first and fourth de-noising control transistors M11 and M14 are both turned off by a high-level signal at the first output terminal OUT1. The second de-noising control transistor M12 is turned off by a high-level signal provided by the third clock signal line GCK3. The fourth output transistor M16 is turned on by a low potential at the first node N1, and the fourth clock signal line GCB1 provides a low-level signal to the second output terminal OUT2.

[0115] In the bootstrap output phase S2, the initial signal line STV provides a high-level signal, the first clock signal line GCK1, the third clock signal line GCK3, and the fourth clock signal line GCB1 provide high-level signals, and the second clock signal line GCK2 provides a low-level signal. The first control transistor M1 and the second control transistor M2 are disconnected under the control of the high-level signal provided by the first clock signal line GCK1. The first node N1 remains at a low potential, and the first output transistor M3 is turned on. The second clock signal line GCK2 provides a low-level signal to the first output terminal OUT1. Because the voltage across the first capacitor C1 cannot change suddenly, the potential of the first node N1 is pulled down to 2VGL+Vth-2VGH under the action of the first capacitor C1 to ensure that the first output transistor M3 is turned on. Wherein, VGH is a high voltage.

[0116] During the bootstrap output phase S2, the seventh control transistor M9 is turned off in response to a high-level signal from the initial signal line STV. The second capacitor C2 maintains a high potential at the second node N2, and the second output transistor M4, fourth control transistor M6, and fifth control transistor M7 are turned off. The sixth control transistor M8 is turned on in response to a low potential at the first node N1, and the first power supply terminal V1 provides a low-level signal to the third node N3.

[0117] During the bootstrap output phase S2, the first and fourth de-noising control transistors M11 and M14 are both turned on in response to a low-level signal at the first output terminal OUT1. The second power supply terminal V2 provides a high-level signal to the first and second de-noising control nodes PD1 and PD2. The second de-noising control node M12 is disconnected in response to a high-level signal provided by the third clock signal line GCK3. The third de-noising control transistor M13 is disconnected in response to a high-level voltage at the second de-noising control node PD2, and the third output transistor M15 is disconnected in response to a high-level voltage at the first de-noising control node PD1. The fourth output transistor M16 is turned on in response to a low-level voltage at the first node N1, and the fourth clock signal line GCB1 provides a high-level signal to the second output terminal OUT2.

[0118] In the latter time period included in the bootstrap output stage S2, the second clock signal provided by the second clock signal line GCK2 jumps from a low-level signal to a high-level signal. Since the potential of the first node N1 is still lower than the potential of the second clock signal, the first output transistor M3 is turned on, and the first output terminal OUT1 outputs the second clock signal, thereby realizing a low pulse output of the first output terminal OUT1.

[0119] During the bootstrap output phase S2, the low potential at the first node N1 turns on the fourth output transistor M16, causing the second output terminal OUT2 to output the fourth clock signal provided by the fourth clock signal line GCB1. Because the high pulse width of the fourth clock signal is shorter than the low pulse width of the second clock signal provided by the second clock signal line GCK2, the entire pulse of the fourth clock signal, including both the rising and falling portions, is transmitted to the second output terminal OUT2. The low potential at the first output terminal OUT1 turns on the first and fourth de-noising control transistors M11 and M14, stabilizing the potentials of the first and second de-noising control nodes PD1 and PD2 at high levels. This turns off the third output transistor M15, preventing any logical conflicts in the output of the second output terminal OUT2.

[0120] During the node pull-up phase S3, the initial signal line STV provides a high-level signal, the first and second clock signal lines GCK1 and GCK2 provide high-level signals, and the third and fourth clock signal lines GCK3 and GCB1 provide low-level signals. The third control transistor M5 is turned on by the low-level signal provided by the third clock signal line GCK3, and the first power supply terminal V1 provides a low-level signal to the second node N2. The second output transistor M4, the fourth control transistor M6, and the fifth control transistor M5 are turned on by the low potential of the second node N2, and the second power supply terminal V2 provides a high-level signal to the first output terminal OUT1 and the first node N1. The first output transistor M3 and the sixth control transistor M8 are turned off by the high potential of the first node N1.

[0121] During the node pull-up phase S3, the first and fourth de-noising control transistors M11 and M14 are both turned off in response to a high-level signal from the first output terminal OUT1. The second de-noising control transistor M12 is turned on in response to a low-level signal from the third clock signal line GCK3, and the first power supply terminal V1 provides a low-level signal to the second de-noising control node PD2. Because the first clock signal line GCK1 provides a high-level signal, the third capacitor C3 stores a potential of VGL + Vth12 - VGH, where Vth12 is the threshold voltage of the second de-noising control transistor M12. The third de-noising control transistor M13 is turned on in response to a low-level signal from the second de-noising control node PD2, pulling the first de-noising control node PD1 to a low level. The third output transistor M15 is turned on in response to a low-level signal from the first de-noising control node PD1, and the first power supply terminal V1 provides a low-level signal to the second output terminal OUT2. The fourth output transistor M16 is turned off in response to a high-level signal from the first node N1.

[0122] During the hold phase S4, the third clock signal provided by the third clock signal line GCK3 periodically pulls the potential of the second node N2 to a low level, ensuring that the second output transistor M4 is conductive, causing the first output terminal OUT1 to stably output a high level. The third clock signal periodically pulls the potentials of the second and first de-noising control nodes PD2 and PD1 down, storing VGL + Vth12 - VGH in the third capacitor C3. Simultaneously, the first clock signal provided by the first clock signal line GCK1 periodically transitions to a low voltage, pulling the potentials of the second and first de-noising control nodes PD2 and PD1 to an even lower level via the third capacitor C3. This ensures that the third output transistor M15 is fully conductive, outputting the low-level signal provided by the first power supply terminal V1 to the second output terminal OUT2.

[0123] In this exemplary embodiment, by continuously performing denoising on the second output terminal OUT2 in the holding phase S4 , the stability of the displayed image can be maintained and the display effect can be improved.

[0124] In some exemplary embodiments, as shown in FIG3 , the first clock signal provided by the first clock signal line GCK1, the second clock signal provided by the second clock signal line GCK2, the third clock signal provided by the third clock signal line GCK3, the fourth clock signal provided by the fourth clock signal line GCB1, and the fifth clock signal provided by the fifth clock signal line GCB2 are all pulse signals. The duty cycles of the first, second, and third clock signals may be the same. The second clock signal is delayed by a set time period relative to the first clock signal, and the third clock signal is delayed by a set time period relative to the second clock signal, so that the first, second, and third clock signals are not all at low voltage at the same time. For example, the second clock signal is delayed by 1H relative to the first clock signal, and the third clock signal is delayed by 1H relative to the second clock signal, where H is the time required for the data signal to refresh a row of pixels. The duty cycles of the fourth and fifth clock signals may be the same. The duty cycle of the fourth clock signal may be smaller than the duty cycle of the first clock signal. The duty cycle refers to the proportion of the high-level duration within a pulse period (including the high-level duration and the low-level duration) to the entire pulse period. The fourth clock signal and the fifth clock signal are not high voltages at the same time. However, this embodiment is not limited to this.

[0125] In some exemplary embodiments, the duty cycle of the first clock signal, the second clock signal, and the third clock signal may be slightly less than 1 / 3, or the duty cycle of the first clock signal, the second clock signal, and the third clock signal may be approximately equal to 1 / 3. However, this embodiment is not limited thereto.

[0126] FIG4 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG4 , the gate driving circuit includes a plurality of cascaded shift register units.

[0127] Among them, the first clock end of the 6n+1th stage shift register unit is connected to the first clock signal line GCK1, the second clock end is connected to the second clock signal line GCK2, the third clock end is connected to the third clock signal line GCK3, and the fourth clock end is connected to the fourth clock signal line GCB1.

[0128] The first clock terminal of the 6n+2th stage shift register unit is connected to the second clock signal line GCK2, the second clock terminal is connected to the third clock signal line GCK3, the third clock terminal is connected to the first clock signal line GCK1, and the fourth clock terminal is connected to the fifth clock signal line GCB2.

[0129] The first clock terminal of the 6n+3th stage shift register unit is connected to the third clock signal line GCK3, the second clock terminal is connected to the first clock signal line GCK1, the third clock terminal is connected to the second clock signal line GCK2, and the fourth clock terminal is connected to the fourth clock signal line GCB1.

[0130] The first clock terminal of the 6n+4th stage shift register unit is connected to the first clock signal line GCK1, the second clock terminal is connected to the second clock signal line GCK2, the third clock terminal is connected to the third clock signal line GCK3, and the fourth clock terminal is connected to the fifth clock signal line GCB2.

[0131] The first clock terminal of the 6n+5th stage shift register unit is connected to the second clock signal line GCK2, the second clock terminal is connected to the third clock signal line GCK3, the third clock terminal is connected to the first clock signal line GCK1, and the fourth clock terminal is connected to the fourth clock signal line GCB1.

[0132] The first clock terminal of the 6n+6th stage shift register unit is connected to the third clock signal line GCK3, the second clock terminal is connected to the first clock signal line GCK1, the third clock terminal is connected to the second clock signal line GCK2, and the fourth clock terminal is connected to the fifth clock signal line GCB2, where n is a natural number.

[0133] In this exemplary embodiment, the first group of clock signal lines includes a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3; the second group of clock signal lines includes a fourth clock signal line GCB1 and a fifth clock signal line GCB2. Each shift register unit stage is connected to three clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines. The six cascaded shift register units in the gate drive circuit of this embodiment serve as a minimum periodic repeating unit to drive six rows of sub-pixels in the display area.

[0134] The description of the clock signals provided by the first clock signal line GCK1 to the fifth clock signal line GCB2 can be described as above, and thus will not be repeated here.

[0135] Figure 5 is a top view of the shift register unit of at least one embodiment of the present disclosure. In Figure 5, the cascaded 6n+1-stage and 6n+2-stage shift register units (for example, n=1) are used as an example for illustration. The following mainly describes the structure of the 6n+1-stage shift register unit as an example. Figure 6 is a schematic partial cross-sectional view along the QQ direction in Figure 5. The equivalent circuit diagram of the shift register unit of this exemplary embodiment is shown in Figure 2. In this exemplary embodiment, the transistors in the shift register unit are P-type transistors, and are low-temperature polycrystalline silicon thin film transistors. However, this embodiment is not limited to this.

[0136] In some exemplary embodiments, as shown in FIG5 , within a plane parallel to the display substrate, the first output circuit, the first group of clock signal lines, the second output circuit, and the second group of clock signal lines are sequentially arranged along a first direction X. In this example, the first output circuit and the second output circuit share the first group of clock signal lines, and the first group of clock signal lines are arranged between the first output circuit and the second output circuit, which can save wiring space.

[0137] In some exemplary embodiments, as shown in FIG5 , a first group of clock signal lines includes a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3. A second group of clock signal lines includes a fourth clock signal line GCB1 and a fifth clock signal line GCB2. The first clock signal line GCK1, the second clock signal line GCK2, and the third clock signal line GCK3 are arranged sequentially in a first direction X, away from the first output circuit. The fourth clock signal line GCB1 and the fifth clock signal line GCB2 are arranged sequentially in the first direction X, away from the second output circuit.

[0138] In some exemplary embodiments, as shown in FIG5 , in a first direction X, a first group of clock signal lines is located between the first node control subcircuit of the first output circuit and the denoising control subcircuit of the second output circuit. A second group of clock signal lines is located on a side of the second and third output subcircuits away from the denoising control subcircuit. The first node control subcircuit is located between the first output subcircuit and the first group of clock signal lines. The first output subcircuit is located between the second node control subcircuit and the first node control subcircuit. The denoising control subcircuit is located between the first group of clock signal lines and the second output subcircuit. The second and third output subcircuits are arranged sequentially along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0139] In some exemplary embodiments, as shown in FIG5 , a low-level signal is continuously provided via a first power line PL1a and a third power line PL1b. The first power line PL1a is connected to the first output circuit of the shift register unit and is configured to provide a low-level signal to the first output circuit. The third power line PL1b is connected to the second output circuit of the shift register unit and is configured to provide a low-level signal to the second output circuit. In the first direction X, the first power line PL1a is located between the first node control sub-circuit and the first set of clock signal lines, while the third power line PL1b is located on the side of the second and third output sub-circuits closer to the first set of clock signal lines. However, this embodiment is not limited to this.

[0140] In some exemplary embodiments, as shown in FIG5 , a high-level signal is continuously provided via the second power line PL2b and the fourth power line PL2a. The second power line PL2b is connected to the second output circuit and configured to provide a high-level signal to the second output circuit. The fourth power line PL2a is connected to the first output circuit and configured to provide a high-level signal to the first output circuit. In the first direction X, the fourth power line PL2a is located on a side of the first output sub-circuit away from the first node control sub-circuit, and the second power line PL2b is located on a side of the denoising control sub-circuit closer to the first group of clock signal lines. However, this embodiment is not limited to this.

[0141] 5 , in some exemplary embodiments, the initial signal line STV is located on a side of the fourth power line PL2 a away from the first output sub-circuit in the first direction X. However, this embodiment is not limited thereto.

[0142] In some exemplary embodiments, as shown in FIG5 , the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCB1, the fifth clock signal line GCB2, the first power line PL1a, the fourth power line PL2a, the third power line PL1b, the second power line PL2b, and the initial signal line STV all extend along the second direction Y. The first output terminal OUT1 and the second output terminal OUT2 both extend along the first direction X.

[0143] In some exemplary embodiments, as shown in FIG5 , within a plane parallel to the display substrate, the first output transistor M3 and the second output transistor M4 of the first output sub-circuit are adjacent in the second direction Y. The first capacitor C1 and the second capacitor C2 of the second node control sub-circuit are adjacent in the second direction Y. The first capacitor C1 and the first output transistor M3 are adjacent in the first direction X, and the first capacitor C1 is located on a side of the first output transistor M3 away from the first node control sub-circuit. The second capacitor C2 and the second output transistor M4 are adjacent in the first direction X, and the second capacitor C2 is located on a side of the second output transistor M4 away from the first node control sub-circuit.

[0144] In some exemplary embodiments, as shown in FIG5 , within a plane parallel to the display substrate, the fourth control transistor M6 and the fifth control transistor M7 are adjacent in the second direction Y. The seventh control transistor M9 and the fourth control transistor M6 are adjacent in the first direction X, and the seventh control transistor M9 is located on a side of the fourth control transistor M6 away from the second output transistor M4. The sixth control transistor M8 and the fifth control transistor M7 are adjacent in the first direction X, and the sixth control transistor M8 is located on a side of the fifth control transistor M7 away from the first output transistor M3. The second control transistor M2 and the sixth control transistor M8 are adjacent in the first direction X, and the second control transistor M2 is located on a side of the sixth control transistor M8 away from the fifth control transistor M7. The eighth control transistor M10 and the second control transistor M2 are adjacent in the first direction X, and the eighth control transistor M10 is located on a side of the second control transistor M2 away from the sixth control transistor M8. In the first direction X, the first control transistor M1 is located between the second control transistor M2 and the eighth control transistor M10. The third control transistor M5 is adjacent to the first control transistor M1 in the first direction X, and the third control transistor M5 is located on a side of the first control transistor M1 away from the second control transistor M2 .

[0145] In some exemplary embodiments, as shown in FIG5 , within a plane parallel to the display substrate, the first de-noising control transistor M11 and the second de-noising control transistor M12 are adjacent in the second direction Y. The first de-noising control transistor M11 and the second de-noising control transistor M12 are adjacent to the second power line PL2b in the first direction X. The first de-noising control transistor M11 and the fourth de-noising control transistor M14 are adjacent in the first direction X, and the fourth de-noising control transistor M14 is located on a side of the first de-noising control transistor M11 away from the second power line PL2b. The third capacitor C3 and the second de-noising control transistor M12 are adjacent in the first direction X, and the third capacitor C3 is located on a side of the second de-noising control transistor M12 away from the second power line PL2b. The third de-noising control transistor M13 and the third capacitor C3 are adjacent in the first direction X, and the third de-noising control transistor M13 is located on a side of the third capacitor C3 away from the second de-noising control transistor M12. The fourth capacitor C4 and the fourth noise reduction control transistor M14 are adjacent in the first direction X and are located on a side of the fourth noise reduction control transistor M14 away from the first noise reduction control transistor M11. The third noise reduction control transistor M13 and the fourth capacitor C4 are adjacent in the second direction Y.

[0146] In some exemplary embodiments, as shown in FIG5 , within a plane parallel to the display substrate, the third output transistor M15 and the fourth output transistor M16 are adjacent to each other in the second direction Y. The third output transistor M15 and the fourth capacitor C4 are adjacent to each other in the first direction X, and the third output transistor M15 is located on a side of the fourth capacitor C4 away from the fourth de-noising control transistor M14. The fourth output transistor M16 and the third de-noising control transistor M13 are adjacent to each other in the first direction X, and the fourth output transistor M16 is located on a side of the third de-noising control transistor M13 away from the third capacitor C3.

[0147] In some exemplary embodiments, as shown in FIG5 , within a plane parallel to the display substrate, in a first direction X, the first output transistor M3 and the second output transistor M4 of the first output sub-circuit, and the first to eighth control transistors M1 to M10 of the first node control sub-circuit are located between the first power line PL1a and the fourth power line PL2a. In the first direction X, the first, second, and fourth de-noising control transistors M11, M12, and M14 of the de-noising control sub-circuit are located between the third power line PL1b and the second power line PL2b. The third de-noising control transistor M13 of the de-noising control sub-circuit, and the third and fourth output transistors M15 and M16 of the second and third output sub-circuit are located between the third power line PL1b and the second group of clock signal lines in the first direction X. The first, second, and third clock signal lines GCK1, GCK2, and GCK3 are located between the first power line PL1a and the second power line PL2b in the first direction X.

[0148] In some exemplary embodiments, as shown in FIG6 , within a plane perpendicular to the display substrate, the non-display region of the display substrate may include: a base substrate 60, a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base substrate 60. Specifically, a first insulating layer 61 is disposed between the base substrate 60 and the first semiconductor layer, a second insulating layer 62 is disposed between the first conductive layer and the first semiconductor layer, a third insulating layer 63 is disposed between the first conductive layer and the second conductive layer, and a fourth insulating layer 64 is disposed between the second conductive layer and the third conductive layer. A fifth insulating layer 65 and a sixth insulating layer 66 are disposed between the third conductive layer and the fourth conductive layer. The fifth insulating layer 65 is located on the side of the sixth insulating layer 66 closest to the base substrate 60. In some examples, the first to fifth insulating layers 61 to 65 are inorganic insulating layers, and the sixth insulating layer 66 is an organic insulating layer. However, this embodiment is not limited to this.

[0149] FIG7A is a top view of a shift register unit after forming the first semiconductor layer according to at least one embodiment of the present disclosure. As shown in FIG5 to FIG7A, the first semiconductor layer in the non-display area includes at least: active layers of multiple transistors of the shift register unit. For example, the first semiconductor layer includes at least: an active layer 110 of a first control transistor M1, an active layer 120 of a second control transistor M2, an active layer 150 of a third control transistor M5, an active layer 160 of a fourth control transistor M6, an active layer 170 of a fifth control transistor M7, an active layer 180 of a sixth control transistor M8, an active layer 190 of a seventh control transistor M9, an active layer 200 of an eighth control transistor M10, an active layer 130 of a first output transistor M3, and an active layer 140 of a first output transistor M4. -1 and 130-2, the active layers 140-1 and 140-2 of the second output transistor M4, the active layer 210 of the first de-noising control transistor M11, the active layer 220 of the second de-noising control transistor M12, the active layer 230 of the third de-noising control transistor M13, the active layer 240 of the fourth de-noising control transistor M14, the active layers 250-1 and 250-2 of the third output transistor M15, and the active layers 260-1 and 260-2 of the fourth output transistor M16.

[0150] In some exemplary embodiments, in the first direction X, the active layer 160 of the fourth control transistor M6 is located between the active layer 140-2 of the second output transistor M4 and the active layer 190 of the seventh control transistor M9; the active layer 170 of the fifth control transistor M7 is located between the active layer 130-2 of the first output transistor M3 and the active layer 180 of the sixth control transistor M8; the active layer 110 of the first control transistor M1 and the active layer 120 of the second control transistor M2 are located between the active layer 200 of the eighth control transistor M10 and the active layer 180 of the sixth control transistor M8; the active layer 230 of the third de-noising control transistor M13 is located between the active layer 220 of the second de-noising control transistor M12 and the active layer 260-1 of the fourth output transistor M16; and the active layer 240 of the fourth de-noising control transistor M14 is located between the active layer 210 of the first de-noising control transistor M11 and the active layer 250-1 of the third output transistor M15.

[0151] In some exemplary embodiments, the active layer 130-1 of the first output transistor M3 and the active layer 140-1 of the second output transistor M4 are integrally formed, for example, in the shape of a rectangle with a notch. The active layer 130-2 of the first output transistor M3 and the active layer 140-2 of the second output transistor M4 are integrally formed, for example, in the shape of a rectangle with a notch. The active layer 160 of the fourth control transistor M6 and the active layer 170 of the fifth control transistor M7 are integrally formed, for example, in the shape of a rectangle. The active layer 110 of the first control transistor M1, the active layer 120 of the second control transistor M2, and the active layer 200 of the eighth control transistor M10 are integrally formed. The active layer 210 of the first de-noising control transistor M11 and the active layer 220 of the second de-noising control transistor M12 are integrally formed. The active layer 250-1 of the third output transistor M15 and the active layer 260-1 of the fourth output transistor M16 are an integrated structure, for example, in a rectangular shape; the active layer 250-2 of the third output transistor M15 and the active layer 260-2 of the fourth output transistor M16 are an integrated structure, for example, in a rectangular shape. However, this embodiment is not limited to this.

[0152] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and a plurality of doped regions. The channel region may be undoped with impurities and have semiconductor properties. The plurality of doped regions may be on both sides of the channel region and doped with impurities, thereby having conductivity. The impurities may vary depending on the type of transistor.

[0153] In some exemplary embodiments, the doped regions of the active layer may be interpreted as source electrodes or drain electrodes of transistors. For example, the source electrode of the first control transistor M1 may correspond to the first doped region 110b doped with impurities and located around the channel region 110a of the active layer 110, and the drain electrode of the first control transistor M1 may correspond to the second doped region 110c doped with impurities and located around the channel region 110a of the active layer 110. Furthermore, portions of the active layer between transistors may be interpreted as impurity-doped wiring, which may be used to electrically connect the transistors.

[0154] FIG7B is a top view of the shift register unit after the first conductive layer is formed in at least one embodiment of the present disclosure. As shown in FIG5 to FIG7B, the first conductive layer in the non-display area includes at least: control electrodes of multiple transistors of the shift register unit, and first electrodes of multiple capacitors. For example, the first conductive layer may include: a control electrode 113 of the first control transistor M1, a control electrode 123 of the second control transistor M2, a control electrode 153a and 153b of the third control transistor M5, a control electrode 163 of the fourth control transistor M6, a control electrode 173 of the fifth control transistor M7, a control electrode 183 of the sixth control transistor M8, a control electrode 193 of the seventh control transistor M9, a control electrode 203a and 203b of the eighth control transistor M10, control electrodes 133a, 133b and 133c of the first output transistor M3, a control electrode 143 of the second output transistor M4, a first de-noising control transistor M6, a control electrode 163 of the fourth control transistor M6, a control electrode 173 of the fifth control transistor M7, a control electrode 183 of the sixth control transistor M8, a control electrode 193 of the seventh control transistor M9, a control electrode 203a and 203b of the eighth control transistor M10, control electrodes 133a, 133b and 133c of the first output transistor M3, a control electrode 143 of the second output transistor M4, a control electrode 153b of the first control transistor M5, a control electrode 153b of the second control transistor M5, a control electrode 153b of the third control transistor M5, a control electrode 163 of the fourth control transistor M6, a control electrode 173 of the fifth control transistor M7, a control electrode 183 of the sixth control transistor M8, a control electrode 193 of the seventh control transistor M9, a control electrode 20 The control electrodes 213a and 213b of the transistor M11, the control electrode 223 of the second de-noising control transistor M12, the control electrode 233 of the third de-noising control transistor M13, the control electrodes 243a and 243b of the fourth de-noising control transistor M14, the control electrode 253 of the third output transistor M15, the control electrodes 263a, 263b and 263c of the fourth output transistor M16, the first electrode 301 of the first capacitor C1, the first electrode 302 of the second capacitor C2, the first electrode 303 of the third capacitor C3, the first electrode 304 of the fourth capacitor C4, the first connection electrode 501 and the second connection electrode 502.

[0155] In some exemplary embodiments, the first electrode 301 of the first capacitor C1, the control electrodes 133a, 133b, and 133c of the first output transistor M3, and the control electrode 183 of the sixth control transistor M8 may be an integrated structure. The first electrode 302 of the second capacitor C2, the control electrode 143 of the second output transistor M4, the control electrode 163 of the fourth control transistor M6, and the control electrode 173 of the fifth control transistor M7 may be an integrated structure. The control electrodes 113 of the first control transistor M1 and the control electrode 123 of the second control transistor M2 may be an integrated structure. The control electrodes 153a and 153b of the third control transistor M5 and the control electrode 223 of the second de-noising control transistor M12 may be an integrated structure. The control electrodes 213a and 213b of the first de-noising control transistor M11 and the control electrodes 243a and 243b of the fourth de-noising control transistor M14 may be an integrated structure. The first electrode 303 of the third capacitor C3 and the control electrode 233 of the third de-noising control transistor M13 may be an integrated structure. The first electrode 304 of the fourth capacitor C4 and the control electrode 253 of the third output transistor M15 can be an integrated structure. The control electrodes 263a, 263b, and 263c of the fourth output transistor M16 can be an integrated structure. The control electrode 193 of the seventh control transistor M9 of any shift register unit, as well as the control electrodes 203a and 203b of the eighth control transistor M10 of the previous shift register unit, and the first connection electrode 501 of the previous shift register unit can be an integrated structure. However, this embodiment is not limited to this.

[0156] In this exemplary embodiment, the third control transistor M5, the eighth control transistor M10, the first noise reduction control transistor M11, and the fourth noise reduction control transistor M14 may be dual-gate transistors, and the first output transistor M3 and the fourth output transistor M16 may be tri-gate transistors to prevent and reduce leakage current. However, this embodiment is not limited to this.

[0157] Figure 7C is a top view of the shift register unit after forming the second conductive layer according to at least one embodiment of the present disclosure. As shown in Figures 5 to 7C, the second conductive layer in the non-display area includes at least the second electrodes of the multiple capacitors of the shift register unit, the first output terminal, and the second output terminal. For example, the second conductive layer may include the second electrode 401 of the first capacitor C1, the second electrode 402 of the second capacitor C2, the second electrode 403 of the third capacitor C3, the second electrode 404 of the fourth capacitor C4, the first output terminal OUT1, the second output terminal OUT2, the third connection electrode 503, and the first connection line 701.

[0158] In some exemplary embodiments, the orthographic projection of the second electrode 401 of the first capacitor C1 on the substrate 60 overlaps with the orthographic projection of the first electrode 301 of the first capacitor C1 on the substrate 60. The orthographic projection of the second electrode 402 of the second capacitor C2 on the substrate 60 overlaps with the orthographic projection of the first electrode 302 of the second capacitor C2 on the substrate 60. The orthographic projection of the second electrode 403 of the third capacitor C3 on the substrate 60 overlaps with the orthographic projection of the first electrode 303 of the third capacitor C3 on the substrate 60. The orthographic projection of the second electrode 404 of the fourth capacitor C4 on the substrate 60 overlaps with the orthographic projection of the first electrode 304 of the fourth capacitor C4 on the substrate 60.

[0159] In some exemplary embodiments, the first output terminal OUT1 and the second output terminal OUT2 extend along a first direction X. The first output terminal OUT1 is located on a side of the third output transistor M15 away from the fourth output transistor M16 in the second direction Y, and the second output terminal OUT2 is located on a side of the third output transistor M15 away from the fourth capacitor C4 in the first direction X. The first connecting line 701 extends along the first direction X and is located between two adjacent stages of shift register units in the second direction Y.

[0160] FIG7D is a top view of a shift register unit after forming the fourth insulating layer according to at least one embodiment of the present disclosure. As shown in FIG5 to FIG7D , a plurality of vias are formed on the fourth insulating layer 64 in the non-display area. For example, the plurality of vias may include: a plurality of first vias K1 to K30, a plurality of second vias H1 to H17, and a plurality of third vias D1 to D10. The fourth insulating layer 64, the third insulating layer 63, and the second insulating layer 62 within the plurality of first vias K1 to K30 are etched away, exposing the surface of the first semiconductor layer. The fourth insulating layer 64 and the third insulating layer 63 within the plurality of second vias H1 to H17 are etched away, exposing the surface of the first conductive layer. The fourth insulating layer 64 within the plurality of third vias D1 to D10 is etched away, exposing the surface of the second conductive layer.

[0161] Figure 7E is a top view of the shift register unit after the third conductive layer is formed according to at least one embodiment of the present disclosure. As shown in Figures 5 to 7E, the third conductive layer in the non-display area includes at least: the first and second electrodes of the multiple transistors of the shift register unit, a first set of clock signal lines, a second set of clock signal lines, and multiple power lines. For example, the third conductive layer may include: a first electrode 111 and a second electrode 112 of the first control transistor M1, a first electrode 121 and a second electrode 122 of the second control transistor M2, a first electrode 151 and a second electrode 152 of the third control transistor M5, a first electrode 161 and a second electrode 162 of the fourth control transistor M6, a first electrode 171 and a second electrode 172 of the fifth control transistor M7, a first electrode 181 and a second electrode 182 of the sixth control transistor M8, a first electrode 191 and a second electrode 192 of the seventh control transistor M9, a first electrode 201 and a second electrode 202 of the eighth control transistor M10, a first electrode 131 and a second electrode 132 of the first output transistor M3, a first electrode 141 and a second electrode 142 of the second output transistor M4, a first electrode 211 and a second electrode 212 of the first de-noising control transistor M11, The first electrode 221 and the second electrode 222 of the second noise elimination control transistor M12, the first electrode 231 and the second electrode 232 of the third noise elimination control transistor M13, the first electrode 241 and the second electrode 242 of the fourth noise elimination control transistor M14, the first electrode 251 and the second electrode 252 of the third output transistor M15, the first electrode 261 and the second electrode 262 of the fourth output transistor M16, the initial signal line STV, the first power line PL1a, the third power line PL1b, the fourth power line PL2a, the second power line PL2b, the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCB1, the fifth clock signal line GCB2, the fourth connection electrode 504, the fifth connection electrode 505, the sixth connection electrode 506, and the second connection line 702.

[0162] In some exemplary embodiments, the fourth power line PL2a, the first electrode 141 of the second output transistor M4, the first electrode 161 of the fourth control transistor M6, and the first electrode 191 of the seventh control transistor M9 may be an integral structure. The second electrode 132 of the first output transistor M3 and the second electrode 142 of the second output transistor M4 may be an integral structure. The second electrode 162 of the fourth control transistor M6, the first electrode 171 of the fifth control transistor M7, and the second electrode 182 of the sixth control transistor M8 may be an integral structure. The second electrode 112 of the first control transistor M1, the first electrode 121 of the second control transistor M2, and the second electrode 202 of the eighth control transistor M10 may be an integral structure. The second electrode 192 of the seventh control transistor M9 and the second electrode 152 of the third control transistor M5 may be an integral structure. The first power line PL1a, the first electrode 151 of the third control transistor M5, and the first electrode 181 of the sixth control transistor M8 may be an integral structure. The second power line PL2b, the first electrode 211 of the first de-noising control transistor M11, and the first electrode 241 of the fourth de-noising control transistor M14 may be an integral structure. The third power line PL1b, the first electrode 221 of the second noise reduction control transistor M12, and the first electrode 251 of the third output transistor M15 can be an integrated structure. The second electrode 212 of the first noise reduction control transistor M11 and the second electrode 222 of the second noise reduction control transistor M12 can be an integrated structure. The second electrode 252 of the third output transistor M15 and the second electrode 262 of the fourth output transistor M16 can be an integrated structure.

[0163] Figure 7F is a top view of the shift register unit after the fourth conductive layer is formed according to at least one embodiment of the present disclosure. As shown in Figures 5 to 7F, multiple vias are formed on the sixth insulating layer 66 in the non-display area. For example, the multiple vias may include: multiple fourth vias F1 to F3. The fifth insulating layer 65 and the sixth insulating layer 66 within the multiple fourth vias F1 to F3 are etched away, exposing the surface of the third conductive layer.

[0164] In some exemplary embodiments, the fourth conductive layer in the non-display area includes at least a connecting electrode. For example, the fourth conductive layer may include a seventh connecting electrode 507 and a third connecting line 703. Both the seventh connecting electrode 507 and the third connecting line 703 extend along the first direction X. The seventh connecting electrode 507 may be connected to the second electrode 172 of the fifth control transistor M7 via a fourth via F1, and may also be connected to the fifth connecting electrode 505 via a fourth via F2. The fifth connecting electrode 505 may be connected to the control electrode 263c of the fourth output transistor M16 via two second vias H17 arranged in a vertical row. The third connecting line 703 may be connected to the second connecting line 702 via a fourth via F3, and the second connecting line 702 may be connected to the first connecting line 701 via a third via D3.

[0165] In some examples, the gate drive circuit of this embodiment can be configured to provide scan signals and reset signals to the sub-pixels in the display area. In this embodiment, a light-emitting drive circuit can be provided on a side of the gate drive circuit away from the display area, configured to provide light-emitting control signals to the sub-pixels in the display area. The light-emitting drive circuit can include multiple cascaded shift register units. The output end of any stage of the shift register unit in the light-emitting drive circuit can be connected to the first connection line 701 and sequentially connected via the second connection line 702 and the third connection line 703 to transmit the light-emitting control signal to the display area. However, this embodiment is not limited to this.

[0166] In some exemplary embodiments, the first control transistor M1 includes an active layer 110, a control electrode 113, a first electrode 111, and a second electrode 112. The active layer 110 includes a channel region 110a, a first doped region 110b, and a second doped region 110c. The control electrode 113 of the first control transistor M1 and the control electrode 123 of the second control transistor M2 are integrally formed. The control electrode 113 of the first control transistor M1 is connected to the first clock signal line GCK1 via two second vias H6 arranged in a vertical row. The first electrode 111 of the first control transistor M1 is connected to the first doped region 110b of the active layer 110 via three first vias K14 arranged side by side, and is also connected to the control electrode 193 of the seventh control transistor M9 via a second via H4. The second electrode 112 of the first control transistor M1 is connected to the second doped region 110c of the active layer 110 via six first vias K15 arranged in a 2*3 array. The second electrode 113 of the first control transistor M1 , the first electrode 121 of the second control transistor M2 , and the second electrode 202 of the eighth control transistor M10 are integrated into one structure.

[0167] In the embodiment of the present disclosure, “arranged side by side” may mean arranged in sequence along a first direction X, and “arranged vertically” may mean arranged in sequence along a second direction Y.

[0168] In some exemplary embodiments, the second control transistor M2 includes an active layer 120, a control electrode 123, a first electrode 121, and a second electrode 122. The active layer 120 includes a channel region 120a, a first doped region 120b, and a second doped region 120c. The active layer 120 of the second control transistor M2 is integrally formed with the active layer 110 of the first control transistor M1, and the first doped region 120b of the active layer 120 is connected to the second doped region 110c of the active layer 110. The second electrode 122 of the second control transistor M2 is connected to the second doped region 120c of the active layer 120 via two first vias K13 arranged in a vertical row, and is also connected to the control electrode 183 of the sixth control transistor M8 via two second vias H3 arranged in a vertical row.

[0169] In some exemplary embodiments, the third control transistor M5 includes an active layer 150, control electrodes 153a and 153b, a first electrode 151, and a second electrode 152. The active layer 150 includes channel regions 150a1, 150a2, and 150a3, a first doped region 150b, and a second doped region 150c. The control electrodes 153a and 153b of the third control transistor M5 are integrally connected to the control electrode 223 of the second noise reduction control transistor M12. The control electrodes 153a and 153b of the third control transistor M5 are connected to the third clock signal line GCK3 via two second vias H5 arranged vertically. The first electrode 151 of the third control transistor M5 is connected to the first doped region 150b of the active layer 150 via a first via K17. The first electrode 151 of the third control transistor M5 is integrally connected to the first power line PL1a. The second electrode 152 of the third control transistor M5 is connected to the second doped region 150c of the active layer 150 via a first via K16. The second electrode 152 of the third control transistor M5 and the second electrode 192 of the seventh control transistor M9 are integrated into one structure.

[0170] In some exemplary embodiments, the fourth control transistor M6 includes an active layer 160, a control electrode 163, a first electrode 161, and a second electrode 162. The active layer 160 includes a channel region 160a, a first doped region 160b, and a second doped region 160c. The active layer 160 of the fourth control transistor M6 and the active layer 170 of the fifth control transistor M7 are integrally formed, and the second doped region 160c of the active layer 160 is connected to the first doped region 170b of the active layer 170. The control electrode 163 of the fourth control transistor M6 is connected to the second electrode 192 of the seventh control transistor M9 via a second via H1. The control electrode 163 of the fourth control transistor M6, the control electrode 173 of the fifth control transistor M7, the control electrode 143 of the second output transistor M4, and the first electrode 302 of the second capacitor C2 may be integrally formed. The first electrode 161 of the fourth control transistor M6 is connected to the first doped region 160b of the active layer 160 via a first via K6. The first electrode 161 of the fourth control transistor M6, the first electrode 191 of the seventh control transistor M9, the first electrode 141 of the second output transistor M4, and the fourth power line PL2a form an integrated structure. The second electrode 162 of the fourth control transistor M6 is connected to the second doped region 160c of the active layer 160 via a first via K7. The second electrode 162 of the fourth control transistor M6, the first electrode 172 of the fifth control transistor M7, and the second electrode 182 of the sixth control transistor M8 form an integrated structure.

[0171] In some exemplary embodiments, the fifth control transistor M7 includes an active layer 170, a control electrode 173, a first electrode 171, and a second electrode 172. The active layer 170 includes a channel region 170a, a first doped region 170b, and a second doped region 170c. The second electrode 172 of the fifth control transistor M7 is connected to the second doped region 170c of the active layer 170 via a first via K8, and is also connected to the control electrode 183 of the sixth control transistor M6 via a second via H2.

[0172] In some exemplary embodiments, the sixth control transistor M8 includes an active layer 180, a control electrode 183, a first electrode 181, and a second electrode 182. The active layer 180 includes a channel region 180a, a first doped region 180b, and a second doped region 180c. The control electrode 183 of the sixth control transistor M8, the control electrodes 133a, 133b, and 133c of the first output transistor M3, and the first electrode 301 of the first capacitor C1 may be integrally formed. The first electrode 181 of the sixth control transistor M8 is connected to the first doped region 180b of the active layer 180 via a first via K12. The first electrode 181 of the sixth control transistor M8 is integrally formed with the first power line PL1a. The second electrode 182 of the sixth control transistor M8 is connected to the second doped region 180c of the active layer 180 via a first via K11.

[0173] In some exemplary embodiments, the seventh control transistor M9 includes an active layer 190, a control electrode 193, a first electrode 191, and a second electrode 192. The active layer 190 includes a channel region 190a, a first doped region 190b, and a second doped region 190c. The first electrode 191 of the seventh control transistor M9 is connected to the first doped region 190b of the active layer 190 via a first via K9, and the second electrode 192 is connected to the second doped region 190c of the active layer 190 via a first via K10. The control electrode 193 of the seventh control transistor M9 of any shift register unit is integrally structured with the control electrodes 203a and 203b of the eighth control transistor M10 of the previous shift register unit and the first connection electrode 501 of the previous shift register unit. In this way, the first output signal of the shift register unit of the current level is transmitted to the input of the shift register unit of the next level. The first connection electrode 501 is connected to the second electrode 132 of the first output transistor M3 through two second via holes H10 arranged side by side.

[0174] In some exemplary embodiments, the eighth control transistor M10 includes an active layer 200, control electrodes 203a and 203b, a first electrode 201, and a second electrode 202. The active layer 200 includes channel regions 200a1, 200a2, and 200a3, a first doped region 200b, and a second doped region 200c. The active layer 200 of the eighth control transistor M10 is integrally formed with the active layer 110 of the first control transistor M1, and the second doped region 200c of the active layer 200 is connected to the second doped region 110c of the active layer 110. The control electrodes 203a and 203b of the eighth control transistor M10 are integrally formed and can be connected to the sixth connection electrode 506 via a second via H11. The sixth connection electrode 506 can be connected to the first output terminal OUT1 via a third via D4. The first electrode 201 of the eighth control transistor M10 is connected to the first doped region 200b of the active layer 200 through a first via K18, and is further connected to the second connection electrode 502 through a second via H7. The second connection electrode 502 is connected to the first electrode 131 of the first output transistor M3 through a second via H8, and is further connected to the second clock signal line GCK2 through two second vias H9 arranged in a vertical row.

[0175] In some exemplary embodiments, the first output transistor M3 includes active layers 130-1 and 130-2, control electrodes 133a, 133b, and 133c, a first electrode 131, and a second electrode 132. The active layer 130-1 includes channel regions 130-1a1, 130-1a2, and 130-1a3, a first doping region 130-1b, a second doping region 130-1c, a third doping region 130-1d, and a fourth doping region 130-1e. The active layer 130-2 includes channel regions 130-2a1, 130-2a2, and 130-2a3, a first doping region 130-2b, a second doping region 130-2c, a third doping region 130-2d, and a fourth doping region 130-2e. The active layer 130-1 of the first output transistor M3 and the active layer 140-1 of the second output transistor M4 are integrally formed, and the fourth doping region 130-1e of the active layer 130-1 is connected to the second doping region 140-1c of the active layer 140-1. The active layer 130-2 of the first output transistor M3 and the active layer 140-2 of the second output transistor M4 are integrally formed, and the fourth doping region 130-2e of the active layer 130-2 is connected to the second doping region 140-2c of the active layer 140-1.

[0176] The first electrode 131 of the first output transistor M3 is connected to the first doping region 130-1b of the active layer 130-1 through a plurality of first via holes K5 (for example, seven first via holes K5) arranged side by side, and is connected to the first doping region 130-2b of the active layer 130-2 through a plurality of first via holes K5 (for example, seven first via holes K5) arranged side by side, and is also connected to the third doping region 130-1d of the active layer 130-1 through a plurality of first via holes K3 (for example, seven first via holes K3) arranged side by side, and is connected to the third doping region 130-2d of the active layer 130-2 through a plurality of first via holes K3 (for example, seven first via holes K3) arranged side by side, and is also connected to the second connection electrode 502 through a second via hole H8.

[0177] The second electrode 132 of the first output transistor M3 is connected to the second doping region 130-1c of the active layer 130-1 through a plurality of first via holes K4 (e.g., seven first via holes K4) arranged side by side, and to the second doping region 130-2c of the active layer 130-2 through a plurality of first via holes K4 (e.g., seven first via holes K4) arranged side by side. It is also connected to the fourth doping region 130-1e of the active layer 130-1 through a plurality of first via holes K2 (e.g., seven first via holes K2) arranged side by side, and to the fourth doping region 130-2e of the active layer 130-2 through a plurality of first via holes K2 (e.g., seven first via holes K2) arranged side by side. The second electrode 132 of the first output transistor M3 is also connected to the second electrode 302 of the second capacitor C2 through three third via holes D2 arranged in a vertical row, and is also connected to the first connection electrode 501 through two second via holes H10 arranged side by side. The second electrode 132 of the first output transistor M3 and the second electrode 142 of the second output transistor M4 are an integral structure.

[0178] In some exemplary embodiments, the second output transistor M4 includes active layers 140-1 and 140-2, a control electrode 143, a first electrode 141, and a second electrode 142. The active layer 140-1 includes a channel region 140-1a, a first doping region 140-1b, and a second doping region 140-1c. The active layer 140-2 includes a channel region 140-2a, a first doping region 140-2b, and a second doping region 140-2c. The first electrode 141 of the second output transistor M4 is connected to the first doping region 140-1b of the active layer 140-1 via a plurality of first vias K1 arranged side by side (e.g., six first vias K1), and is connected to the first doping region 140-2b of the active layer 140-2 via a plurality of first vias K1 arranged side by side (e.g., six first vias K1).

[0179] In some exemplary embodiments, the first capacitor C1 includes a first electrode 301 and a second electrode 401. The first electrode 301 is integrally connected to the control electrodes 133a1, 133a2, and 133a3 of the first output transistor M3. The second electrode 401 is connected to the second electrode 132 of the first output transistor M3 via three third vias D2 arranged in a vertical row. The second capacitor C2 includes a first electrode 302 and a second electrode 402. The first electrode 302 is integrally connected to the control electrode 143 of the second output transistor M4. The second electrode 402 is connected to the fourth power line PL2a via a third via D1.

[0180] In some exemplary embodiments, the first de-noising control transistor M11 includes an active layer 210, control electrodes 213a and 213b, a first electrode 211, and a second electrode 212. The active layer 210 includes channel regions 210a1, 210a2, and 210a3, a first doped region 210b, and a second doped region 210c. The active layer 210 of the first de-noising control transistor M11 and the active layer 220 of the second de-noising control transistor M12 are integrally formed, and the second doped region 210c of the active layer 210 is connected to the second doped region 220c of the active layer 220. The control electrodes 213a and 213b of the first de-noising control transistor M11 and the control electrodes 243a and 243b of the fourth de-noising control transistor M14 are integrally formed and connected to the fourth connection electrode 504 via a second via H16. The fourth connection electrode 504 may be connected to the first output terminal OUT1 via a third via D5. The first electrode 211 of the first de-noising control transistor M11 is connected to the first doped region 210b of the active layer 210 via a first via K21. The second electrode 212 of the second de-noising control transistor M11 is connected to the second doped region 210c of the active layer 210 via four first vias K20 arranged in a 2x2 array. It is also connected to the first electrode 303 of the third capacitor C3 via a second via H12. The first electrode 211 of the first de-noising control transistor M11 and the first electrode 241 of the fourth de-noising control transistor M14 are integrally formed. The second electrode 212 of the first de-noising control transistor M11 and the second electrode 222 of the second de-noising control transistor M12 are integrally formed.

[0181] In some exemplary embodiments, the second noise reduction control transistor M12 includes an active layer 220, a control electrode 223, a first electrode 221, and a second electrode 222. The active layer 220 includes a channel region 220a, a first doped region 220b, and a second doped region 220c. The first electrode 221 of the second noise reduction control transistor M12 is connected to the first doped region 220b of the active layer 220 via two first vias K19 arranged side by side.

[0182] In some exemplary embodiments, the third noise reduction control transistor M13 includes an active layer 230, a control electrode 233, a first electrode 231, and a second electrode 232. The active layer 230 includes a channel region 230a, a first doped region 230b, and a second doped region 230c. The control electrode of the third noise reduction control transistor M13 and the first electrode 303 of the third capacitor C3 are integrally formed. The first electrode 231 of the third noise reduction control transistor M13 is connected to the first doped region 230b of the active layer 230 via two first vias K24 arranged side by side, and is also connected to the first electrode 303 of the third capacitor C3 via two second vias H13 arranged side by side. The second electrode 232 of the third noise reduction control transistor M13 is connected to the second doped region 230c of the active layer 230 via two first vias K25 arranged side by side, and is also connected to the first electrode 304 of the fourth capacitor C4 via two second vias H14 arranged side by side.

[0183] In some exemplary embodiments, the fourth noise reduction control transistor M14 includes an active layer 240, control electrodes 243a and 243b, a first electrode 241, and a second electrode 242. The active layer 240 includes channel regions 240a1, 240a2, and 240a3, a first doped region 240b, and a second doped region 240c. The first electrode 241 of the fourth noise reduction control transistor M14 is connected to the first doped region 240b of the active layer 240 via a first via K22. The second electrode 242 of the fourth noise reduction control transistor M14 is connected to the second doped region 240c of the active layer 240 via a first via K23, and is also connected to the first electrode 304 of the fourth capacitor C4 via a second via H15.

[0184] In some exemplary embodiments, the third output transistor M15 includes active layers 250-1 and 250-2, a control electrode 253, a first electrode 251, and a second electrode 252. The active layer 250-1 includes a channel region 250-1a, a first doping region 250-1b, and a second doping region 250-1c. The active layer 250-2 includes a channel region 250-2a, a first doping region 250-2b, and a second doping region 250-2c. The active layer 250-1 of the third output transistor M15 and the active layer 260-1 of the fourth output transistor M16 are integrally formed, and the second doping region 250-1c of the active layer 250-1 is connected to the fourth doping region 260-1e of the active layer 260-1. The active layer 250-2 of the third output transistor M15 and the active layer 260-2 of the fourth output transistor M16 are integrally formed, and the second doped region 250-2c of the active layer 250-2 is connected to the fourth doped region 260-2e of the active layer 260-2. The control electrode 253 of the third output transistor M15 and the first electrode 303 of the fourth capacitor C4 are integrally formed.

[0185] The first electrode 251 of the third output transistor M15 is connected to the first doped region 250-1b of the active layer 250-1 through a plurality of first via holes K30 (e.g., four first via holes K30) arranged side by side. It is also connected to the first doped region 250-2b of the active layer 250-2 through a plurality of first via holes K30 (e.g., four first via holes K30) arranged side by side. The first electrode 251 of the third output transistor M15 is integrally formed with the third power line PL1b.

[0186] The second electrode 252 of the third output transistor M15 is connected to the second doping region 250-1c of the active layer 250-1 through a plurality of first via holes K29 (e.g., four first via holes K29) arranged side by side. It is also connected to the second doping region 250-2c of the active layer 250-2 through a plurality of first via holes K29 (e.g., four first via holes K29) arranged side by side. The second electrode 252 of the third output transistor M15 and the second electrode 262 of the fourth output transistor M16 are integrally structured.

[0187] In some exemplary embodiments, the fourth output transistor M16 includes active layers 260-1 and 260-2, control electrodes 263a, 263b, and 263c, a first electrode 261, and a second electrode 262. The active layer 260-1 includes channel regions 260-1a1, 260-1a2, and 260-1a3, a first doping region 260-1b, a second doping region 260-1c, a third doping region 260-1d, and a fourth doping region 260-1e. The active layer 260-2 includes channel regions 260-2a1, 260-2a2, and 260-2a3, a first doping region 260-2b, a second doping region 260-2c, a third doping region 260-2d, and a fourth doping region 260-2e.

[0188] The control electrodes 263a, 263b, and 263c of the fourth output transistor M16 are integrally structured and connected to the fifth connection electrode 505 via two second via holes H17 arranged in a vertical row. The fifth connection electrode 505 is connected to the sixth connection electrode 506 via a fourth via hole F2. The sixth connection electrode 506 is connected to the second electrode 172 of the fifth control transistor M7 via a fourth via hole F1.

[0189] The first electrode 261 of the fourth output transistor M16 is connected to the first doped region 260-1b of the active layer 260-1 through a plurality of first via holes K26 (e.g., four first via holes K26) arranged side by side, and to the first doped region 260-2b of the active layer 260-2 through a plurality of first via holes K26 (e.g., four first via holes K26) arranged side by side. It is also connected to the third doped region 260-1d of the active layer 260-1 through a plurality of first via holes K28 (e.g., four first via holes K28) arranged side by side, and to the third doped region 260-2d of the active layer 260-2 through a plurality of first via holes K28 (e.g., four first via holes K28) arranged side by side. The first electrode 261 of the fourth output transistor M16 is also connected to the third connection electrode 503 through two third via holes D8 arranged side by side. The third connection electrode 503 is connected to the fourth clock signal line GCB1 through two third via holes D9 arranged in a vertical row.

[0190] The second electrode 262 of the fourth output transistor M16 is connected to the second doped region 260-1c of the active layer 260-1 through a plurality of first via holes K27 (e.g., four first via holes K27) arranged side by side, and is connected to the second doped region 260-2c of the active layer 260-2 through a plurality of first via holes K27 (e.g., four first via holes K27) arranged side by side. The second electrode 262 of the fourth output transistor M16 is connected to the second output terminal OUT2 through two third via holes D10 arranged in a vertical row.

[0191] In some exemplary embodiments, the third capacitor C3 includes a first electrode 303 and a second electrode 403. The first electrode 303 is connected to the first electrode 231 of the third de-noising control transistor M13 and the second electrode 222 of the second de-noising control transistor M12. The second electrode 403 is connected to the first clock signal line GCK1 via two third vias D6 arranged in a vertical row. The fourth capacitor C4 includes a first electrode 304 and a second electrode 404. The first electrode 304 is connected to the second electrode 232 of the third de-noising control transistor M13 and the second electrode 242 of the fourth de-noising control transistor M14. The second electrode 404 is connected to the third power line PL1b via two third vias D7 arranged in a vertical row.

[0192] In some exemplary embodiments, as shown in FIG5 to FIG7F , the control electrode 113 of the first control transistor M1 of the 6n+1-th stage shift register unit can be connected to the first clock signal line GCK1 via a second via, and the second electrode 403 of the third capacitor C3 can be connected to the first clock signal line GCK1 via a third via. The control electrode of the third control transistor M5 and the control electrode of the second de-noising control transistor M12 are integrally structured and can be connected to the third clock signal line GCK3 via a second via. The second connection electrode 502 is connected to the second clock signal line GCK2, and the second connection electrode 502 is connected to the first electrode 201 of the eighth control transistor M10 and the first electrode 131 of the first output transistor M3. The first electrode 261 of the fourth output transistor M16 is connected to the fourth clock signal line GCB1 via a third connection electrode 503.

[0193] In some exemplary embodiments, as shown in Figures 5 to 7F, the control electrode 113 of the first control transistor M1 of the 6n+2-stage shift register unit can be connected to the second clock signal line GCK2 through a second via, and the second electrode 403 of the third capacitor C3 can be connected to the second clock signal line GCK2 through a second via; the control electrode of the third control transistor M5 and the control electrode of the second noise reduction control transistor M12 are an integrated structure and can be connected to the first clock signal line GCK1 through a second via; the second connection electrode 502 can be connected to the third clock signal line GCK3, and the second connection electrode 502 is connected to the first electrode 201 of the eighth control transistor M10 and the first electrode 131 of the first output transistor M3; the first electrode 261 of the fourth output transistor M16 is connected to the fifth clock signal line GCB2 through the third connection electrode 503.

[0194] In this exemplary embodiment, combined with the cascade relationship of the shift register units shown in Figure 4 and the structure of the shift register shown in Figures 5 to 7F, the connection method between each level of shift register units and the first group of clock signal lines and the second group of clock signal lines can be determined, so it is not repeated here.

[0195] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "composition process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more of spray coating and spin coating, and etching can be carried out by any one or more of dry etching and wet etching. "Thin film" refers to a thin film made by a deposition or coating process on a substrate of a certain material. If the "thin film" does not require a composition process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a composition process during the entire production process, it is called a "thin film" before the composition process and a "layer" after the composition process. The "layer" after the composition process contains at least one "pattern".

[0196] As used in this disclosure, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary of the projection of A, or that the boundary of the projection of A overlaps the boundary of the projection of B.

[0197] The manufacturing process of the display substrate of this exemplary embodiment includes the following steps.

[0198] (1) Provide a substrate.

[0199] In some exemplary embodiments, the substrate 60 may be a rigid substrate or a flexible substrate. The rigid substrate may include one or more of glass and metal foil. The flexible substrate may include one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0200] (2) Forming a first semiconductor layer pattern.

[0201] In some exemplary embodiments, a first insulating film and a first semiconductor film are sequentially deposited on a base substrate 60, and the first semiconductor film is patterned by a patterning process to form a first insulating layer 61 covering the entire base substrate 60, and a first semiconductor layer pattern disposed on the first insulating layer 61, as shown in FIG7A . The first semiconductor layer pattern includes at least: an active layer of multiple transistors (e.g., transistors M1 to M16) in the shift register unit. The active layer may include at least one channel region and multiple doped regions. The channel region may be undoped with impurities and have semiconductor properties. The doped region is doped with impurities and therefore has conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor film may be polycrystalline silicon.

[0202] (3) Forming a first conductive layer pattern.

[0203] In some exemplary embodiments, a second insulating film and a first conductive film are sequentially deposited on the base substrate 60 having the aforementioned pattern formed thereon, and the first conductive film is patterned through a patterning process to form a second insulating layer 62 covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 62, as shown in FIG7B . In some examples, the first conductive layer pattern may include: control electrodes of multiple transistors (e.g., transistors M1 to M16) of the shift register unit, first electrodes of multiple capacitors (e.g., first capacitor C1 to fourth capacitor C4) of the shift register unit, and multiple connection electrodes (e.g., first connection electrode 501 and second connection electrode 502).

[0204] (4) Forming a second conductive layer pattern.

[0205] In some exemplary embodiments, a third insulating film and a second conductive film are sequentially deposited on the base substrate 60 having the aforementioned pattern formed thereon. The second conductive film is then patterned through a patterning process to form a third insulating layer 63 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 63, as shown in FIG7C . In some examples, the second conductive layer pattern may include: second electrodes of multiple capacitors (e.g., first capacitor C1 to fourth capacitor C4) of the shift register unit, a first output terminal OUT1, a second output terminal OUT2, and a connecting electrode (e.g., third connecting electrode 503).

[0206] (5) Forming a fourth insulating layer pattern.

[0207] In some exemplary embodiments, a fourth insulating film is deposited on the base substrate 60 having the aforementioned pattern formed thereon, and the fourth insulating film is patterned through a patterning process to form a pattern of a fourth insulating layer 64 covering the second conductive layer, as shown in FIG7D . In some examples, a plurality of vias are formed in the fourth insulating layer 64. The plurality of vias include at least: a plurality of first vias K1 to K30, a plurality of second vias H1 to H17, and a plurality of third vias D1 to D10. The fourth insulating layer 64, the third insulating layer 63, and the second insulating layer 62 within the plurality of first vias K1 to K30 are etched away, exposing the surface of the first semiconductor layer. The fourth insulating layer 64 and the third insulating layer 63 within the plurality of second vias H1 to H17 are etched away, exposing the surface of the first conductive layer. The fourth insulating layer 64 within the plurality of third vias D1 to D10 is etched away, exposing the surface of the second conductive layer.

[0208] (6) Forming a third conductive layer pattern.

[0209] In some exemplary embodiments, a third conductive film is deposited on the base substrate 60 having the aforementioned pattern formed thereon, and the third conductive film is patterned through a patterning process to form a third conductive layer pattern on the fourth insulating layer 64, as shown in FIG7E . In some examples, the third conductive layer pattern may include: first and second electrodes of a plurality of transistors (e.g., transistors M1 to M16) of a shift register unit; a first group of clock signal lines (e.g., including a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3); a second group of clock signal lines (e.g., including a fourth clock signal line GCB1 and a fifth clock signal line GCB2); a plurality of power lines (e.g., a first power line PL1a, a fourth power line PL2a, a third power line PL1b, and a second power line PL2b); and connection electrodes (e.g., a fourth connection electrode 504, a fifth connection electrode 505, and a sixth connection electrode 506).

[0210] (7) Forming patterns of the fifth insulating layer and the sixth insulating layer.

[0211] In some exemplary embodiments, a fifth insulating film 65 is deposited on the patterned base substrate 60. A sixth insulating film is then applied. The sixth insulating film is masked, exposed, and developed to form a pattern in the sixth insulating layer 66. Subsequently, the fifth insulating film is patterned to form a pattern in the fifth insulating layer 65. In some examples, the sixth insulating layer 66 includes a plurality of vias. For example, the plurality of vias may include a plurality of fourth vias F1 to F3. The fifth insulating layer 65 and the sixth insulating layer 66 within the plurality of fourth vias F1 to F3 are etched away, exposing the surface of the third conductive layer.

[0212] (8) Forming a fourth conductive layer pattern.

[0213] In some exemplary embodiments, a fourth conductive film is deposited on the base substrate 60 having the aforementioned pattern formed thereon, and the fourth conductive film is patterned through a patterning process to form a fourth conductive layer pattern on the sixth insulating layer 66, as shown in FIG7F . In some examples, the fourth conductive layer pattern includes at least connecting electrodes, such as the seventh connecting electrode 507 and the third connecting line 703.

[0214] In some exemplary embodiments, while forming a shift register unit in a non-display area, a pixel circuit can be formed in a display area. For example, the first semiconductor layer in the display area can include an active layer of a transistor of a pixel driving circuit, the first conductive layer in the display area can include a control electrode of the transistor of the pixel driving circuit and a first electrode of a storage capacitor, the second conductive layer in the display area can include at least a second electrode of the storage capacitor of the pixel driving circuit, the third conductive layer in the display area can include at least a first electrode and a second electrode of the transistor of the pixel driving circuit, and the fourth conductive layer in the display area can include at least a connecting electrode between the pixel driving circuit and the anode of the light-emitting element. After forming the first conductive layer, a second semiconductor layer can be formed in the display area, and an insulating layer is provided between the second semiconductor layer and the first conductive layer. The material of the second semiconductor thin film can be a metal oxide, for example, IGZO. However, this embodiment does not limit the position of the second semiconductor layer.

[0215] In some exemplary embodiments, after forming the fourth conductive layer, a seventh insulating layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer and an encapsulation layer pattern may be formed in sequence in the display area. In some examples, a seventh insulating film is coated on the substrate base having the aforementioned pattern formed thereon, and the seventh insulating layer pattern is formed by masking, exposing and developing the seventh insulating film. Subsequently, an anode film is deposited on the substrate base having the display area having the aforementioned pattern formed thereon, and the anode film is patterned by a composition process to form an anode pattern on the seventh insulating layer. Then, a pixel definition film is coated on the substrate base having the aforementioned pattern formed thereon, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed by masking, exposing and developing processes. The pixel definition layer is formed in each sub-pixel in the display area, and the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode. Subsequently, an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned by a composition process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer and the second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material. In some possible implementations, the cathode may be connected to the second power line in various ways, such as laser drilling.

[0216] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer 61, the second insulating layer 62, the third insulating layer 63, the fourth insulating layer 64, and the fifth insulating layer 65 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The sixth insulating layer 66 and the seventh insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The first insulating layer 61 can be referred to as a buffer layer. The first insulating layer 61 is configured to improve the water and oxygen resistance of the base substrate 60; the second insulating layer 62 and the third insulating layer 63 are referred to as gate insulating (GI) layers, the fourth insulating layer 64 is referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer 65 is referred to as a passivation (PVX) layer; the sixth insulating layer 66 and the seventh insulating layer are referred to as planar layers. The pixel definition layer can be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. However, this embodiment is not limited to this. For example, the anode can be made of a reflective material such as a metal, and the cathode can be made of a transparent conductive material.

[0217] The structure and fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or reduced as needed. For example, the fourth conductive layer may not be provided. For another example, the order of the multiple clock signal lines in the first group of clock signal lines may be changed, and the order of the multiple clock signal lines in the second group of clock signal lines may be changed. However, this embodiment is not limited to this.

[0218] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0219] The display substrate provided by this exemplary embodiment is provided with a first output circuit and a second output circuit sharing a clock signal line, and a first group of clock signal lines, a first power line and a second power line are provided between the first output circuit and the second output circuit. This can improve the layout density of the shift register unit, which is conducive to achieving a narrow frame; moreover, it can reduce the load on the clock signal line, which is conducive to improving the performance of the shift register unit.

[0220] In some exemplary embodiments, the gate drive circuit includes a plurality of cascaded shift register units. The first output terminal of the 2k-1th shift register unit is connected to the input terminal of the 2k+1th shift register unit, and the input terminal of the first shift register unit is connected to the first initial signal line STVO. The first output terminal of the 2kth shift register unit is connected to the input terminal of the 2k+2th shift register unit, and the input terminal of the second shift register unit is connected to the second initial signal line STVE. k is a positive integer.

[0221] In some exemplary embodiments, the first group of clock signal lines includes a first grouped clock signal line and a second grouped clock signal line, and the second group of clock signal lines includes a third grouped clock signal line and a fourth grouped clock signal line. The 2k-1th stage shift register unit is connected to the first grouped clock signal line and the third grouped clock signal line, and the 2kth stage shift register unit is connected to the second grouped clock signal line and the fourth grouped clock signal line.

[0222] In some exemplary embodiments, the first group of clock signal lines includes a first clock signal line GCKO1, a second clock signal line GCKO2, and a third clock signal line GCKO3. The second group of clock signal lines includes a sixth clock signal line GCKE1, a seventh clock signal line GCKE2, and an eighth clock signal line GCKE3. The third group of clock signal lines includes a fourth clock signal line GCBO1 and a fifth clock signal line GCBO2. The fourth group of clock signal lines includes a ninth clock signal line GCBE1 and a tenth clock signal line GCBE2.

[0223] In this exemplary embodiment, odd-numbered shift register units are sequentially cascaded and connected to the first and third grouped clock signal lines, while even-numbered shift register units are sequentially cascaded and connected to the second and fourth grouped clock signal lines. The gate drive circuit of this exemplary embodiment increases the number of clock signals and employs even-odd row drive, which increases charging time and ensures efficient pixel charging. This allows for application in high-frequency drive modes.

[0224] FIG8 is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG8 , the first clock terminal of the 12n+1th stage shift register unit is connected to the first clock signal line GCKO1, the second clock terminal is connected to the second clock signal line GCKO2, the third clock terminal is connected to the third clock signal line GCKO3, and the fourth clock terminal is connected to the fourth clock signal line GCBO1.

[0225] The first clock terminal of the 12n+3th stage shift register unit is connected to the second clock signal line GCKO2, the second clock terminal is connected to the third clock signal line GCKO3, the third clock terminal is connected to the first clock signal line GCKO1, and the fourth clock terminal is connected to the fifth clock signal line GCBO2.

[0226] The first clock terminal of the 12n+5th stage shift register unit is connected to the third clock signal line GCKO3, the second clock terminal is connected to the first clock signal line GCKO1, the third clock terminal is connected to the second clock signal line GCKO2, and the fourth clock terminal is connected to the fourth clock signal line GCBO1.

[0227] The first clock terminal of the 12n+7th stage shift register unit is connected to the first clock signal line GCKO1, the second clock terminal is connected to the second clock signal line GCKO2, the third clock terminal is connected to the third clock signal line GCKO3, and the fourth clock terminal is connected to the fifth clock signal line GCBO2.

[0228] The first clock terminal of the 12n+9th stage shift register unit is connected to the second clock signal line GCKO2, the second clock terminal is connected to the third clock signal line GCKO3, the third clock terminal is connected to the first clock signal line GCKO1, and the fourth clock terminal is connected to the fourth clock signal line GCBO1.

[0229] The first clock terminal of the 12n+11th shift register unit is connected to the third clock signal line GCKO3, the second clock terminal is connected to the first clock signal line GCKO1, the third clock terminal is connected to the second clock signal line GCKO2, and the fourth clock terminal is connected to the fifth clock signal line GCBO2.

[0230] The first clock terminal of the 12n+2-stage shift register unit is connected to the sixth clock signal line GCKE1, the second clock terminal is connected to the seventh clock signal line GCKE2, the third clock terminal is connected to the eighth clock signal line GCKE3, and the fourth clock terminal is connected to the ninth clock signal line GCBE1.

[0231] The first clock terminal of the 12n+4th stage shift register unit is connected to the seventh clock signal line GCKE2, the second clock terminal is connected to the eighth clock signal line GCKE3, the third clock terminal is connected to the sixth clock signal line GCKE1, and the fourth clock terminal is connected to the tenth clock signal line GCBE2.

[0232] The first clock terminal of the 12n+6th stage shift register unit is connected to the eighth clock signal line GCKE3, the second clock terminal is connected to the sixth clock signal line GCKE1, the third clock terminal is connected to the seventh clock signal line GCKE2, and the fourth clock terminal is connected to the ninth clock signal line GCBE1.

[0233] The first clock terminal of the 12n+8th stage shift register unit is connected to the sixth clock signal line GCKE1, the second clock terminal is connected to the seventh clock signal line GCKE2, the third clock terminal is connected to the eighth clock signal line GCKE3, and the fourth clock terminal is connected to the tenth clock signal line GCBE2.

[0234] The first clock terminal of the 12n+10th stage shift register unit is connected to the seventh clock signal line GCKE2, the second clock terminal is connected to the eighth clock signal line GCKE3, the third clock terminal is connected to the sixth clock signal line GCKE1, and the fourth clock terminal is connected to the ninth clock signal line GCBE1.

[0235] The first clock terminal of the 12n+12th stage shift register unit is connected to the eighth clock signal line GCKE3, the second clock terminal is connected to the sixth clock signal line GCKE1, the third clock terminal is connected to the seventh clock signal line GCKE2, and the fourth clock terminal is connected to the tenth clock signal line GCBE2, where n is a natural number.

[0236] The 12 shift register units of the gate driving circuit of this embodiment can serve as a minimum period repeating unit to drive 12 rows of sub-pixels.

[0237] FIG9 is a timing diagram of clock signals according to at least one embodiment of the present disclosure. As shown in FIG9 , the first clock signal provided by the first clock signal line GCKO1, the second clock signal provided by the second clock signal line GCKO2, the third clock signal provided by the third clock signal line GCKO3, the fourth clock signal provided by the fourth clock signal line GCBO1, the fifth clock signal provided by the fifth clock signal line GCBO2, the sixth clock signal provided by the sixth clock signal line GCKE1, the seventh clock signal provided by the seventh clock signal line GCKE2, the eighth clock signal provided by the eighth clock signal line GCKE3, the ninth clock signal provided by the ninth clock signal line GCBE1, and the tenth clock signal provided by the tenth clock signal line GCBE2 ​​are all pulse signals.

[0238] In some exemplary embodiments, as shown in FIG9 , the duty cycles of the first clock signal, the second clock signal, the third clock signal, the sixth clock signal, the seventh clock signal, and the eighth clock signal may be the same. The second clock signal is delayed by a first set time length (e.g., 2 hours) compared to the first clock signal, and the third clock signal is delayed by a first set time length (e.g., 2 hours) compared to the second clock signal line, so that the first clock signal, the second clock signal, and the third clock signal are not at a low voltage at the same time. The seventh clock signal is delayed by a first set time length (e.g., 2 hours) compared to the sixth clock signal, and the eighth clock signal is delayed by a first set time length (e.g., 2 hours) compared to the seventh clock signal line, so that the sixth clock signal, the seventh clock signal, and the eighth clock signal are not at a low voltage at the same time. The sixth clock signal is delayed by a second set time length (e.g., 1 hour) compared to the first clock signal, the seventh clock signal is delayed by a second set time length (e.g., 1 hour) compared to the second clock signal, and the eighth clock signal is delayed by a second set time length (e.g., 1 hour) compared to the third clock signal.

[0239] In some example embodiments, as shown in FIG. 9 , the second initial signal provided by the second initial signal line STVE is delayed by 1H compared to the first initial signal provided by the first initial signal line STVO.

[0240] In some exemplary embodiments, as shown in FIG9 , the duty cycles of the fourth clock signal, the fifth clock signal, the ninth clock signal, and the tenth clock signal may be the same. The duty cycle of the fourth clock signal may be less than the duty cycle of the first clock signal. The fourth clock signal and the fifth clock signal are not simultaneously at high voltages, and the ninth clock signal and the tenth clock signal are not simultaneously at high voltages. The ninth clock signal is delayed from the fourth clock signal by a second set time length (e.g., 1 hour), and the tenth clock signal is delayed from the fifth clock signal by a second set time length (e.g., 1 hour).

[0241] In some exemplary embodiments, the operation sequence of the first-stage shift register unit in FIG8 may include a first stage OS1, a second stage OS2, a third stage OS3, and a fourth stage OS4. The operation process of the second-stage shift register unit may include a first stage ES1, a second stage ES2, a third stage ES3, and a fourth stage ES4. The operation process of the four stages can be referred to the description of the operation process of the shift register unit in the aforementioned embodiment, and thus will not be repeated here.

[0242] FIG10 is another top view of a shift register unit according to at least one embodiment of the present disclosure. FIG10 illustrates the structure of the 12n+1 and 12n+2 shift register units (e.g., n=1) as examples. The following description mainly uses the structure of the 12n+1 shift register unit as an example.

[0243] Figure 11A is a top view of the shift register unit after forming the first semiconductor layer according to at least one embodiment of the present disclosure. Figure 11B is another top view of the shift register unit after forming the first conductive layer according to at least one embodiment of the present disclosure. Figure 11C is another top view of the shift register unit after forming the second conductive layer according to at least one embodiment of the present disclosure. Figure 11D is another top view of the shift register unit after forming the third conductive layer according to at least one embodiment of the present disclosure. Figure 11E is another top view of the shift register unit after forming the fourth conductive layer according to at least one embodiment of the present disclosure.

[0244] In some exemplary embodiments, as shown in FIG10 , within a plane parallel to the display substrate, in a first direction X, the second initial signal line STVE is located between the first initial signal line STVO and the fourth power line PL2a, the first group of clock signal lines is located between the first power line PL1a and the second power line PL2b, and the third power line PL1b is located between the second power line PL2b and the second group of clock signal lines. The first group of clock signal lines includes a first group of clock signal lines and a second group of clock signal lines. The first group of clock signal lines and the second group of clock signal lines are alternately arranged in the first direction X. In this example, the first group of clock signal lines includes a first clock signal line GCKO1, a second clock signal line GCKO2, and a third clock signal line GCKO3, and the second group of clock signal lines includes a sixth clock signal line GCKE1, a seventh clock signal line GCKE2, and an eighth clock signal line GCKE3. In the first direction D1 from the first power line PL1a to the second power line PL2b, the first clock signal line GCKO1, the sixth clock signal line GCKE1, the second clock signal line GCKO2, the seventh clock signal line GCKE2, the third clock signal line GCKO3, and the eighth clock signal line GCKE3 are arranged in sequence. The second group of clock signal lines includes a third group of clock signal lines and a fourth group of clock signal lines. The third group of clock signal lines includes a fourth clock signal line GCBO1 and a fifth clock signal line GCBO2, and the fourth group of clock signal lines includes a ninth clock signal line GCBE1 and a tenth clock signal line GCBE2. In the first direction D1 away from the second output circuit, the fourth clock signal line GCBO1, the ninth clock signal line GCBE1, the fifth clock signal line GCBO2, and the tenth clock signal line GCBE2 ​​are arranged in sequence. However, this embodiment is not limited to this. In some examples, the first and second group of clock signal lines can be arranged in sequence along the first direction, and the third and fourth group of clock signal lines can be arranged in sequence along the first direction.

[0245] In some exemplary embodiments, as shown in FIG11B , the first conductive layer in the non-display area includes at least the control electrodes of the plurality of transistors (e.g., transistors M1 to M16) of the shift register unit and the first electrodes of the plurality of capacitors (e.g., first capacitor C1 to fourth capacitor C4). The control electrodes 203 a and 203 b of the eighth control transistor M10 of any one stage of the shift register unit and the first connection electrode 501 may be integrally formed and not connected to the control electrode 193 of the seventh control transistor M9 of the next stage of the shift register unit.

[0246] In some exemplary embodiments, as shown in FIG11D , the third conductive layer in the non-display area may include: first and second electrodes of multiple transistors (e.g., transistors M1 to M16) of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, a plurality of power supply lines, and connection electrodes (e.g., an eighth connection electrode 508 and a ninth connection electrode 509). For example, the control electrode 193 of the seventh control transistor M9 of the 12n+1 stage shift register unit may be connected to the eighth connection electrode 508 via two second vias H18 arranged vertically, thereby being connected to the first output terminal OUT1 of the 12n-1 stage shift register unit via the eighth connection electrode 508. The first output terminal OUT1 of the 12n+1 stage shift register unit may be connected to another eighth connection electrode 508 via a third via D11, thereby being connected to the control electrode 193 of the seventh control transistor M9 of the 12n+3 stage shift register unit via the eighth connection electrode 508, thereby providing an input signal to the 12n+3 stage shift register unit. The control electrode 193 of the seventh control transistor M9 of the 12n+2th stage shift register unit can be connected to the ninth connection electrode 509 through two second via holes H19 arranged vertically, so as to be connected to the first output terminal OUT1 of the 12nth stage shift register unit through the ninth connection electrode 509 .

[0247] In some exemplary embodiments, as shown in FIG10 to FIG11E , the control electrode of the third control transistor M5 and the control electrode of the second noise reduction control transistor M12 of the 12n+1th stage shift register unit may be an integrated structure and connected to the third clock signal line GCKO3 via a second via. The second electrode of the third capacitor C3 is connected to the first clock signal line GCKO1 via a third via. The control electrode of the first control transistor M1 is connected to the first clock signal line GCKO1 via a second via. The second connection electrode connected to the first electrode of the eighth control transistor M10 may be connected to the second clock signal line GCKO2 via a second via. The second connection electrode is also connected to the first electrode of the first output transistor M3 via a second via. The first electrode of the fourth output transistor M16 is connected to the fourth clock signal line GCBO1 via a third connection electrode.

[0248] In some exemplary embodiments, as shown in FIG10 to FIG11E , the control electrode of the third control transistor M5 and the control electrode of the second noise reduction control transistor M12 of the 12n+2-stage shift register unit may be an integrated structure and connected to the eighth clock signal line GCKE3 via a second via. The second electrode of the third capacitor C3 is connected to the sixth clock signal line GCKE1 via a third via. The control electrode of the first control transistor M1 is connected to the sixth clock signal line GCKE1 via a second via. The second connection electrode connected to the first electrode of the eighth control transistor M10 may be connected to the seventh clock signal line GCKE2 via a second via. The second connection electrode is also connected to the first electrode of the first output transistor M3 via a second via. The first electrode of the fourth output transistor M16 is connected to the ninth clock signal line GCBE1 via a third connection electrode.

[0249] The cascade relationship of the shift register units of this embodiment can be referred to as shown in FIG8 . The remaining structures of the display substrate of this embodiment can be referred to the description of the aforementioned embodiments, and thus will not be described in detail here.

[0250] The embodiment of the present disclosure also provides a method for preparing a display substrate, which is used to prepare the display substrate as described above. The preparation method of this embodiment includes: providing a base substrate; forming a gate drive circuit in a non-display area. The gate drive circuit includes: a plurality of cascaded shift register units; the shift register unit is connected to at least one power line. The shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In the first direction, the first group of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on the side of the second output circuit away from the first group of clock signal lines.

[0251] The method for preparing the display substrate of this embodiment can be referred to the description of the aforementioned embodiment, and thus will not be described in detail here.

[0252] FIG12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG12 , this embodiment provides a display device 91, comprising: a display substrate 910. The display substrate 910 is the display substrate provided in the aforementioned embodiment. The display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be: an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. However, this embodiment is not limited thereto.

[0253] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A display area and a non-display area, wherein the non-display area is provided with a gate driving circuit, the gate driving circuit comprising: a plurality of cascaded shift register units; the shift register units are connected to at least one power line; The shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines; In a first direction, the first group of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second group of clock signal lines is located on a side of the second output circuit away from the first group of clock signal lines.

2. The display substrate according to claim 1, wherein The at least one power line includes: a first power line and a second power line, the first power line is connected to the first output circuit, and the second power line is connected to the second output circuit; In the first direction, the first power line is located between the first output circuit and a first group of clock signal lines, and the second power line is located between the first group of clock signal lines and a second output circuit.

3. The display substrate according to claim 2, wherein: The non-display area is further provided with a third power line and a fourth power line; The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit; In the first direction, the fourth power line is located at a side of the first output circuit away from the first power line, and the third power line is located between the second power line and the second group of clock signal lines.

4. The display substrate according to claim 3, wherein: The non-display area is further provided with an initial signal line. In the first direction, the initial signal line is located on a side of the fourth power line away from the first output circuit.

5. The display substrate according to any one of claims 1 to 4, wherein The first output circuit includes: a first node control subcircuit, a second node control subcircuit and a first output subcircuit; The first node control subcircuit is connected to the input terminal, the first output terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power terminal, the second power terminal, the first node, and the second node, and is configured to control the potential of the first node and the second node under the control of the first clock terminal, the third clock terminal, and the input terminal; The second node control subcircuit is connected to the first node, the second node, the second power supply terminal and the first output terminal, and is configured to maintain the potential of the first node and the second node; The first output sub-circuit is connected to the first node, the second node, the second clock terminal, the second power terminal and the first output terminal, and is configured to control the first output terminal to output the first output signal under the control of the first node and the second node; The second node control sub-circuit, the first output sub-circuit and the first node control sub-circuit are arranged in sequence along a first direction. The display substrate according to claim 5 , wherein: The first node control subcircuit includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor and an eighth control transistor; The control electrode of the first control transistor is connected to the first clock terminal, the first electrode is connected to the input terminal, and the second electrode is connected to the fourth node; The control electrode of the second control transistor is connected to the first clock terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the first node; The control electrode of the third control transistor is connected to the third clock terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second node; The control electrode of the fourth control transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the third node; The control electrode of the fifth control transistor is connected to the second node, the first electrode is connected to the third node, and the second electrode is connected to the first node; The control electrode of the sixth control transistor is connected to the first node, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the third node; The control electrode of the seventh control transistor is connected to the input terminal, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the second node; The control electrode of the eighth control transistor is connected to the first output terminal, the first electrode is connected to the second clock terminal, and the second electrode is connected to the fourth node; The second node control subcircuit includes: a first capacitor and a second capacitor; a first electrode of the first capacitor is connected to the first node, and a second electrode is connected to the first output terminal; a first electrode of the second capacitor is connected to the second node, and a second electrode is connected to the second power supply terminal; The first output sub-circuit includes: a first output transistor and a second output transistor; the control electrode of the first output transistor is connected to the first node, the first electrode is connected to the second clock terminal, and the second electrode is connected to the first output terminal; the control electrode of the second output transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first output terminal.

7. The display substrate according to claim 6, wherein: The first capacitor and the first output transistor are adjacent to each other in the first direction, and the second capacitor and the second output transistor are adjacent to each other in the first direction; the first capacitor and the second capacitor are adjacent to each other in the second direction, and the first output transistor and the second output transistor are adjacent to each other in the second direction; The second direction intersects the first direction.

8. The display substrate according to claim 6, wherein: The active layers of the first control transistor, the second control transistor and the eighth control transistor are an integrated structure, the active layers of the fourth control transistor and the fifth control transistor are an integrated structure; the active layers of the first output transistor and the second output transistor are an integrated structure.

9. The display substrate according to claim 8, wherein: In the first direction, the active layer of the sixth control transistor is located between the active layer of the fifth control transistor and the active layer of the second control transistor, and the active layer of the seventh control transistor is located between the active layer of the fourth control transistor and the active layer of the third control transistor.

10. The display substrate according to any one of claims 1 to 9, wherein: The second output circuit includes: a denoising control subcircuit, a second output subcircuit and a third output subcircuit; The denoising control subcircuit is connected to the first output terminal, the first clock terminal, the third clock terminal, the first power terminal, the second power terminal, and the first denoising control node, and is configured to, under the control of the third clock signal terminal, rectify the charge of the first power terminal to the first denoising control node, so that the first denoising control node is maintained at a voltage that turns on the second output subcircuit; and, under the control of the first output terminal, transmit the signal of the second power terminal to the first denoising control node, so that the first denoising control node is maintained at a voltage that turns off the second output subcircuit; The second output sub-circuit is connected to the first denoising control node, the second output terminal and the first power terminal, and is configured to transmit the signal of the first power terminal to the second output terminal under the control of the first denoising control node; The third output sub-circuit is connected to the first node, the fourth clock terminal and the second output terminal, and is configured to transmit the signal of the fourth clock terminal to the second output terminal under the control of the first node; In the second direction, the second output sub-circuit and the third output sub-circuit are adjacent; In the first direction, the denoising control subcircuit is located between the first group of clock signal lines and the second output subcircuit, and the second direction intersects the first direction.

11. The display substrate according to claim 10, wherein: The de-noising control sub-circuit includes: a first de-noising control transistor, a second de-noising control transistor, a third de-noising control transistor, a fourth de-noising control transistor, a third capacitor, and a fourth capacitor; The control electrode of the first de-noising control transistor is connected to the first output terminal, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the second de-noising control node; The control electrode of the second de-noising control transistor is connected to the third clock terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second de-noising control node; The control electrode and the first electrode of the third de-noising control transistor are connected to the second de-noising control node, and the second electrode is connected to the first de-noising control node; The control electrode of the fourth de-noising control transistor is connected to the first output terminal, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first de-noising control node; The first electrode of the third capacitor is connected to the second noise reduction control node, and the second electrode is connected to the first clock terminal; The first electrode of the fourth capacitor is connected to the first noise reduction control node, and the second electrode is connected to the first power supply terminal; The second output sub-circuit includes: a third output transistor; The control electrode of the third output transistor is connected to the first de-noising control node, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second output terminal; The third output sub-circuit includes: a fourth output transistor; The control electrode of the fourth output transistor is connected to the first node, the first electrode is connected to the fourth clock terminal, and the second electrode is connected to the second output terminal.

12. The display substrate according to claim 11, wherein: The third output transistor and the fourth output transistor are adjacent to each other in the second direction, and the first noise removal control transistor and the second noise removal control transistor are adjacent to each other in the second direction; In the first direction, the third capacitor is located between the second noise removal control transistor and the third noise removal control transistor, and the fourth noise removal control transistor is located between the first noise removal control transistor and the fourth capacitor.

13. The display substrate according to claim 11 or 12, wherein: The active layers of the first and second noise removal control transistors are an integrated structure, and the active layers of the third and fourth output transistors are an integrated structure.

14. The display substrate according to any one of claims 1 to 13, wherein: The first group of clock signal lines includes: a first clock signal line, a second clock signal line, and a third clock signal line; The second group of clock signal lines includes: a fourth clock signal line and a fifth clock signal line; The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the third clock signal provided by the third clock signal line have the same duty cycle, the fourth clock signal provided by the fourth clock signal line and the fifth clock signal provided by the fifth clock signal line have the same duty cycle, and the duty cycle of the fourth clock signal is smaller than the duty cycle of the first clock signal; The second clock signal is delayed by a set time length compared to the first clock signal, and the third clock signal is delayed by a set time length compared to the second clock signal, so that the first clock signal, the second clock signal and the third clock signal are not the first voltage at the same time; the fourth clock signal and the fifth clock signal are not the second voltage at the same time; and the first voltage is different from the second voltage.

15. The display substrate according to claim 14, wherein: In the first direction, the first clock signal line, the second clock signal line and the third clock signal line are sequentially arranged in a direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are sequentially arranged in a direction away from the second output circuit.

16. The display substrate according to claim 14 or 15, wherein: The first output circuit of any stage shift register unit is connected to the first clock signal line, the second clock signal line and the third clock signal line, and the second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

17. The display substrate according to claim 16, wherein: The first clock terminal of the 6n+1th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fourth clock signal line; The first clock terminal of the 6n+2-stage shift register unit is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fifth clock signal line; The first clock terminal of the 6n+3-stage shift register unit is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fourth clock signal line; The first clock terminal of the 6n+4th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fifth clock signal line; The first clock terminal of the 6n+5th stage shift register unit is connected to the second clock signal line, the second clock terminal is connected to the third clock signal line, the third clock terminal is connected to the first clock signal line, and the fourth clock terminal is connected to the fourth clock signal line; The first clock terminal of the 6n+6th stage shift register unit is connected to the third clock signal line, the second clock terminal is connected to the first clock signal line, the third clock terminal is connected to the second clock signal line, and the fourth clock terminal is connected to the fifth clock signal line; Wherein, n is a natural number.

18. The display substrate according to any one of claims 1 to 13, wherein: The first output terminal of the 2k-1th stage shift register unit is connected to the input terminal of the 2k+1th stage shift register unit, and the input terminal of the first stage shift register unit is connected to the first initial signal line; The first output terminal of the 2k-th stage shift register unit is connected to the input terminal of the 2k+2-th stage shift register unit, and the input terminal of the second stage shift register unit is connected to the second initial signal line, where k is a positive integer; The first group of clock signal lines includes: a first grouped clock signal line and a second grouped clock signal line, and the second group of clock signal lines includes: a third grouped clock signal line and a fourth grouped clock signal line; The 2k-1th stage shift register unit is connected to the first block clock signal line and the third block clock signal line, and the 2kth stage shift register unit is connected to the second block clock signal line and the fourth block clock signal line.

19. The display substrate according to claim 18, wherein: In the first direction, the first grouped clock signal lines and the second grouped clock signal lines are arranged at intervals, and the third grouped clock signal lines and the fourth grouped clock signal lines are arranged at intervals.

20. The display substrate according to claim 18 or 19, wherein: The first grouped clock signal lines include: a first clock signal line, a second clock signal line and a third clock signal line; The second group of clock signal lines includes: a sixth clock signal line, a seventh clock signal line and an eighth clock signal line; The third grouped clock signal line includes: a fourth clock signal line and a fifth clock signal line; The fourth group of clock signal lines includes: a ninth clock signal line and a tenth clock signal line; The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, the third clock signal provided by the third clock signal line, the sixth clock signal provided by the sixth clock signal line, the seventh clock signal provided by the seventh clock signal line, and the eighth clock signal provided by the eighth clock signal line have the same duty cycle; the second clock signal is delayed by a first set time period compared to the first clock signal, and the third clock signal is delayed by a first set time period compared to the second clock signal, so that the first clock signal, the second clock signal, and the third clock signal are not simultaneously at the first voltage; the seventh clock signal is delayed by a first set time period compared to the sixth clock signal, and the eighth clock signal is delayed by a first set time period compared to the seventh clock signal, so that the sixth clock signal, the seventh clock signal, and the eighth clock signal are not simultaneously at the first voltage; the sixth clock signal is delayed by a second set time period compared to the first clock signal, the seventh clock signal is delayed by a second set time period compared to the second clock signal, and the eighth clock signal is delayed by a second set time period compared to the third clock signal; The fourth clock signal provided by the fourth clock signal line, the fifth clock signal provided by the fifth clock signal line, the ninth clock signal provided by the ninth clock signal line, and the tenth clock signal provided by the tenth clock signal line have the same duty cycle; the duty cycle of the fourth clock signal is smaller than the duty cycle of the first clock signal; the fourth clock signal and the fifth clock signal are not the second voltage at the same time, the ninth clock signal and the tenth clock signal are not the second voltage at the same time, and the second voltage is different from the first voltage; the ninth clock signal is delayed by a second set time length compared to the fourth clock signal, and the tenth clock signal is delayed by a second set time length compared to the fifth clock signal.

21. The display substrate according to any one of claims 1 to 20, wherein: In a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes: a base substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged on the base substrate; The first semiconductor layer at least includes: active layers of a plurality of transistors of the shift register unit; The first conductive layer at least includes: control electrodes of multiple transistors of the shift register unit, and first electrodes of multiple capacitors; The second conductive layer at least includes: second electrodes of a plurality of capacitors of the shift register unit; The third conductive layer at least includes: first electrodes and second electrodes of a plurality of transistors of the shift register unit, a first group of clock signal lines, a second group of clock signal lines, and a plurality of power supply lines; The fourth conductive layer at least includes: a connection electrode connecting the first node and the third output sub-circuit of the second output circuit.

22. A display substrate comprising the display substrate according to any one of claims 1 to 21.

23. A method for preparing a display substrate, for preparing the display substrate according to any one of claims 1 to 21, the method comprising: providing a substrate; forming a gate driving circuit in the non-display area; In which, the gate drive circuit includes: a plurality of cascaded shift register units; the shift register unit is connected to at least one power line; the shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines; in a first direction, the first group of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on the side of the second output circuit away from the first group of clock signal lines.

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