ARRAYS AND ARRAYS CONTROL METHODS, AND DISPLAY DEVICES

Abstract

The invention relates to an array substrate; and a method for controlling an array substrate and a display device. The array substrate consists of: a base substrate; and multiple pixels on the base substrate, where multiple pixels are arranged in an array in the first and second directions. At least one of the multiple pixels consists of: subpixels, and a pixel controller for controlling each subpixel within the pixel. The array substrate also consists of: multiple addressing signal lines on the base substrate, where the addressing signal lines are coupled to the addressing signal terminals of the pixel controllers of a row of pixels arranged in the first direction and multiple data lines on the base substrate, where the data lines are coupled to the data signal terminals of the pixel controllers of a column of pixels arranged in the second direction.

Description

Array substrate, driving method thereof and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, and a display device. Background Art

[0002] With the continuous development of light emitting diode (LED) technology, micro-LEDs are manufactured by miniaturizing LEDs to less than 300 microns. Thousands, tens of thousands, or even more micro-LEDs are fixed on a substrate, enabling more detailed local dimming and presenting a display with high contrast and color expression.

[0003] In related technologies, micro-LED displays use a passive matrix (PM) drive method. This requires a large number of signal traces to be fabricated on the glass substrate, making signal trace binding difficult. This is especially true for tiled display products, where a side-wiring process is required, further increasing the complexity. Furthermore, due to the insufficient thickness of the metal layer used to fabricate the signal traces and the limited number of layers, a multiplexer (MUX) is required to reduce the number of signal traces. However, a high proportion of multiplexers results in excessive power consumption in the micro-LED display.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, which includes:

[0006] substrate;

[0007] A plurality of pixels are located on the substrate; the plurality of pixels are arranged in an array in a first direction and a second direction, the first direction and the second direction intersecting each other; at least one of the plurality of pixels includes: a sub-pixel and a pixel driver chip for driving each of the sub-pixels in the pixel; the sub-pixel includes at least one light-emitting diode; the pixel driver chip includes: a data signal terminal and an addressing signal terminal;

[0008] A plurality of address selection signal lines are located on the base substrate; the address selection signal lines are coupled to the addressing signal terminals of the pixel driving chips of a row of pixels arranged in the first direction;

[0009] A plurality of data lines are located on the base substrate; the data lines are coupled to the data signal terminals of the pixel driving chips of a row of pixels arranged in the second direction.

[0010] Optionally, in the embodiment of the present disclosure, each of the address selection signal lines extends along the first direction and is arranged along the second direction;

[0011] The address selection signal line is located in a gap between two adjacent rows of pixels arranged along the first direction.

[0012] Optionally, in the embodiment of the present disclosure, it further includes: a plurality of site selection signal transfer lines;

[0013] A plurality of the site selection signal adapter lines extend along the second direction and are arranged along the first direction;

[0014] The plurality of site selection signal adapter wires correspond one to one with the plurality of site selection signal lines;

[0015] The site selection signal adapter wire and the site selection signal line are arranged in different layers, and the site selection signal adapter wire is coupled to the corresponding site selection signal line through a first via hole; the first via hole penetrates the insulating layer between the site selection signal adapter wire and the site selection signal line.

[0016] Optionally, in the embodiment of the present disclosure, each of the data lines extends along the second direction and is arranged along the first direction;

[0017] The data line is located in a gap between two adjacent rows of pixels arranged along the first direction.

[0018] Optionally, in the embodiment of the present disclosure, it further includes: a plurality of power signal lines, and a plurality of fixed voltage signal lines;

[0019] The pixel driving chip further includes: a signal channel terminal and a fixed voltage signal terminal;

[0020] The power signal line is coupled to the first electrodes of the light-emitting diodes of a row of pixels arranged in the second direction; the second electrodes of the light-emitting diodes in the pixels are respectively coupled to the signal channel terminals of the pixel driving chip;

[0021] The fixed voltage signal line is coupled to the fixed voltage signal terminals of the pixel driving chips of a row of pixels arranged in the second direction.

[0022] Optionally, in an embodiment of the present disclosure, the pixel includes at least: a red sub-pixel, a green sub-pixel, and a blue sub-pixel;

[0023] The plurality of power signal lines are divided into a plurality of first power signal lines and a plurality of second power signal lines;

[0024] The first power signal line is coupled to the first electrode of each of the red sub-pixels of a row of the pixels arranged in the second direction;

[0025] The second power signal line is coupled to first electrodes of the green sub-pixels and the blue sub-pixels of a row of pixels arranged in the second direction.

[0026] Optionally, in an embodiment of the present disclosure, a plurality of auxiliary signal lines;

[0027] Each of the auxiliary signal lines extends along the first direction and is arranged along the second direction;

[0028] The auxiliary signal line is located in the gap between two adjacent rows of pixels arranged in the first direction;

[0029] The auxiliary signal lines and the fixed voltage signal lines are arranged in different layers, and each of the auxiliary signal lines is coupled to at least one fixed voltage signal line through a second via hole; the second via hole penetrates the insulating layer between the auxiliary signal line and the fixed voltage signal line.

[0030] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising: any one of the above-mentioned array substrates.

[0031] Accordingly, an embodiment of the present disclosure further provides a driving method for any of the above array substrates, comprising:

[0032] Each display frame at least includes: an address allocation phase and a data signal transmission phase; wherein,

[0033] In the address allocation stage, address selection information is input to each address selection signal line in sequence; the address selection information includes address information corresponding to a row of pixels arranged in a first direction;

[0034] During the data signal transmission stage, data information is input to each data line respectively; the data information includes multiple sub-data information; the sub-data information includes: address information corresponding to a row of pixels arranged in a first direction, and pixel data information of the pixels corresponding to the address information and coupled to the data line.

[0035] Optionally, in an embodiment of the present disclosure, the address selection information includes: a start instruction, the address information, an interval instruction and an end instruction set in sequence.

[0036] Optionally, in an embodiment of the present disclosure, the sub-data information includes: a start instruction, the address information, a data transmission instruction, an interval instruction, the image information and an end instruction arranged in sequence.

[0037] Optionally, in the embodiment of the present disclosure, each display frame further includes: a current setting phase before the data signal transmission phase;

[0038] In the current setting phase, current setting information is input to each of the data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present disclosure;

[0040] FIG2 is a schematic diagram of the connection relationship of a pixel in an embodiment of the present disclosure;

[0041] FIG3 is a schematic diagram of another connection relationship of a pixel in an embodiment of the present disclosure;

[0042] FIG4 is a timing diagram corresponding to the driving method provided by an embodiment of the present disclosure;

[0043] FIG5 is a schematic diagram of the timing of site selection information in an embodiment of the present disclosure;

[0044] FIG6 is a schematic diagram of encoding of a data signal. DETAILED DESCRIPTION

[0045] Embodiments of the present disclosure provide an array substrate, a driving method thereof, and a display device.

[0046] The following describes in detail the array substrate, its driving method, and the display device provided by the embodiments of the present disclosure in conjunction with the accompanying drawings. The sizes and shapes of the structures in the drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure.

[0047] FIG1 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present disclosure. As shown in FIG1 , the array substrate provided in an embodiment of the present disclosure may include:

[0048] Base substrate 10;

[0049] A plurality of pixels 11 are located on a substrate 10; the plurality of pixels 11 are arranged in an array in a first direction F1 and a second direction F2, with the first direction F1 and the second direction F2 intersecting each other. FIG2 is a schematic diagram of the connection relationship of a pixel 11 in an embodiment of the present disclosure. Combining FIG1 and FIG2 , at least one pixel 11 among the plurality of pixels 11 includes: a sub-pixel 111, and a pixel driver chip 112 for driving each sub-pixel 111 within the pixel 11; each sub-pixel 111 includes at least one light-emitting diode; the pixel driver chip 112 includes: a data signal terminal Da and an addressing signal terminal Uc;

[0050] M address selection signal lines S are located on the base substrate 10; each address selection signal line S i (0<i≤M, i is a positive integer) coupled to the addressing signal terminal Uc of each pixel driving chip 112 of a row of pixels 11 arranged in the first direction F1;

[0051] N data lines D are located on the base substrate 10; each data line D j (0<j≤N, j is a positive integer) is coupled to the data signal terminal Da of each pixel driving chip 112 of a row of pixels arranged in the second direction F2.

[0052] It should be noted that the first direction may be a row direction, and the second direction may be a column direction; or the first direction may be a column direction, and the second direction may be a row direction, without limitation. For ease of description, in the embodiments of the present disclosure, the first direction is a row direction, and the second direction is a column direction.

[0053] In the array substrate provided by the embodiments of the present disclosure, at least one pixel includes: a sub-pixel and a pixel driver chip. By using the pixel driver chip to directly drive each sub-pixel within the pixel to emit light, fine pixel-level driving can be achieved. By providing multiple addressing signal lines and multiple data signal lines, during the driving process, addressing information is sequentially input to each addressing signal line, and multiple sub-data information is respectively input to each data line, so that each pixel driver chip then provides the sub-data information to the corresponding sub-pixel, thereby achieving an active addressing driving mode, significantly reducing the number of signal traces on the substrate, and allowing sufficient space for signal trace wiring in the array substrate. The resistance of the signal trace can be reduced by increasing the width of the signal trace, etc., and the brightness of the light-emitting diode can be increased without increasing the thickness of the signal trace, thereby reducing the power of the array substrate. At the same time, the number of signal traces can be greatly reduced, thereby reducing the width of the binding area and the difficulty of binding the binding area and the signal trace.

[0054] In the embodiments of the present disclosure, the above-mentioned light-emitting diodes can be sub-millimeter light-emitting diodes (micro light-emitting diodes) or micro light-emitting diodes (Micro LEDs), which are not limited here. In Figures 1 and 2, each sub-pixel includes one light-emitting diode as an example for illustration. In specific implementation, the sub-pixel can also include more light-emitting diodes. For example, the sub-pixel in Figure 3 can include two light-emitting diodes. The number of light-emitting diodes in the sub-pixel is not limited here. For ease of control, when a sub-pixel includes at least two light-emitting diodes, the colors of the light-emitting diodes in the sub-pixel are the same. Of course, in some cases, the colors of the light-emitting diodes in the sub-pixel may not be exactly the same, which is not limited here. Figure 3 illustrates the light-emitting diodes in the sub-pixel connected in parallel. The light-emitting diodes in the sub-pixel can also be connected in series, which is not limited here.

[0055] Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG1 , each address selection signal line S i Extending along the first direction F1 and arranged along the second direction F2; each site selection signal line Si Located in the gap between two adjacent rows of pixels 11 arranged along the first direction F1. In this way, the address selection signal line S i It is easier to connect with a corresponding row of pixels 11, facilitates wiring, and prevents crossing between signal lines.

[0056] In a specific implementation, the array substrate provided in the embodiment of the present disclosure, with continued reference to FIG1 , may further include: M address selection signal transfer lines Q;

[0057] M site selection signal patch cables Q extend along the second direction F2 and are arranged along the first direction F1;

[0058] Signal transfer line Q for each site i (0<i≤M, i is a positive integer) and the site selection signal line S i One-to-one correspondence, for example, the site selection signal adapter line Q1 corresponds to the site selection signal line S1;

[0059] The site selection signal transfer line Q and the site selection signal line S are set on different layers, and the site selection signal transfer line Q i Through the first via hole (as shown in the figure, the signal transfer line Q i With the site selection signal line S i The black circle at the intersection) and the corresponding location signal line S i Coupling; the first via hole passes through the site selection signal transfer line Q i With the site selection signal line S i Insulation layer between.

[0060] If the address selection signal adapter line Qi is not provided, it is necessary to provide signal sources at both ends of the extending direction of the address selection signal line Si, which increases the area of ​​the border region of the array substrate. In the embodiment of the present disclosure, by providing the address selection signal adapter line Qi extending along the second direction F2, the address selection signal adapter line Q can be used to connect the address selection signal line Si to the array substrate. i To the corresponding location signal line S i Provides address selection signals, so that the signal sources of the address selection signal lines Si and the data lines Dj can be set on the same side of the array substrate. For example, the signal source can be set on the address selection signal adapter line Q i At least one of the two ends can reduce the area of ​​the border region of the array substrate. i Provide an address selection signal, for example, the signal source may be a driver chip.

[0061] Optionally, in order to avoid the location signal switching line Q i Affect the light emitting diode, you can switch the address signal to Q i Set in the gap between two adjacent pixel columns, in practical applications, each address signal can be transferred to the Qi It is set to be evenly distributed in each gap. For example, when the number of rows and columns in the array substrate is equal, a selection signal transfer line Q can be set on the same side of each pixel column. i When the number of rows in the array substrate is greater than the number of columns, an address selection signal transfer line Q can be set in the gap between every two adjacent pixel columns. i , and two location selection signal transfer lines Q are set in at least part of the gap i .

[0062] Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG1 , each data line D j Extending along the second direction F2 and arranged along the first direction F1;

[0063] Data cable D j Located in the gap between two adjacent rows of pixels 11 arranged along the first direction F1. In this way, the data line D j It is easier to connect with a corresponding row of pixels 11, facilitates wiring, and prevents crossing between signal lines.

[0064] In addition, the array substrate provided in the embodiment of the present disclosure, in conjunction with FIG. 1 and FIG. 2 , may further include: N power signal lines Va and Vb, and N fixed voltage signal lines G;

[0065] The pixel driving chip 112 may further include: a signal channel terminal CH (eg, CH1, CH2, CH3) and a fixed voltage signal terminal Gd;

[0066] Power signal line Va j 、Vb j It is coupled to the first electrodes of the light-emitting diodes of a row of pixels 11 arranged in the second direction F2; the second electrodes of each light-emitting diode in the pixel 11 are respectively coupled to the signal channel ends CH of the pixel driving chip 112; wherein the first electrode can be the positive electrode of the light-emitting diode, and the second electrode can be the negative electrode of the light-emitting diode.

[0067] Fixed voltage signal line G j (0<j≤N, j is a positive integer) is coupled to the fixed voltage signal terminal Gd of the pixel driving chip 112 of a row of pixels 11 arranged in the second direction F2.

[0068] Power signal line Va j (or Vb j )(0<j≤N, j is a positive integer) is coupled to the first electrode of the light emitting diode, so the power signal line Va j (or Vb j) can provide power to the light emitting diode, and the second electrode of the light emitting diode is coupled to the signal channel terminal CH of the pixel driving chip 112, and the fixed voltage signal line G j The fixed voltage signal line G is coupled to the fixed voltage signal terminal Gd of the pixel driving chip 112. j A fixed voltage signal can be provided to the pixel driver chip 112 to form a power supply circuit. The light emitting diode is a current driven element. The pixel driver chip 112 provides a signal path to the coupled light emitting diode through the signal channel terminal CH, so that the light emitting diode can achieve different light output brightness under the control of current signals with different current amplitudes and / or different duty cycles. Optionally, each power signal line Va j (or Vb j ) and each fixed voltage signal line G j It can be set in the gap between two adjacent pixel columns.

[0069] In a specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, in conjunction with Figures 1 and 2, the pixel 11 includes at least: a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R may include at least one red micro-light emitting diode, the green sub-pixel G may include at least one green micro-light emitting diode, and the blue sub-pixel B may include at least one blue micro-light emitting diode;

[0070] The plurality of power signal lines are divided into a plurality of first power signal lines Va j and a plurality of second power signal lines Vb j ;

[0071] First power signal line Va j coupled to the first electrode of each red sub-pixel R of a row of pixels 11 arranged in the second direction F2;

[0072] Second power signal line Vb j The first electrode is coupled to each green sub-pixel G and each blue sub-pixel B in a row of pixels 11 arranged in the second direction F2.

[0073] Due to the different characteristics of light-emitting diodes of different colors, the voltage required for the red sub-pixel is quite different from the voltage required for the green sub-pixel, and the voltage required for the green sub-pixel is similar to the voltage required for the blue sub-pixel. Therefore, the second power signal line Vbj is coupled to each green sub-pixel G and each blue sub-pixel B in a column of pixels 11, and the green sub-pixel G and the blue sub-pixel B share the power signal line, which can greatly reduce the number of power signal lines and simplify the wiring of the array substrate.

[0074] Optionally, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG1 , there are M auxiliary signal lines W;

[0075] Each auxiliary signal line W i (0<i≤M, i is a positive integer) extending along the first direction F1 and arranged along the second direction F2;

[0076] Auxiliary signal line W i Located in the gap between two adjacent rows of pixels 11 arranged in the first direction F1 to avoid affecting the light emission of each sub-pixel;

[0077] Auxiliary signal line W i With fixed voltage signal line G j Different layers are set, and each auxiliary signal line W i Through the second via hole (as shown in the auxiliary signal line W i With fixed voltage signal line G j The black circle at the intersection) and at least one fixed voltage signal line G j The second via hole passes through the auxiliary signal line W i With fixed voltage signal line G j Insulation layer between.

[0078] By setting the fixed voltage signal line G j Auxiliary signal line W on different layers i , and the auxiliary signal line W i Through the second via hole and the fixed voltage signal line G j The plurality of fixed voltage signal lines G and the plurality of auxiliary signal lines W are coupled so as to form a grid-like parallel structure, thereby reducing the resistance of the fixed voltage signal line G and reducing the fixed voltage signal line G. j voltage drop, reducing the fixed voltage signal line G j Optionally, a second via hole can be provided in each region where the orthographic projection of the fixed voltage signal line G and the auxiliary signal line W on the substrate overlaps, so as to increase the signal delay of the fixed voltage signal line G. j With auxiliary signal line W i The parallel area of ​​the fixed voltage signal line G is further reduced j Signal delay on .

[0079] In the embodiment of the present disclosure, in order to save the process flow and save the production cost, each location signal line S i , and each auxiliary signal line W i Set in the same film layer, each data line D j , each site selection signal transfer line Q i , each power signal line Va j and Vb j , and each fixed voltage signal line G jIn other words, the signal lines extending along the first direction F1 are arranged in the same film layer, and the signal lines extending along the second direction F2 are arranged in the same film layer. This can also prevent the signal lines extending along the first direction F1 and the signal lines extending along the second direction F2 from crossing each other when they are located in the same film layer, thereby reducing wiring difficulty.

[0080] In a specific implementation, referring to FIG1 , a signal source can be provided at the edge of the side of the array substrate extending along the first direction F1. The signal source can be coupled to N data lines D, M addressing signal adapters Q, N power signal lines Va and N power signal lines Vb, and N fixed voltage signal lines G to pass corresponding drive signals to each signal line extending along the second direction F2. Optionally, the signal source can be a field programmable gate array (FPGA), an integrated circuit (IC), a printed circuit board (PCB), a flexible printed circuit (FPC), or a chip on flex (COF), etc., which are not limited here. In the embodiment of the present disclosure, by providing a signal source to provide corresponding signals to each signal line, the wiring space of the array substrate can be greatly increased, which is conducive to the narrow frame of the array substrate.

[0081] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising the aforementioned array substrate. This display device can be applied to any product or component with a display function, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, and navigation systems. Because the principles underlying the display device are similar to those of the aforementioned array substrate, the implementation of this display device can be referenced to the implementation of the aforementioned array substrate, and any overlapping details will not be repeated here.

[0082] Based on the same inventive concept, an embodiment of the present disclosure also provides a driving method for any of the above-mentioned array substrates. Since the principle of solving the problem by the driving method is similar to that of the above-mentioned array substrate, the implementation of the driving method can refer to the implementation of the above-mentioned array substrate, and the repeated parts will not be repeated.

[0083] FIG4 is a timing diagram corresponding to the driving method provided in an embodiment of the present disclosure. In conjunction with FIG1 and FIG4 , the driving method of any of the above array substrates provided in an embodiment of the present disclosure may include:

[0084] Each display frame T may include at least: an address allocation phase t1 and a data signal transmission phase t3; wherein,

[0085] In the address allocation phase t1, each address selection signal line S is sent to each address selection signal line S in turn. i Enter site information i FIG5 is a schematic diagram of the timing of the location information in the embodiment of the present disclosure. As shown in FIG5 , the location information s i This may include assigning corresponding address information IDs to a row of pixels 11 arranged in the first direction F1. For example, the address selection signal line S1 assigns address information s1 including address information ID 00000001 to the first row of pixels 11 in the current row arranged along the first direction F1, and the address selection signal line S2 assigns address information s2 including address information ID 00000010 to the second row of pixels 11 in the current row arranged along the first direction F1, and so on, completing the address assignment process to the pixel driver chips in each pixel row.

[0086] In the data signal transmission phase t3, the data lines D j Specifically, a plurality of sub-data information da are sequentially input to each data line Dj. i , that is, each data information da includes multiple sub-data information da arranged in a specific order (for example, the specific order can be the arrangement order of each column of pixels) i , so that the data line Dj transmits the corresponding sub-data information da to each pixel driving chip in the corresponding pixel column in turn i The sub-data information includes: the address information ID corresponding to each pixel 11, and the address information ID corresponding to the data line D j The pixel data information of the coupled pixel 11, the pixel driving chip receives the sub-data information da i After that, according to the sub-data information da i The address information ID in the data signal is transmitted to the corresponding pixel. For example, in the data signal transmission phase t3, the pixel data information is transmitted to the data line D j Enter the sub-data information da in sequence i , and data line D j After receiving sub-data information da1, the coupled pixel driver chip decodes the address information ID as 00000001 and transmits the pixel data information contained in sub-data information da1 to pixel 11 located in the first row of the jth column. Data information da1 includes pixel data corresponding to multiple pixels 11 arranged in the first direction F1, thereby controlling different pixels 11 to achieve different light output brightness.

[0087] In the driving method provided by the embodiment of the present disclosure, in the address allocation stage, the addressing information is input into each addressing signal line in turn, and the addressing information includes the address information ID of the corresponding pixel row. In the data signal transmission stage, the data information is input into each data line respectively; the sub-data information in the data information includes the address information ID and pixel data information of the corresponding pixel row. Therefore, after the pixel driving chip receives the pixel data information, it can transmit the pixel data information of the pixel row to the corresponding sub-pixels respectively, thereby realizing the active addressing driving method.

[0088] Optionally, in the driving method provided by the embodiment of the present disclosure, as shown in FIG5 , the location information s i It may include: the start instruction SoT, address information ID, interval instruction DCX and end instruction EoT set in sequence. i Corresponding location information s i The address information ID in the address information is different, so as to distinguish the address information of pixels in different rows. i The length of can be set to 12 bits, wherein the start instruction SoT can be set to 1 bit, the address information ID can be set to 8 bits, the interval instruction DCX can be set to 1 bit, and the end instruction EoT can be set to 2 bits.

[0089] As shown in FIG5 , in a specific implementation, the address selection signal line S i The signal amplitude of the transmission is used to distinguish the addressing function from other functions. For example, when the signal amplitude level is V2 (for example, the voltage value is 3.3V), the addressing function is executed, and when the signal amplitude level is V1 (for example, the voltage value is 1.8V), the display function is executed. In actual operation, the addressing signal line S is first selected. i The amplitude of the transmitted signal needs to be increased from level V0 (for example, 0V) to level V1 so as to be consistent with the addressing signal line S i The connected components enter the working state, and then the signal amplitude changes from level V1 to level V2 as the reference fluctuation, then the address signal line S i Perform the site selection function by modulating the site selection signal line S i The fluctuation variation law of the transmission signal. For example, the signal is at the first amplitude V 2H and the second amplitude V 2L Changes between V1 <V 2L <V2<V 2H By modulating the changing rules of the first amplitude V1 and the second amplitude V2, the location information s i Modulate the signal so that the corresponding address information is transmitted while transmitting power. iIt starts with the start instruction SoT, then transmits the address information ID and the interval instruction DCX, and finally ends the address allocation of the pixel row with the end instruction EoT. When the signal amplitude fluctuates from the level V2 as the reference and then returns to the level V1 and keeps the level V1, the address selection signal line S i It can be used to realize other functions, such as multiplexing s as a sensing signal line, etc., which is not limited here. Of course, the addressing signal line S i In this case, it is also possible not to have any function.

[0090] Optionally, in the driving method provided by the embodiment of the present disclosure, as shown in FIG4 , the sub-data information may include: a start instruction SoT, address information ID, a data transmission instruction DCX, an interval instruction IoT, pixel data information Rda, Gda, Bda, and an end instruction EoT. Among them, when the data transmission instruction DCX is a set value, it indicates that data transmission is performed. For example, when DCX=1, it indicates data transmission. When the pixel driver chip recognizes that the value of DCX is 1, the pixel data information in the sub-data information is transmitted to the corresponding light-emitting diode. The pixel data information Rda represents the image data information required to drive the red sub-pixel to emit light, the pixel data information Gda represents the image data information required to drive the green sub-pixel to emit light, and the pixel data information Bda represents the image data information required to drive the blue sub-pixel to emit light. In specific implementation, the length of the sub-data information can be set to 63 bits, among which the start instruction SoT occupies 1 bit, the address information ID occupies 8 bits, the data transmission instruction DCX occupies 1 bit, the interval instruction IoT occupies 1 bit, the image information Rda, Gda or Bda occupies 16 bits respectively, and the end instruction EoT occupies 2 bits. In addition, the interval instruction IoT can also be set between adjacent pixel data information.

[0091] Figure 6 shows a schematic diagram of data signal encoding, using the timing of sub-data information da1 as an example. As shown in Figure 6, the meaning of each bit in data information da can be represented by designing the duty cycle of the pulse sequence. For example, a 25% duty cycle of a pulse in the pulse sequence indicates that the bit represents a 0; a 75% duty cycle of a pulse indicates that the bit represents a 1; a 50% duty cycle of a pulse indicates that the bit is a start of time (SoT); and when two consecutive pulses have a 50% duty cycle, i.e., two consecutive SoTs occur, the two bits represent an end of time (EoT).

[0092] In addition, in the above-mentioned driving method provided by the embodiment of the present disclosure, as shown in Figure 4, each display frame T may also include: a current setting stage t2 before the data signal transmission stage t3, for example, the current setting stage t2 may be located between the address allocation stage t1 and the data signal transmission stage t3.

[0093] 1 and 4, in the current setting phase t2, the current is supplied to each data line D j Input current setting information Co. By inputting current setting information to the data line, the drive current of the pixel driver chip can be controlled, thereby further precisely controlling the display brightness of the corresponding pixel. In a specific implementation, the drive current provided by different pixel driver chips can be set to be different. In a specific implementation, the current setting information Co can also be provided with address information ID, so that the current setting information Co is input to the corresponding pixel row.

[0094] Optionally, the length of the current setting information Co can be 63 bits, specifically including: a 1-bit start instruction SoT, 8 bits of address information ID, a 1-bit current setting instruction DCX, a 1-bit interval instruction IoT, 16 bits of data consisting of a frame start instruction C and a control instruction P1 (for example, indicating that the signal channel end CH needs to provide a current amplitude correction coefficient to the light-emitting diode), a 1-bit interval instruction IoT, 16 bits of reserved control instruction bits P2+P3, a 1-bit interval instruction IoT, 16 bits of reserved control instruction bits P4+P5, and a 2-bit end instruction EoT. Among them, when the current setting instruction DCX is a set value, it indicates that the current is set. For example, when DCX is 0, it indicates that the current is set.

[0095] The following describes in detail the driving process of a display frame T in the embodiment of the present disclosure in conjunction with the timing sequence shown in FIG. 4 .

[0096] In the address allocation phase t1, each address selection signal line Si is controlled to be enabled row by row, and the address information ID is written to the pixel driver chip of each row in turn. That is, the address information ID of the pixel driver chips located in the same row can be the same, so that in the data signal transmission phase t3, when the pixel driver chip receives and analyzes the data signal, it can obtain data information that matches its own address.

[0097] During the current setting phase t2, current setting information Co is simultaneously input to all data lines Dj, and each data line Dj writes correction data to the buffers of the pixel driver chips in the same pixel column. For example, due to differences in manufacturer and batch, the photoelectric characteristics of the light-emitting diodes in different pixels inevitably vary. This results in different brightness levels for different pixels when the display device displays a solid color image. In the disclosed embodiment, during the current setting phase t2, the display brightness of the light-emitting diodes in each pixel can be adjusted by writing correction data to each pixel driver chip.

[0098] In the data signal transmission phase t3, data information da is input to all data lines Dj at the same time, and each data information da is transmitted to the pixel driver chip of the same pixel column in turn. After receiving and parsing the data information da, the pixel driver chip can obtain the sub-data information da that matches its own address. j , according to the sub-data information da j Drive the light emitting diode to emit light.

[0099] The array substrate, driving method, and display device provided in the embodiments of the present disclosure utilize a pixel-level constant current driver chip to directly drive each sub-pixel within the pixel to emit light, thus achieving pixel-level drive display. By providing multiple addressing signal lines and multiple data signal lines, during the drive process, addressing information is sequentially input to each addressing signal line, and multiple sub-data information is input to each data line, thereby controlling each pixel driver chip to provide pixel data information to each sub-pixel. This achieves an active addressing drive mode and significantly reduces the number of signal traces on the substrate.

[0100] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0101] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of pixels are located on the base substrate; The plurality of pixels are arranged in an array in a first direction and a second direction, wherein the first direction and the second direction intersect each other; At least one pixel among the plurality of pixels comprises: a sub-pixel, and a pixel driver chip for driving each of the sub-pixels in the pixel; the sub-pixel comprises at least one light-emitting diode; the pixel driver chip comprises: a data signal terminal and an addressing signal terminal; A plurality of address selection signal lines are located on the base substrate; the address selection signal lines are coupled to the addressing signal terminals of the pixel driving chips of a row of pixels arranged in the first direction; A plurality of data lines are located on the base substrate; the data lines are coupled to the data signal terminals of the pixel driving chips of a row of pixels arranged in the second direction.

2. The array substrate according to claim 1, wherein: Each of the address selection signal lines extends along the first direction and is arranged along the second direction; The address selection signal line is located in a gap between two adjacent rows of pixels arranged along the first direction.

3. The array substrate according to claim 2, wherein: Also includes: Multiple site selection signal transfer lines; A plurality of the site selection signal adapter lines extend along the second direction and are arranged along the first direction; The plurality of site selection signal adapter wires correspond one to one with the plurality of site selection signal lines; The site selection signal adapter wire and the site selection signal line are arranged in different layers, and the site selection signal adapter wire is coupled to the corresponding site selection signal line through a first via hole; the first via hole penetrates the insulating layer between the site selection signal adapter wire and the site selection signal line.

4. The array substrate according to claim 1, wherein: Each of the data lines extends along the second direction and is arranged along the first direction; The data line is located in a gap between two adjacent rows of pixels arranged along the first direction.

5. The array substrate according to any one of claims 1 to 4, wherein: Also includes: Multiple power signal lines and multiple fixed voltage signal lines; The pixel driving chip further includes: a signal channel terminal and a fixed voltage signal terminal; The power signal line is coupled to the first electrodes of the light-emitting diodes of a row of pixels arranged in the second direction; the second electrodes of the light-emitting diodes in the pixels are respectively coupled to the signal channel terminals of the pixel driving chip; The fixed voltage signal line is coupled to the fixed voltage signal terminals of the pixel driving chips of a row of pixels arranged in the second direction.

6. The array substrate according to claim 5, wherein: The pixel includes at least: a red sub-pixel, a green sub-pixel, and a blue sub-pixel; The plurality of power signal lines are divided into a plurality of first power signal lines and a plurality of second power signal lines; The first power signal line is coupled to the first electrode of each of the red sub-pixels of a row of the pixels arranged in the second direction; The second power signal line is coupled to first electrodes of the green sub-pixels and the blue sub-pixels of a row of pixels arranged in the second direction.

7. The array substrate according to claim 5, wherein: Multiple auxiliary signal lines; Each of the auxiliary signal lines extends along the first direction and is arranged along the second direction; The auxiliary signal line is located in the gap between two adjacent rows of pixels arranged in the first direction; The auxiliary signal lines and the fixed voltage signal lines are arranged in different layers, and each of the auxiliary signal lines is coupled to at least one fixed voltage signal line through a second via hole; the second via hole penetrates the insulating layer between the auxiliary signal line and the fixed voltage signal line.

8. A display device, wherein: include: The array substrate according to any one of claims 1 to 7.

9. A driving method for an array substrate according to any one of claims 1 to 7, wherein: include: Each display frame at least includes: an address allocation phase and a data signal transmission phase; wherein, In the address allocation stage, address selection information is input to each address selection signal line in sequence; the address selection information includes address information corresponding to a row of pixels arranged in a first direction; During the data signal transmission phase, data information is input to each data line respectively; the data information includes a plurality of sub-data information; the sub-data information includes: address information corresponding to each pixel, and pixel data information of the pixel corresponding to the address information and coupled to the data line.

10. The driving method according to claim 9, wherein: The address selection information includes: a start instruction, the address information, an interval instruction and an end instruction which are set in sequence.

11. The driving method according to claim 9, wherein: The sub-data information includes: a start instruction, the address information, a data transmission instruction, an interval instruction, the image information and an end instruction which are arranged in sequence.

12. The driving method according to any one of claims 9 to 11, wherein: Each display frame further includes: a current setting phase prior to the data signal transmission phase; In the current setting phase, current setting information is input to each of the data lines.

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