Methods for creating photovoltaic devices and methods for creating the absorbing layer of photovoltaic devices.

Abstract

According to the methods described herein, the invention relates to a method for constructing a photovoltaic device which may include a multilayer semiconductor deposition step. The multilayer semiconductor may include a doped layer doped with a group V dopant. The doped layer may include cadmium selenide or cadmium tellurite. The method may include an annealing step for the multilayer semiconductor to form an absorbent layer. The invention also relates to a photovoltaic device.

Description

THIN FILM STACKS FOR GROUP V DOPING, PHOTOVOLTAIC DEVICES INCLUDING THE SAME, AND METHODS FOR FORMING PHOTOVOLTAICDEVICES WITH THIN FILM STACKS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from U.S. Provisional Patent Application No.62 / 464,127, filed on February 27, 2017, which is incorporated by reference herein in its entirety.

[0002] The present specification generally relates to the use of p-type dopants in thin film photovoltaic devices and, more specifically, to the use of group V p-type dopants in thin film photovoltaic devices.

[0003] A photovoltaic device generates electrical power by converting light into direct current electricity using semiconductor materials that exhibit the photovoltaic effect. Certain types of semiconductor material can be difficult to manufacture. For example, thin film layers provided adjacent to semiconductor material can lead to moperability or instability of the photovoltaic device. The use of group V elements as a dopant for a p-type semiconductor can be particularly difficult.

[0004] Accordingly, a need exists for alternative thin film stacks for use in thin film photovoltaic devices incorporating group V p-type dopants.SUMMARY

[0005] The embodiments provided herein relate to thin-film stacks for use with groupV dopants. These and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description, in conjunction with the drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments set forth in the drawings are illustrative and exemplary in nature and not intended to limit the subject matter defined by the claims. The following detailed description of the illustrative embodiments can be understood when read inconjunction with the following drawings, where like structure is indicated with like reference numerals and in which:

[0007] FIG. 1 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein;

[0008] FIG. 2 schematically depicts a substrate according to one or more embodiments shown and described herein;

[0009] FIG. 3 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein; and

[0010] FIGS, 4 and 5 schematically depict film stacks for forming absorber layers of photovoltaic devices according to one or more embodiments shown and described herein.DETAILED DESCRIPTION

[0011] Thin film photovoltaic devices can include multiple layers created on a substrate (or superstrate). For example, a photovoltaic device can include a barrier layer, a transparent conductive oxide (TCO) layer, a buffer layer, an absorber layer, and a back contact layer formed in a stack on a substrate. Each layer may in turn include more than one layer or film. For example, absorber layer can be formed from a plurality of semiconductor layers.

[0012] Referring now to FIG. 1, an embodiment of a photovoltaic device 100 is schematically depicted. The photovoltaic device 100 can be configured to receive light and transform light into electrical signals, e.g., photons can be absorbed from the light and transformed into electrical signals via the photovoltaic effect. Accordingly, the photovoltaic device 100 can define an energy side 102 configured to be exposed to a light source such as, for example, the sun. The photovoltaic device 102 can also define an opposing side 104 offset from the energy side 102. It is noted that the term "light" can refer to various wavelengths of the electromagnetic spectrum such as, but not limited to, wavelengths in the ultraviolet (UV), infrared (IR), and visible portions of the electromagnetic spectrum. The photovoltaic device 100 can include a plurality of layers disposed between the energy side 102 and the opposing side 104. As used herein, the term "layer" can refer to a thickness of material provided upon a surface. Additionally, each layer can cover all or any portion of the surface.

[0013] The photovoltaic device 100 can include a substrate 110 configured to facilitate the transmission of light into the photovoltaic device 100. The substrate 110 can be disposedat the energy side 102 of the photovoltaic device 100, Referring collectively to FIGS. 1 and 2, the substrate 110 can have a first surface 112 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 114 substantially facing the opposing side 104 of the photovoltaic device 100. One or more layers of material can be disposed between the first surface 1 12 and the second surface 1 14 of the substrate 110.

[0014] Referring collectively to FIGS. 1 and 2, the substrate 110 can include a transparent layer 120 having a first surface 122 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 124 substantially facing the opposing side 104 of the photovoltaic device 100. The transparent layer 120 can be formed from a substantially transparent material such as, for example, glass. Suitable glass can include soda-lime glass, or any glass with reduced iron content. The transparent layer 120 can have any suitable transmittance, including about 250 ran to about 1,300 ran in some embodiments. The transparent layer 120 may also have any suitable transmission percentage, including, for example, more than about 50% in one embodiment, more than about 60% in another embodiment, more than about 70% in yet another embodiment, more than about 80% in a further embodiment, or more than about 85% in still a further embodiment, in one embodiment, transparent layer 120 can be formed from a glass with about 90% transmittance. Optionally, the substrate 110 can include a coating 126 applied to the first surface 122 of the transparent layer 120. The coating 126 can be configured to interact with light or to improve durability of the substrate 1 10 such as, but not limited to, an antireflective coating, an antisoiling coating, or a combination thereof.

[0015] Referring again to FIG, 1 , the photovoltaic device 100 can include a barrier layer130 configured to mitigate diffusion of contaminants (e.g. sodium) from the substrate 1 10, which could result in degradation or delamination. The barrier layer 130 can have a first surface 132 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 134 substantially facing the opposing side 104 of the photovoltaic device 100. in some embodiments, the barrier layer 130 can be provided adjacent to the substrate 110. For example, the first surface 132 of the barrier layer 130 can be provided upon the second surface 114 of the substrate 100.

[0016] Generally, the barrier layer 130 can be substantially transparent, thermally stable, with a reduced number of pin holes and having high sodium-blocking capability, and good adhesive properties. Alternatively or additionally, the barrier layer 130 can be configured to apply color suppression to the light. The barrier layer 130 can include one or more layers ofsuitable material, including, but not limited to, tin oxide, silicon dioxide, aluminum-doped silicon oxide, silicon oxide, silicon nitride, or aluminum oxide. The barrier layer 130 can have any suitable thickness bounded by the first surface 132 and the second surface 134, including, for example, more than about 500 A in one embodiment, more than about 750 A in another embodiment, or less than about 1200 A in a further embodiment.

[0017] Referring still to FIG. 1, the photovoltaic device 100 can include a transparent conductive oxide (TCO) layer 140 configured to provide electrical contact to transport charge carriers generated by the photovoltaic device 100. The TCO layer 140 can have a first surface 142 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 144 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the TCO layer 140 can be provided adjacent to the barrier layer 130. For example, the first surface 142 of the barrier layer 140 can be provided upon the second surface 134 of the barrier layer 130. Generally, the TCO layer 140 can be formed from one or more layers of n-type semiconductor material that is substantially transparent and has a wide band gap. Specifically, the wide band gap can have a larger energy value compared to the energy of the photons of the light, which can mitigate undesired absorption of light. The TCO layer 140 can include one or more layers of suitable material, including, but not limited to, tin dioxide, doped tin dioxide (e.g., F-Sn02), indium tin oxide, or cadmium stannate.

[0018] The photovoltaic device 100 can include a buffer layer 150 configured to provide an insulating layer between the TCO layer 140 and any semiconductor layers. The buffer layer 150 can have a first surface 152 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 154 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the buffer layer 150 can be provided adjacent to the TCO layer 140. For example, the first surface 152 of the buffer layer 150 can be provided upon the second surface 144 of the TCO layer 140. The buffer layer 140 may include material having higher resistivity than the TCO later 140, including, but not limited to, intrinsic tin dioxide, zinc magnesium oxide (e.g., Zni-xMgxO), silicon dioxide (Sn02), aluminum oxide (AI2O3), aluminum nitride (A1N), zinc tin oxide, zinc oxide, tin silicon oxide, or a combination thereof. Generally, the material of the buffer layer 150 can be configured to substantially match the band gap of an adjacent semiconductor layer (e.g., an absorber). The buffer layer 150 may have any suitable thickness between the first surface 152 and the second surface 154, including, for example, more than about 100 A in one embodiment, between about100 A and about 800 A in another embodiment, or between about 150 A and about 600 A in a further embodiment.

[0019] The photovoltaic device 100 can include an absorber layer 160 configured to form a p-n junction within the photovoltaic device 100. Accordingly, absorbed photons of the light can free electron-hole pairs and generate carrier flow, which can yield electrical power. The absorber layer 160 can have a first surface 162 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 164 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the absorber layer 160 can be defined between the first surface 162 and the second surface 164. The thickness of the absorber layer 160 can be between about 0.5 μπι to about 10 μηι such as, for example, between about 1 μπι to about 7 μιη in one embodiment, or between about 2 μιη to about 5 μιη in another embodiment. The absorber layer 160 can further include a midpoint 165 located in the middle of the thickness of the absorber layer 160, i.e., located at the 50% location between the first surface 162 and the second surface 164 of the absorber layer 160.

[0020] Referring still to FIG. 1, the absorber layer 160 can be formed from a p-type semiconductor material having an excess of positive charge carriers, i.e., holes. The absorber layer 160 can include any suitable p-type semiconductor material, including, for example, semi-conductor materials formed from cadmium, tellurium, selenium, sulfur, or any combination thereof. Specific examples include, but are not limited to, cadmium telluride, ternaries of cadmium, selenium and tellurium (e.g., CdSexTei.x,), ternaries of cadmium, sulfur, and tellurium (e.g., CdSxTei-x,), quaternaries of cadmium, selenium, sulfur, and tellurium, or their equivalent. In embodiments where the absorber layer 160 comprises selenium and cadmium, the atomic percent of the selenium can be greater than about 0 atomic percent and less than about 20 atomic compared to cadmium, it is noted that the atomic percent described herein is representative of the entirety of the absorber layer 160, the atomic percentage of material at a particular location within the absorber layer 160 can vary with thickness compared to the overall composition of the absorber layer 160. In embodiments where the absorber layer 160 comprises sulfur and cadmium, the atomic percent of the sulfur can be greater than about 0 atomic percent and less than about 20 atomic compared to cadmium, it is noted that the concentration of tellurium can vary through the thickness of the absorber layer 160. For example, when the absorber layer 160 comprises a ternary of cadmium, selenium, and tellurium (CdSexTei-x), x can vary in the absorber layer 160 with distance from the first surface 162 of the absorber layer 160, Similarly, when the absorber layer 160 comprises a ternary ofcadmium, sulfur, and tellurium (CdSxTei-x), x can vary in the absorber layer 160 with distance from the first surface 162 of the absorber layer 160.

[0021] According to the embodiments provided herein, the absorber layer 1 60 can be doped with a dopant configured to manipulate the charge carrier concentration. In some embodiments, the absorber layer can be doped with a group V dopant such as, for example, arsenic, phosphorous, antimony, or a combination thereof. The total dosage of the group V dopant within the absorber layer 160 can be controlled. In some embodiments, the total dosage of the group V dopant in the absorber layer 160 is greater than about 0 atomic % and less than about atomic 0.1 %, such as, for example, greater than about 0.001 atomic % and less than about 0.05 atomic % in one embodiment. Alternatively or additionally, the percent concentration profile of the group V dopant through the thickness of the absorber layer 160. Specifically, the amount of the group V dopant can vary with distance from the first surface 162 of the absorber layer 160. Furthermore, the concentration of oxygen in the absorber layer 160 can be controlled. Specifically, an average concentration of oxygen in the absorber layer 160, measured between the first surface 162 of the absorber layer 160 and the midpoint 165 of the absorber layer 160, can be less or equal to about 3xl017cm"3such as, for example, less than or equal to about 2xl Qi7cm"3in one embodiment, between about 5x l0i5cm"Jand about 3xlOi 7cnv3in another embodiment, or between about 5xl0l5cm"3and about 2xlOi 7cm"3in a further embodiment. It is noted that the average concentration of oxygen was detennined using Time-of-Fltght Secondary' Ion Mass Spectrometry (TOF-SIMS).

[0022] In some embodiments, the absorber layer 160 can include absorber buffer interface region 166 formed adjacent to the first surface 162 of the absorber layer 160, and a bulk portion 168 from adjacent to the absorber buffer interface region 166, i.e., between the absorber buffer interface region 1 66 and the second surface 164 of the absorber layer 160. For example, the absorber buffer interface region 166 can span the fi rst 10% of the thickness of the absorber layer 160 from the first surface 162 and the bulk portion 168 can span the remainder of the thickness of the absorber layer 160. In embodiments where the group V dopant comprises arsenic, the percent concentration profile of arsenic in the absorber buffer interface region 166 can differ from the percent concentration profile of arsenic in the bulk portion 168.

[0023] Referring still to FIG. 1, the p-n junction can be formed by providing the absorber layer 1 60 sufficiently close to a portion of the photovoltaic device 100 having an excess of negative charge carriers, i.e., electrons. In some embodiments, the absorber layer 160 can be provided adjacent to n-type semiconductor material. Alternatively, one or moreintervening layers can be provided between the absorber layer 160 and n-type semiconductor material, in some embodiments, the absorber layer 160 can be provided adjacent to the buffer layer 150. For example, the first surface 162 of the absorber layer 160 can be provided upon the second surface 154 of the buffer layer 150.

[0024] Referring now to FIG. 3, in some embodiments, a photovoltaic device 200 can include a window layer 170 comprising n-type semiconductor material. The absorber layer 160 can be formed adjacent to the window layer 170. The window layer 170 can have a first surface 172 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 174 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the window layer 170 can be positioned between the absorber layer 160 and the T'CO layer 140. In one embodiment, the window layer 170 can be positioned between the absorber layer 160 and the buffer layer 140. The window layer 170 can include any suitable material, including, for example, cadmium sulfide, zinc sulfide, cadmium zinc sulfide, zinc magnesium oxide, or any combination thereof.

[0025] Referring collectively to FIGS. 1 and 3, the photovoltaic device 100 can include a back contact layer 180 configured to mitigate undesired alteration of the group V dopant and to provide electrical contact to the absorber layer 160. The back contact layer 180 can have a first surface 182 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 184 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the back contact layer 180 can be defined between the first surface 182 and the second surface 184. The thickness of the back contact layer 180 can be between about 5 ran to about 200 ran such as, for example, between about 10 ran to about 50 ran in one embodiment.

[0026] In some embodiments, the back contact layer 180 can be provided adjacent to the absorber layer 160. For example, the first surface 182 of the back contact layer 180 can be provided upon the second surface 164 of the absorber layer 160. In some embodiments, the back contact layer 180 can be substantially copper free, i.e., can be formed from materials that do not include copper. Without being bound to theory, it is believed that copper can interfere with group V dopants (e.g., arsenic). Specifically, the back contact layer 180 can include any suitable material such as, for example, nitrogen-doped zinc telluride (ZnT'e), or the like.

[0027] The photovoltaic device 100 can include a conducting layer 190 configured to provide electrical contact with the absorber layer 160. The back conducting layer 190 can have a first surface 192 substantially facing the energy side 102 of the photovoltaic device 100 anda second surface 194 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the conducting layer 190 can be provided adjacent to the back contact layer 180. For example, the first surface 192 of the conducting layer 190 can be provided upon the second surface 184 of the back contact layer 180. The conducting layer 190 can include any suitable conducting material such as, for example, molybdenum nitride (MoNx) doped with aluminum, molybdenum, or the like.

[0028] The photovoltaic device 100 can include a back support 196 configured to cooperate with the substrate 110 to form a housing for the photovoltaic device 100, The back support 196 can be disposed at the opposing side 102 of the photovoltaic device 100. For example, the back support 196 can be formed adjacent to conducting layer 190. The back support 196 can include any suitable material, including, for example, glass (e.g., soda-lime glass).

[0029] Referring collectively to FIGS. 4 and 5, the absorber layer 160 can be formed from a plurality of semiconductor layers 210. For example, the semiconductor layers 210 can be provided as a stack of thin films deposited upon one another using any known deposition technique, including vapor transport deposition. Each of the semiconductor layers 210 can include any suitable p-type semiconductor material, including, for example, semiconductor materials formed from cadmium, tellurium, selenium, sulfur, or any combination thereof. In some embodiments, the material composition of the semiconductor layers 210 can vary. After deposition, the semiconductor layers 210 can be annealed, which can cause the semiconductor layers 210 to diffuse into one another to form a blended material composition having the characteristics described above with respect to the absorber layer 160. In some embodiments, one or more of the semiconductor layers 210 can be provided as a doped layer, i.e., doped with a group V dopant as described herein. In further embodiments, a majority of the absorber layer 160 can be formed from the doped layer, i.e., the doped layer can be the thickest of the semiconductor layers 210,

[0030] With reference to FIG. 4, in some embodiments, the semiconductor layers 210 can comprise a first semiconductor layer 212, a second semiconductor layer 214, and a third semiconductor layer 216. The first semiconductor layer 212 can be the layer nearest to the first surface 162 of the absorber layer 160. The third semiconductor layer 216 can be the layer nearest to the second surface 164 of the absorber layer 160. The second semiconductor layer 214 can be positioned between the first semiconductor layer 212 and the third semiconductor layer 216. In one embodiment, the first semiconductor layer 212 can comprise cadmiumselenide (CdSe), the second semiconductor layer 214 can comprise cadmium teliuride (CdTe), and the third semiconductor layer 216 can comprise cadmium teliuride (CdTe) doped with arsenic. The third semiconductor layer 216 can be the thickest layer, and the second semiconductor layer 214 can be thicker than the first semiconductor layer 212. For example, a ratio of the thickness of the third semiconductor layer 216 to the first semiconductor layer 212 can be greater than about 4 such as, for example, greater than about 6 in one embodiment, or greater than about 8 in another embodiment. A ratio of the thickness of the second semiconductor layer 214 to the first semiconductor layer 212 can be greater than about 1 , 1 and less than about 10 such as, for example, greater than about 1 .25 and less than about 5 in one embodiment.

[0031] In another embodiment, the first semiconductor layer 212 can comprise cadmium teliuride (CdTe), the second semiconductor layer 214 can comprise cadmium selenide (CdSe), and the third semiconductor layer 216 can comprise cadmium teliuride (CdTe) doped with arsenic. The third semiconductor layer 21 6 can be the thickest layer, and the second semiconductor layer 214 can be thicker than the first semiconductor layer 212.

[0032] In yet another embodiment, the first semiconductor layer 212 can comprise a ternary of cadmium, selenium and tellurium (e.g., CdSexTei-x,), the second semiconductor layer 214 can comprise cadmium teliuride (CdTe), and the third semiconductor layer 216 can comprise cadmium teliuride (CdTe) doped with arsenic. The third semiconductor layer 216 can be the thickest layer, and the first semiconductor layer 212 can be thicker than the second semiconductor layer 214.

[0033] In a further embodiment, the first semiconductor layer 212 can comprise cadmium sulfide (CdS), the second semiconductor layer 214 can comprise cadmium teliuride (CdTe), and the third semiconductor layer 216 can comprise cadmium teliuride (CdTe) doped with arsenic. The third semiconductor layer 216 can be the thickest layer, and the second semiconductor layer 214 can be thicker than the first semiconductor layer 212.

[0034] Referring still to FIG. 4, in some embodiments, the first semiconductor layer212 can comprise cadmium teliuride (CdTe), the second semiconductor layer 214 can comprise cadmium selenide (CdSe) doped with arsenic, and the third semiconductor layer 216 can comprise cadmium teliuride (CdTe), Alternatively, the third semiconductor layer 216 can comprise cadmium teliuride (CdTe) doped with arsenic. The third semiconductor layer 216 can be the thickest layer, and the second semiconductor layer 214 can be thicker than the firstsemiconductor layer 212. For example, a ratio of the thickness of the third semiconductor layer 216 to the first semiconductor layer 212 can be greater than about 10 such as, for example, greater than about 20 in one embodiment, or greater than about 25 in another embodiment. A ratio of the thickness of the second semiconductor layer 214 to the first semiconductor layer 212 can be greater than about 1.1 and less than about 10 such as, for example, greater than about 1.25 and less than about 5 in one embodiment.

[0035] According to the embodiments provided herein, the first semiconductor layer212 can comprise cadmium telluride (CdTe), the second semiconductor layer 214 can comprise cadmium selenide (CdSe), and the third semiconductor layer 216 can comprise cadmium telluride (CdTe) doped with arsenic. The third semiconductor layer 216 can be the thickest layer, and the second semiconductor layer 214 can be thicker than the first semiconductor layer 212. For example, a ratio of the thickness of the third semiconductor layer 216 to the first semiconductor layer 212 can be greater than about 10, and a ratio of the thickness of the second semiconductor layer 214 to the first semiconductor layer 212 can be greater than about 1.1 and less than about 10.

[0036] With reference to FIG. 5, in some embodiments, the semiconductor layers 220 can comprise a first semiconductor layer 222, and a second semiconductor layer 224. The first semiconductor layer 222 can be the layer nearest to the first surface 162 of the absorber layer 160. The second semiconductor layer 224 can be the layer nearest to the second surface 164 of the absorber layer 160. In one embodiment, the first semiconductor layer 222 can comprise cadmium selenide (CdSe) doped with arsenic, and the second semiconductor layer 224 can comprise cadmium telluride (CdTe) doped with arsenic. The second semiconductor layer 224 can be thicker than the first semiconductor layer 222. For example, a ratio of the thickness of the second semiconductor layer 224 to the first semiconductor layer 222 can be greater than about 6 such as, for example, greater than about 8 in one embodiment, or greater than about 10 in another embodiment,

[0037] In another embodiment, the first semiconductor layer 222 can comprise cadmium selenide (CdSe), and the second semiconductor layer 224 can comprise cadmium telluride (CdTe) doped with arsenic. The second semiconductor layer 224 can be thicker than the first semiconductor layer 222. For example, a ratio of the thickness of the second semiconductor layer 224 to the first semiconductor layer 222 can be greater than about 7 such as, for example, greater than about 9 in one embodiment, or greater than about 10 in another embodiment.

[0038] it should now be understood that the embodiments described herein relate to thin film photovoltaic devices and thin film stacks for use with photovoltaic devices that facilitate the use of group V dopants within p~type semiconductor materials. The described film stacks can provide for operational group V doped p-type CdTe solar devices. Moreover, the back contacts described herein can be provided with copper free material to improve the stability of the dopants.

[0039] According to the embodiments provided herein, a method for forming a photovoltaic device can include depositing a plurality of semiconductor layers. The plurality of semiconductor layers can include a doped layer that is doped with a group V dopant. The doped layer can include cadmium selenide or cadmium telluride. The method can include annealing the plurality of semiconductor layers to form an absorber layer. The absorber layer can include cadmium, selenium, and tellurium. A total dosage of the group V dopant in the absorber layer can be greater than 0 atomic % and less than 0.1 atomic %.

[0040] In a further embodiment, a photovoltaic device can include an absorber layer and a back contact layer. The absorber layer can have a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device. The absorber layer can include cadmium and tellurium. The absorber layer can be doped with a group V dopant. The back contact layer can be provided upon the second surface of the absorber layer. The back contact layer can include nitrogen-doped zinc telluride,

[0041] In another embodiment, a photo voltaic device can include an absorber layer and a back contact layer. The absorber layer can have a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device. The absorber layer can include cadmium and tellurium. The absorber layer can be doped with a group V dopant. The back contact layer can be provided upon the second surface of the absorber layer. The back contact layer can be substantially free of copper.

[0042] In yet another embodiment, photovoltaic device can include a buffer layer and an absorber layer. The buffer layer can have a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device. The absorber layer can be provided upon the second surface of the buffer layer. The absorber layer can be formed from a plurality of semiconductor layers. The plurality of semiconductor layers can include a doped layer comprising cadmium and tellurium. The doped layer can be doped with a group V dopant.

[0043] it is noted that the terms "substantially" and "about" may be utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation, These terms are also utilized herein to represent the degree by which a quantitative representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue.

[0044] While particular embodiments have been illustrated and described herein, it should be understood that various other changes and modifications may be made without departing from the spirit and scope of the claimed subject matter. Moreover, although various aspects of the claimed subject matter have been described herein, such aspects need not be utilized in combination. It is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the claimed subject matter.

Claims

What is claimed is:

1. A method for forming a photovoltaic device comprising:depositing a plurality of semiconductor layers, wherein:the plurality of semiconductor layers comprise a doped layer that is doped with a group V dopant, andthe doped layer comprises cadmium selenide, cadmium telluride, or a combination thereof; andannealing the plurality of semiconductor layers, whereby an absorber layer is formed, wherein:the absorber layer comprises cadmium, selenium, and tellurium, and a total dosage of the group V dopant in the absorber layer is greater than 0% and less than 0.1 %.

2. The method of claim 1 , wherein the doped layer comprises cadmium telluride, and the plurality of semiconductor layers comprises an additional layer comprising cadmium selenide.

3. The method of claim 2, wherein the additional layer is doped with arsenic.

4. The method of claim 2, wherein the doped layer is thicker than the additional layer,5. The method of claim 4, wherein a ratio of a thickness of the doped layer to a thickness of the additional layer is greater than 6,6. The method of claim 2, wherein the plurality of semiconductor layers comprises a third layer comprising cadmium telluride.

7. The method of claim 6, wherein the additional layer is positioned between the doped layer and the third layer.

8. The method of claim 7, wherein the doped layer is a thickest layer, and the additional layer is thicker than the third layer.

9. The method of claim 8, wherein a ratio of a thickness of the doped layer to a thicknessof the third layer is greater than 10.

10. The method of claim 6, wherein the third layer is positioned between the doped layer and the additional layer.

11. The method of claim 10, wherein the doped layer is a thickest layer, and the doped layer is thicker than the additional layer.

12. The method of claim 1 1 , wherein a ratio of a thickness of the doped layer to a thickness of the additional layer is greater than 4.

13. The method of claim 1, comprising forming a back contact layer adjacent to the absorber layer, wherein the back contact is substantially free of copper.

14. The method of claim 13, wherein:the absorber layer has a first surface and a second surface offset by a thickness;the back contact is formed upon the second surface of the absorber layer; and an average concentration of oxygen in the absorber layer measured between a first surface of the absorber layer and a midpoint of the absorber layer is less than 3x1017cm"3.

15. The method of claim 13, wherein the back contact layer comprises nitrogen-doped zinc telluride.

16. The method of claim 15, comprising forming a conducting layer adjacent to the back contact layer.

17. The method of claim 1, wherein the plurality of semiconductor layers are deposited upon a buffer layer, and the absorber layer has a first surface adjacent to the buffer layer.

18. The method of claim 17, wherein the doped layer is further from the buffer layer than any other layer of the plurality of semiconductor layers.

19. The method of claim 18, wherein:an absorber buffer interface region is formed adjacent to the first surface of the absorberlayer;a percent concentration profile of the Group V dopant is formed in the absorber layer with distance from the first surface of the absorber layer; andthe percent concentration profile of arsenic at the absorber buffer interface differs from the percent concentration profile of arsenic in a bulk portion of the absorber layer,20. The method of claim 17, wherein the buffer layer comprises intrinsic tin dioxide, zinc magnesium oxide, silicon dioxide, aluminum oxide, aluminum nitride, or a combination thereof,21. The method of claim 1, wherein the group V dopant is arsenic.

22. The method of claim 1, wherein a majority of the absorber layer is formed from the doped layer.

23. The method of claim 1, wherein the absorber layer has a thickness between about 0.5 μιη to about 10 μιη.

24. The method of claim 1 , wherein the group V dopant comprises arsenic, phosphorous, antimony, or a combination thereof.

25. The method of claim 1, wherein the absorber layer comprises a ternary of cadmium, selenium, and tellurium.

26. The method of claim 25, wherein the absorber layer comprises greater than about 0 atomic percent and less than about 20 atomic percent of selenium compared to cadmium.

27. A photovoltaic device comprising:an absorber layer having a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device, wherein:the absorber layer comprises cadmium and tellurium, andthe absorber layer is doped with a group V dopant, anda back contact layer provided upon the second surface of the absorber layer, wherein the back contact layer comprises nitrogen -doped zinc telluride.

28. A photovoltaic device comprising:an absorber layer having a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device, wherem:the absorber layer comprises cadmium and tellurium, andthe absorber layer is doped with a group V dopant, anda back contact layer provided upon the second surface of the absorber layer, wherein the back contact layer is substantially free of copper.

29. The photovoltaic device of any of claims 27-28, comprising a substrate disposed at the energy side of the photovoltaic device.

30. The photovoltaic device of any of claims 27-29, comprising a barrier layer provided upon the substrate.

31. The photovoltaic device of any of claims 27-30, comprising a transparent conductive oxide layer provided upon the barrier layer,32. The photovoltaic device of any of claims 27-31, comprising a buffer layer provided upon the transparent conductive oxide layer.

33. The photovoltaic device of any of claims 27-32, comprising a buffer layer adjacent to the absorber layer.

34. The photovoltaic device of claim 33, wherem:an absorber buffer interface region is formed adjacent to the first surface of the absorber layer;the group V dopant comprises arsenic;a percent concentration profile of arsenic is formed in the absorber layer with distance from the first surface of the absorber layer; andthe percent concentration profile of arsenic at the absorber buffer interface differs from the percent concentration profile of arsenic in a bulk portion of the absorber layer.

35. The photovoltaic device of claim of any of ciaims 33-34, wherein the buffer layercomprises intrinsic tin dioxide.

36. The photovoltaic device of claim 33-35, wherein the buffer layer comprises zinc magnesium oxide.

37. The photovoltaic device of claim 33-36, wherein the buffer layer comprises silicon dioxide.

38. The photovoltaic device of claim 33-37, wherem the buffer layer comprises aluminum oxide.

39. The photovoitaic device of claim 33-38, wherein the buffer layer comprises aluminum nitride.

40. The photovoltaic device of claim 33-39, comprising a conducting layer adjacent to the back contact layer.

41. The photovoltaic device of claim 40, wherein the conducting layer comprises molybdenum nitride doped with aluminum.

42. The photovoltaic device of any of claims 27-41, wherein the back contact layer is substantially free of copper.

43. The photovoltaic device of any of claims 27-42, wherein the absorber layer has a thickness between about 0.5 μηι to about 10 μιη.

44. The photovoltaic device of any of claims 27-43, wherein the group V dopant is arsenic.

45. The photovoltaic device of any of claims 27-43, wherein the group V dopant is phosphorous.

46. The photovoltaic device of any of claims 27-43, wherein the group V dopant is antimony.

47. The photovoltaic device of claim 44, wherein a total dosage of arsenic in the absorber layer is greater than 0% and less than about 0.1 %.

48. The photovoltaic device of any of claims 27-47, wherein the absorber layer comprises selenium.

49. The photovoltaic device of any of claims 27-47, wherein the absorber layer comprises sulfur.

50. The photovoltaic device of claim 48, wherein the absorber layer comprises a ternary of cadmium, selenium, and tellurium.

51. The photovoltaic device of claim 50, wherein the ternary of cadmium, selenium, and tellurium is given by the formula CdSexTei-xand x varies in the absorber layer with distance from the first surface of the absorber layer.

52. The photovoltaic device of claim 50, wherein the ternary of cadmium, selenium, and tellurium is doped with the group V dopant, and wherein the group V dopant comprises arsenic.

53. The photovoltaic device of any of claims 27-52, wherein the absorber layer comprises greater than about 0 atomic percent and less than about 20 atomic percent of selenium compared to cadmium.

54. The photovoltaic device of any of claims 27-53, wherein the absorber layer comprises greater than about 0 atomic percent and less than about 20 atomic percent of sulfur compared to cadmium.

55. A photovoltaic device comprising:a buffer layer having a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device; andan absorber layer provided upon the second surface of the buffer layer, wherein: the absorber layer is formed from a plurality of semiconductor layers, the plurality of semiconductor layers comprises a doped layer comprising cadmium and tellurium, andthe doped layer is doped with a group V dopant.

56. The photovoltaic device of claim 55, comprising a substrate disposed at the energy side of the photovoltaic device.

57. The photovoltaic device of any of claims 55-56, comprising a barrier layer provided upon the substrate.

58. The photovoltaic device of any of claims 55-57, comprising a transparent conductive oxide layer provided upon the barrier layer,59. The photovoltaic device of any of claims 55-58, wherein the buffer layer comprises intrinsic tin dioxide.

60. The photovoltaic device of any of claims 55-59, wherein the buffer layer comprises zinc magnesium oxide.

61. The photovoltaic device of claim 55-60, wherein the second surface of the buffer layer is formed from zinc magnesium oxide.

62. The photovoltaic device of any of claims 55-61, wherein the buffer layer comprises silicon dioxide.

63. The photovoltaic device of any of claims 55-62, wherein the buffer layer comprises aluminum oxide.

64. The photovoltaic device of any of claims 55-63, wherein the buffer layer comprises aluminum nitride.

65. The photovoltaic device of any of claims 55-64, wherein the doped layer is further from the second surface of the buffer layer than any other layer of the plurality of semiconductor layers.The photovoltaic device of any of claims 55-65, wherein a majority of the absorberlayer is formed from the doped layer.

67. The photovoltaic device of any of claims 55-66, wherein the plurality of semiconductor layers comprises an additional layer positioned between the second surface of the buffer layer and the doped layer.

68. The photovoltaic device of claim 67, wherein the additional layer is doped with arsenic.

69. The photovoltaic device of any of claims 67-68, wherein the additional layer comprises cadmium and tellurium.

70. The photovoltaic device of any of claims 67-68, wherein the additional layer comprises cadmium and selenium.

71. The photovoltaic device of any of claims 67-70, wherein the additional layer comprises a ternary of cadmium, selenium, and tellurium.

72. The photovoltaic device of any of claims 55-71, wherein the plurality of semiconductor layers comprises a third layer positioned between the second surface of the buffer layer and the additional layer.

73. The photovoltaic device of claim 72, wherein the third layer comprises cadmium and tellurium.

74. The photovoltaic device of claim 72, wherein the third layer comprises cadmium and selenium.

75. The photovoltaic device of claim 72, wherein the third layer comprises a ternary of cadmium, selenium, and tellurium.

76. A photovoltaic device comprising:a buffer layer having a first surface facing an energy side of the photovoltaic device and a second surface facing an opposing side of the photovoltaic device; andan absorber layer provided upon the second surface of the buffer layer, wherein:the absorber layer comprises cadmium, selenium, and tellurium, and a total dosage of the group V dopant in the absorber layer is greater than 0% and less than 0.1 %the absorber layer is formed from a plurality of semiconductor layers, the plurality of semiconductor layers comprises a doped layer comprising cadmium selentde or cadmium telluride, andthe doped layer is doped with a group V dopant,77. The photovoltaic device of claim 76, wherein the doped layer comprises cadmium telluride, and the plurality of semiconductor layers comprises an additional layer comprising cadmium seienide78. The photovoltaic device of any of claims 76 or 77, wherein the absorber layer has a first surface nearest an energy side of the photovoltaic device, and wherein an average concentration of oxygen in the absorber layer measured between a first surface of the absorber layer and a midpoint of the absorber layer is less than 3xl017cm"3.

79. The method or photovoltaic device of any of claim 2 or claims 77-78, wherein the additional layer is doped with arsenic.

80. The method or photovoltaic device of any of claim 2 or claims 77-79, wherein the doped layer is thicker than the additional layer.

81. The method or photovoltaic device of any of claim 2 or claims 77-80, wherein a ratio of a thickness of the doped layer to a thickness of the additional layer is greater than 6.

82. The method or photovoltaic device of any of claim 2 or claims 77-81, wherein the plurality of semiconductor layers compri ses a third layer comprising cadmium telluride.

83. The method or photovoltaic device of claim 82, wherem the additional layer is positioned between the doped layer and the third layer.

84. The method or photovoltaic device of claim 83, wherein the doped layer is a thickest layer, and the additional layer is thicker than the third layer.

85. The method or photovoltaic device of claim 84, wherein a ratio of a thickness of the doped layer to a thickness of the third layer is greater than 10.

86. The method or photovoltaic device of claim 82, wherein the third layer is positioned between the doped layer and the additional layer.

87. The method or photovoltaic device of claim 86, wherein the doped layer is a thickest layer, and the doped layer is thicker than the additional layer.

88. The method or photovoltaic device of claim 87, wherein a ratio of a thickness of the doped layer to a thickness of the additional layer is greater than 4,89. The method or photovoltaic device of any of claim 2 or claims 77-88, comprising forming a back contact layer adjacent to the absorber layer, wherein the back contact is substantially free of copper.

90. The method or photovoltaic device of claim 89, wherein the back contact layer comprises nitrogen-doped zinc telluride.

91. The method or photovoltaic device of claim 90, comprising forming a conducting layer adjacent to the back contact layer.

92. The method or photovoltaic device of any of claim 2 or claims 77-91, wherein the plurality of semiconductor layers are deposited upon a buffer layer, and the absorber layer has a first surface adjacent to the buffer layer.

93. The method or photovoltaic device of claim 92, wherein the doped layer is further from the buffer layer than any other layer of the plurality of semiconductor layers.

94. The method or photovoltaic device of any of claims 92-93, wherein:an absorber buffer interface region is formed adjacent to the first surface of the absorber layer;a percent concentration profile of the Group V dopant is formed in the absorber layerwith distance from the first surface of the absorber layer: andthe percent concentration profile of arsenic at the absorber buffer interface differs from the percent concentration profile of arsenic in a bulk portion of the absorber layer, 95. The method or photovoltaic device of any of claims 92-94, wherein the buffer layer comprises intrinsic tin dioxide, zinc magnesium oxide, silicon dioxide, aluminum oxide, aluminum nitride, or a combination thereof.

96. The method or photovoltaic device of any of claim 2 or claims 77-95, wherein the group V dopant is arsenic.

97. The method or photovoltaic device of any of claim 2 or claims 77-96, wherein a majority of the absorber layer is formed from the doped layer.

98. The method or photovoltaic device of any of claim 2 or claims 77-97, wherein the absorber layer has a thickness between about 0.5 μπι to about 10 μτη.

99. The method or photovoltaic device of any of claim 2 or claims 77-98, wherein the group V dopant comprises arsenic, phosphorous, antimony, or a combination thereof.

100. The method or photovoltaic device of any of claim 2 or claims 77-98, wherein the absorber layer comprises a ternary of cadmium, selenium, and tellurium.

101. The method or photovoltaic device of any of claim 2 or claims 77-100, wherein the absorber layer comprises greater than about 0 atomic percent and less than about 20 atomic percent of selenium compared to cadmium,102. The method of any of claim 2 or claims 79-101 , wherein an average concentration of oxygen in the absorber layer measured between a first surface of the absorber layer and a midpoint of the absorber layer is less than 3x1017cm"3.

103. The method of any of claim 2 or claims 79-102, wherein the doped layer comprises a ternary of cadmium, selenium, and tellurium.

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