The process of implementing a non-replicating physical function (PUF) based on SRAM memory utilizes error-reduction bit selection and hamming error correction codes.

Abstract

The invention relates to a process for implementing a non-replicating physical function (PUF) based on SRAM memory using error-reduction bit selection and Hamming error correction code, performed in the following steps: (i) selecting SRAM technology / device; (ii) performing an evaluation process for error-reduction bit selection; (iii) generating auxiliary data based on the threshold value T and the position of stable bits; (iv) storing auxiliary data for use on the host and device; (v) generating an output using a cryptographic hash function to enhance security; (vi) using the output of the PUF to authenticate the device or secret key. The invention also relates to a process for reproducing a non-replicating physical function (PUF) based on SRAM memory using error-reduction bit selection and Hamming error correction code, performed on an embedded device, consisting of the following steps: (i) powering on the device; (ii) reading the SRAM memory at the starting address; (iii) filtering bits by the position of stable bits; (iv) reconstruct the output value using Hamming error correction code and auxiliary data; and (v) generate the output using cryptographic hash functions.

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