Chip structure and display board

Abstract

The invention relates to the field of display technology and reveals the structure of a chip and display panel. The chip structure consists of: a first substrate, a light-emitting block, and a color-converting block. The light-shielding layer in the color-converting block may include a body and an extension distributed around the body. Light emitted by the auxiliary light-emitting functional layers in the light-emitting block is directed towards the second semiconductor layer, and after the light creates an optical waveguide phenomenon inside the second semiconductor layer, the light emitted from the edge of the second semiconductor layer can be absorbed by the extension in the light-shielding layer, and then the light leakage in the chip structure can be reduced, making the display panel integrated with the chip structure have better display performance.

Description

Chip structure and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a chip structure and a display panel. Background Art

[0002] With the development of display technology, LED display panels have become the most advantageous new generation display media and have been widely used due to their advantages of pure color, wide dynamic range, high brightness, high definition, low operating voltage, low power consumption, long life, impact resistance, large viewing angle and stable and reliable operation.

[0003] Summary of the Invention

[0004] The present invention provides a chip structure and a display panel. This can solve the problem of poor display quality of LED display panels in the prior art. The technical solution is as follows:

[0005] In one aspect, a chip structure is provided, comprising: a first substrate, a light-emitting unit, and a color conversion unit, wherein the color conversion unit is located on the light-emitting side of the light-emitting unit; the color conversion unit comprises:

[0006] a light shielding layer located on one side of the first substrate, the light shielding layer comprising: a main body portion and an extension portion arranged around the main body portion, the main body portion having a plurality of light holes;

[0007] a defining dam layer located on a side of the light-shielding layer facing away from the first substrate, the defining dam layer having a plurality of opening areas corresponding one-to-one to the plurality of light-through holes, the orthographic projections of the opening areas on the first substrate overlapping with the orthographic projections of the corresponding light-through holes on the first substrate, the orthographic projection of the main body on the first substrate overlapping with the orthographic projection of the defining dam layer on the first substrate, and the extending portion protruding from an outer contour of the defining dam layer in a direction parallel to the first substrate;

[0008] a first encapsulation layer located between the light shielding layer and the defining dam layer, the first encapsulation layer covering the main portion and at least a portion of the extending portion;

[0009] an optical functional layer located inside the opening area, at least a portion of the optical functional layer being used to convert the color of light entering the optical functional layer;

[0010] and a second encapsulation layer located on a side of the definition dam layer facing away from the first substrate, wherein the second encapsulation layer has a first contact region in contact with the first encapsulation layer, and the first contact region is arranged around the definition dam layer.

[0011] Optionally, the first contact area is in the shape of a ring, and the width of the ring ranges from 0.5 microns to 60 microns;

[0012] The shape formed by the outer contour of the first substrate is a rectangle, and the length and width of the rectangle are both less than or equal to 500 micrometers.

[0013] Optionally, in a direction parallel to the first substrate, a distance between an outer contour of the light-shielding layer and an outer contour of the first substrate is less than or equal to 20 micrometers.

[0014] Optionally, the outer contour of the first substrate is flush with the outer contour of the light shielding layer.

[0015] Optionally, the chip structure has a first side and a second side that are relatively arranged. In a direction parallel to the first substrate, the distance between the boundary contour of the light-shielding layer and the outer contour of the first substrate adjacent to the first side is a first distance, and the distance between the light-shielding layer and the boundary contour of the outer contour of the first substrate adjacent to the second side is a second distance. The sum of the first distance and the second distance is greater than or equal to 5 microns.

[0016] Optionally, an outer contour of at least one of the first encapsulation layer and the second encapsulation layer is flush with an outer contour of the first substrate.

[0017] Optionally, there is a distance between an outer contour of at least one of the first encapsulation layer and the second encapsulation layer and an outer contour of the first substrate.

[0018] Optionally, the outer side of the first substrate is a fracture surface, and the fracture surface includes: a first fracture portion, a second fracture portion, and a laser cutting portion located between the first fracture portion and the second fracture portion;

[0019] The first fracture portion and the second fracture portion show traces of stress fracture, and the laser cut portion shows traces of laser cutting ablation.

[0020] Optionally, the color conversion unit further includes: a filter layer located between the first substrate and the optical functional layer; the filter layer includes a plurality of filter units corresponding one-to-one to the plurality of light holes, and the orthographic projections of the filter units on the first substrate overlap with the orthographic projections of the corresponding light holes on the first substrate.

[0021] Optionally, the orthographic projections of the optical functional layer and the definition dam layer on the first substrate are both located within the orthographic projection of the first encapsulation layer on the first substrate;

[0022] The filter unit is located on a side of the first packaging layer facing away from the first substrate, and a portion of the first packaging layer is located in the light-through hole;

[0023] Alternatively, the light filtering unit is located on a side of the first packaging layer facing the first substrate, and at least a portion of the light filtering layer is located in the light through hole.

[0024] Optionally, the first encapsulation layer has a plurality of auxiliary openings corresponding one-to-one to the plurality of light through holes, and orthographic projections of the auxiliary openings on the first substrate overlap with orthographic projections of corresponding light through holes on the first substrate;

[0025] At least a portion of the filter unit is located in the auxiliary opening, and two oppositely disposed surfaces of the filter unit are in contact with the first substrate and the optical functional layer respectively.

[0026] Optionally, the orthographic projection of the auxiliary opening on the first substrate is located within the orthographic projection of the light-through hole on the first substrate, and a portion of the first encapsulation layer extends into the light-through hole and covers the inner wall of the light-through hole, so that the filter unit is spaced apart from the light-shielding layer.

[0027] Optionally, the light shielding layer has at least one annular through-groove, and the orthographic projections of the plurality of light holes on the first substrate are located within an area enclosed by the orthographic projections of the annular through-groove on the first substrate;

[0028] A portion of the first packaging layer is located in the annular groove.

[0029] Optionally, the orthographic projection of the annular through groove on the first substrate is located within the orthographic projection of the defining dam layer on the first substrate.

[0030] Optionally, the second encapsulation layer covers the side of the definition dam layer and the optical functional layer facing away from the first substrate, and covers the outer side of the definition dam layer; the light-emitting unit is located on the side of the second encapsulation layer facing away from the first substrate;

[0031] The orthographic projections of the definition dam layer and the optical functional layer on the first substrate are both located within the orthographic projection of the second encapsulation layer on the first substrate.

[0032] Optionally, the materials of the first encapsulation layer and the second encapsulation layer are both inorganic materials.

[0033] Optionally, the chip structure further includes: a connection layer located on the side of the second packaging layer facing away from the first substrate, the light-emitting unit is located on the side of the connection layer facing away from the first substrate, and the light-emitting unit is fixed to the side of the second packaging layer facing away from the first substrate through the connection layer.

[0034] Optionally, the light-emitting unit includes: a plurality of sub-light-emitting functional layers corresponding one-to-one to the plurality of opening areas, and the orthographic projections of the sub-light-emitting functional layers on the first substrate overlap with the orthographic projections of the corresponding opening areas on the first substrate.

[0035] Optionally, the plurality of sub-light-emitting functional layers include: a first sub-light-emitting functional layer, a second sub-light-emitting functional layer, and a third sub-light-emitting functional layer; the plurality of sub-light-emitting functional layers emit a first light in a working state, and the first light includes at least one of blue light and ultraviolet light;

[0036] The plurality of opening regions include: a first opening region, a second opening region, and a third opening region; the first opening region is arranged corresponding to the first sub-light-emitting functional layer, the second opening region is arranged corresponding to the second sub-light-emitting functional layer, and the third opening region is arranged corresponding to the third sub-light-emitting functional layer;

[0037] The optical functional layer includes: a first color conversion portion for converting the first light into red light, a second color conversion portion for converting the first light into green light, and a third color conversion portion for converting the first light into blue light or maintaining blue light; the first color conversion portion is located in the first opening area, the second color conversion portion is located in the second opening area, and the third color conversion portion is located in the third opening area.

[0038] Optionally, each of the plurality of sub-light-emitting functional layers includes: a first electrode, a first semiconductor layer, and a light-emitting layer stacked in a direction perpendicular to and toward the first substrate;

[0039] The light emitting portion further includes a second semiconductor layer and a common electrode layer, wherein the second semiconductor layer is located on the light emitting side of the plurality of sub-light emitting functional layers;

[0040] The second semiconductor layer includes: a connecting portion and an auxiliary portion arranged in a direction parallel to the first substrate, the connecting portion is connected to the sub-light-emitting functional layer, the auxiliary portion connects the connecting portions to each other, the connecting portion and the auxiliary portion are an integral structure, and the common electrode layer is connected to the auxiliary portion.

[0041] Optionally, the material of the first semiconductor layer includes P-type doped gallium nitride, and the light-emitting layer is a multi-quantum well layer;

[0042] The second semiconductor layer includes: a first sublayer and a second sublayer stacked in a direction perpendicular to and toward the first substrate, the first sublayer is located between the second sublayer and the light-emitting layer, the material of the first sublayer is N-type doped gallium nitride, and the second sublayer is a gallium nitride buffer layer.

[0043] Optionally, each sub-light-emitting functional layer further includes: a current spreading layer located between the first electrode and the first semiconductor layer.

[0044] On the other hand, a display panel is provided, comprising: a driving backplane, and a plurality of chip structures arranged in an array on one side of the driving backplane, wherein the chip structure is the above-mentioned chip structure.

[0045] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0046] A chip structure includes: a first substrate, a light-emitting unit, and a color conversion unit. The light-shielding layer in the color conversion unit may include: a main body portion and an extension portion disposed around the main body portion. Light emitted from each sub-light-emitting functional layer in the light-emitting unit is directed toward a second semiconductor layer. After light waveguides within the second semiconductor layer, light emitted from the edge of the second semiconductor layer is absorbed by the extension portion of the light-shielding layer. This reduces the probability of light leakage in the chip structure, resulting in a better display quality for a display panel incorporating this chip structure. Furthermore, a first encapsulation layer is provided between the light-shielding layer and the limiting dam layer. The first encapsulation layer covers the main body portion of the light-shielding layer, and the main body portion of the light-shielding layer overlaps with the orthographic projection of the isolation dam layer on the first substrate. Therefore, if water and oxygen from the external environment intrudes into the light-shielding layer, the water and oxygen that intrudes into the light-shielding layer are isolated by the first encapsulation layer, preventing it from further intruding into the isolation layer. This ensures that water and oxygen that intrudes into the light-shielding layer will not corrode the optical functional layer, further improving the reliability of the optical functional layer and thereby enhancing the stability of the chip structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] FIG1 is a top view of a chip structure provided in an embodiment of the present application;

[0049] FIG2 is a schematic diagram of the film layer structure of the chip structure shown in FIG1 at AA';

[0050] FIG3 is a diagram showing an effect of generating an optical waveguide phenomenon inside a second semiconductor layer according to an embodiment of the present application;

[0051] FIG4 is a schematic diagram of another film layer structure at AA' of the chip structure shown in FIG1;

[0052] FIG5 is a schematic diagram of the membrane structure of another chip structure provided by the present application;

[0053] FIG6 is a schematic diagram of a film layer structure of another chip structure provided by the present application;

[0054] FIG7 is a schematic structural diagram of a first large plate provided in an embodiment of the present application;

[0055] FIG8 is a schematic structural diagram of a first initial wafer provided in an embodiment of the present application;

[0056] FIG9 is a schematic structural diagram of a second initial wafer provided in an embodiment of the present application;

[0057] FIG10 is a schematic structural diagram of a second large plate provided in an embodiment of the present application;

[0058] FIG11 is a schematic structural diagram of a motherboard wafer provided in an embodiment of the present application;

[0059] FIG12 is a partial enlarged view of the motherboard wafer at position B in FIG11;

[0060] FIG13 is another partial enlarged view of the motherboard wafer at position B in FIG12;

[0061] FIG14 is a top view of another chip structure provided in an embodiment of the present application;

[0062] FIG15 is a schematic diagram of the outer side surface of a first substrate provided in an embodiment of the present application;

[0063] FIG16 is a top view of another chip structure provided in an embodiment of the present application;

[0064] FIG17 is a schematic diagram of the film layer structure at CC' of the chip structure shown in FIG16;

[0065] FIG18 is a schematic diagram of the film layer structure of the chip structure shown in FIG16 at position DD′;

[0066] FIG19 is a schematic diagram of a film layer structure of a chip structure provided by another embodiment of the present application;

[0067] FIG20 is a schematic diagram of a film layer structure of another chip structure provided by another embodiment of the present application;

[0068] FIG21 is a schematic diagram of a film layer structure of another chip structure provided by another embodiment of the present application;

[0069] FIG22 is a top view of a chip structure provided by yet another embodiment of the present application;

[0070] FIG23 is a schematic diagram of the film layer structure of the chip structure shown in FIG22 at EE';

[0071] FIG24 is a schematic diagram of another film layer structure at EE' of the chip structure shown in FIG22;

[0072] FIG25 is a schematic diagram of another film layer structure at EE' of the chip structure shown in FIG22;

[0073] FIG26 is a top view of a light-emitting unit located on a connecting layer provided in an embodiment of the present application;

[0074] FIG27 is a schematic diagram of the film structure of the light-emitting unit at position FF' shown in FIG26;

[0075] FIG28 is a top view of another light-emitting unit located on a connecting layer provided in an embodiment of the present application;

[0076] FIG29 is a schematic diagram of the film structure of the light-emitting unit at GG′ shown in FIG28 . DETAILED DESCRIPTION

[0077] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0078] Please refer to Figures 1 and 2. Figure 1 is a top view of a chip structure provided in an embodiment of the present application, and Figure 2 is a schematic diagram of the film layer structure of the chip structure shown in Figure 1 at the AA' position. The chip structure 000 may include: a first substrate 100, a light-emitting unit 200, and a color conversion unit 300. The color conversion unit 300 in the chip structure 000 may be located on the light-emitting side of the light-emitting unit 200. In one possible implementation, the color conversion unit 300 in the chip structure 000 may be located on one side of the first substrate 100, and the light-emitting unit 200 in the chip structure 000 may be located on the side of the color conversion unit 300 facing away from the first substrate 100. In this case, the light emitted by the light-emitting unit 200 may be directed toward the color conversion unit 300, and then pass through the color conversion unit 300 and the first substrate 100 before being emitted.

[0079] The color conversion unit 300 in the chip structure 000 may include a light shielding layer 301 , a defining dam layer 302 , an optical functional layer 303 , and a second encapsulation layer 305 .

[0080] The light shielding layer 301 in the color conversion unit 300 may be located on one side of the first substrate 100. The light shielding layer 301 may have a plurality of light through holes K1.

[0081] The defining dam layer 302 in the color conversion unit 300 can be located on the side of the light shielding layer 301 facing away from the first substrate 100. The defining dam layer 302 can have a plurality of opening areas K2 corresponding one-to-one with the plurality of light passage holes K1. Here, the orthographic projection of each opening area K2 on the first substrate 100 can overlap with the orthographic projection of the corresponding light passage hole K1 on the first substrate 100.

[0082] The optical functional layer 303 in the color conversion unit 300 can be located within the opening region K2 defining the dam layer 302. At least a portion of the optical functional layer 303 is used to convert the color of light entering the optical functional layer 303. Here, light emitted from the light-emitting unit 200 in the chip structure 000 can be directed toward the optical functional layer 303, where it is converted in color before being emitted through the through hole K1 of the light-shielding layer 301.

[0083] The second encapsulation layer 305 in the color conversion unit 300 can be located on the side of the definition dam layer 302 facing away from the first substrate 100. The second encapsulation layer 305 can encapsulate the definition dam layer 302 and the optical functional layer 303 to prevent water and oxygen in the external environment from penetrating the definition dam layer 302 and corroding the optical functional layer 303. This ensures that the optical functional layer 303 can stably convert the color of light, thereby increasing the reliability of the optical functional layer 303.

[0084] In the embodiment of the present application, the light-emitting unit 200 in the chip structure 000 may include: a plurality of sub-light-emitting functional layers 200a. The plurality of sub-light-emitting functional layers 200a in the light-emitting unit 200 may correspond one-to-one to the plurality of opening areas K2 defined in the dam layer 303. The light-emitting side of each sub-light-emitting functional layer 200a may face the corresponding opening area K2, and the orthographic projection of each sub-light-emitting functional layer 200a on the first substrate 100 may overlap with the orthographic projection of the corresponding opening area K2 on the first substrate 100. In one possible scenario, the orthographic projection of each sub-light-emitting functional layer 200a on the first substrate 100 may be located within the orthographic projection of the corresponding opening area K2 on the first substrate 100.

[0085] In this case, the light emitted by the sub-light-emitting functional layer 200a in the light-emitting unit 200 can all be directed toward the optical functional layer 303 within the corresponding opening area K2 defined in the dam layer 302. It should be noted that each sub-light-emitting functional layer 200a in the light-emitting unit 200 can emit light of the same color, and different types of optical functional layers 303 are filled within different opening areas K2. As a result, the light emitted by the sub-light-emitting functional layer 200a can be converted into light of other colors by the different types of optical functional layers 303 after passing through different opening areas K2.

[0086] It should also be noted that the light-emitting unit 200 may further include: a second semiconductor layer 200b located on the light-emitting side of the plurality of sub-light-emitting functional layers 200a. Since the light-emitting side of each sub-light-emitting functional layer 200a in the light-emitting unit 200 faces the first substrate, each sub-light-emitting functional layer 200a in the light-emitting unit 200 is distributed on the side of the same second semiconductor layer 200b facing away from the first substrate 100. In other words, the second semiconductor layer 200 is closer to the first substrate 100 than the sub-light-emitting functional layer 200a. In this way, during the light-emitting process of the sub-light-emitting functional layer 200a, the light emitted by the sub-light-emitting functional layer 200a will first pass through the second semiconductor layer 200b before being emitted to the color conversion unit 300.

[0087] However, some of the light directed toward the interior of the second semiconductor layer 200b is very likely to generate a light waveguide phenomenon within the second semiconductor layer 200b. For example, please refer to Figure 3, which is a rendering of a light waveguide phenomenon generated within the second semiconductor layer provided by an embodiment of the present application. Some of the light directed toward the second semiconductor layer 200b can undergo multiple round-trip total reflections between two opposing planes in the second semiconductor layer 200b and be laterally transmitted, ultimately exiting from the edge of the second semiconductor layer 200b. After the light waveguide phenomenon is generated within the second semiconductor layer 200b, the light emitted from the edge of the second semiconductor layer 200b may not be absorbed by the light shielding layer 301, thereby causing the chip structure 000 to be very susceptible to light leakage.

[0088] To this end, in an embodiment of the present application, the light-shielding layer 301 in the color conversion unit 300 needs to extend toward the outer contour of the first substrate 100, so that the extended light-shielding layer 301 can absorb the light emitted from the edge of the second semiconductor layer 200b, thereby reducing the probability of light leakage in the chip structure 000.

[0089] For example, as shown in FIG2 , the light shielding layer 301 may include a main portion 3011 and extensions 3012 distributed around the main portion 3011. Here, the main portion 3011 in the light shielding layer 301 may have a plurality of light holes K1, and the orthographic projection of the main portion 3011 on the first substrate 100 may overlap with the orthographic projection of the dam layer 302 in the color conversion unit 300 on the first substrate 100. The extensions 3012 in the light shielding layer 301 may protrude beyond the outer contour of the dam layer 302 in a direction parallel to the first substrate 100.

[0090] It should be noted that the outer contour of a structure in the embodiments of the present application refers to the outer boundary of the orthographic projection of the structure on the plane where the first substrate 100 is located. For example, the outer contour of the dam layer 302 refers to the outer boundary of the orthographic projection of the dam layer 302 on the plane where the first substrate 100 is located. It should also be noted that the outer boundary of the orthographic projection of a structure on the plane where the first substrate 100 is located can generally surround a closed area. For this reason, the outer contour of the structure can also surround a closed area. Here, when the extension 3012 in the light-shielding layer 301 protrudes from the outer contour of the dam layer 302 in a direction parallel to the first substrate 100, the orthographic projection of the dam layer 302 on the first substrate 100 can be located within the area enclosed by the outer contour of the light-shielding layer 301, and there is a certain distance between the outer contour of the light-shielding layer 301 and the outer contour of the dam layer 302 in a direction parallel to the first substrate 100.

[0091] In one possible scenario, the orthographic projection of the dam layer 302 on the first substrate 100 may be located within the orthographic projection of the main portion 3011 of the light shielding layer 301 on the first substrate 100, while the orthographic projection of the extension 3012 of the light shielding layer 301 on the first substrate 100 does not overlap with the orthographic projection of the dam layer 302 on the first substrate 100. In other words, the boundary line between the orthographic projection of the main portion 3011 of the light shielding layer 301 and the orthographic projection of the extension 3012 of the light shielding layer 301 on the first substrate 100 is the outer contour of the orthographic projection of the dam layer 302 on the first substrate 100.

[0092] In this case, the light emitted by each sub-light-emitting functional layer 200a in the light-emitting unit 200 is emitted toward the second semiconductor layer 200b, and after the light generates an optical waveguide phenomenon inside the second semiconductor layer 200b, the light emitted from the edge of the second semiconductor layer 200b can be absorbed by the extension portion 3012 in the light-shielding layer 301, thereby reducing the probability of light leakage in the chip structure 000, so that the display effect of the display panel integrated with this chip structure 000 is better.

[0093] Furthermore, after the light-shielding layer 301 extends toward the edge of the first substrate 100, the second encapsulation layer 305 in the color conversion unit 300 can no longer encapsulate the light-shielding layer 301. This can result in water and oxygen in the external environment invading the optical functional layer 303 through the light-shielding layer 301 and the barrier dam layer 302, potentially causing failure of the optical functional layer 300. To address this issue, a first encapsulation layer 304 is provided in the color conversion unit 300 between the light-shielding layer 301 and the limiting dam layer 302. This first encapsulation layer 304 can cover the main portion 3011 of the light-shielding layer 301 and at least a portion of the extension portion 3012 of the light-shielding layer 301.

[0094] Here, because the first encapsulation layer 304 is disposed between the light-shielding layer 301 and the limiting dam layer 302, and the first encapsulation layer 304 can cover the main portion 3011 of the light-shielding layer 301, and the main portion 3011 of the light-shielding layer 301 overlaps with the orthographic projection of the isolation dam layer 302 on the first substrate 100, after water and oxygen from the external environment intrudes into the light-shielding layer 301, the water and oxygen that intrudes into the light-shielding layer 301 can be isolated by the first encapsulation layer 304, so that such water and oxygen will no longer intrude into the isolation layer 302. This ensures that the water and oxygen that intrudes into the light-shielding layer 301 will not corrode the optical functional layer 303, further improving the reliability of the optical functional layer 303.

[0095] In the present application, the second encapsulation layer 305 in the color conversion unit 300 may contact the first encapsulation layer 304 , so that the second encapsulation layer 305 may have a first contact region 305 a in contact with the first encapsulation layer 304 , and the first contact region 305 a may be disposed around the definition dam layer 302 .

[0096] For example, the second encapsulation layer 305 can cover the side of the definition dam layer 302 and the optical functional layer 303 facing away from the first substrate 100, and can also cover the outer side of the definition dam layer 302. The orthographic projections of the definition dam layer 302 and the optical functional layer 303 on the first substrate 100 can both be located on the orthographic projection of the second encapsulation layer 305 on the substrate 100. Here, the portion of the second encapsulation layer 305 located on the outer side of the definition dam layer 303 can contact the first encapsulation layer 304 on the side facing the first substrate 100. In this way, through the cooperation of the first encapsulation layer 304 and the second encapsulation layer 305, the definition dam layer 302 and the optical functional layer 303 can be sealed, so that the optical functional layer 303 is not corroded by water and oxygen in the external environment.

[0097] In summary, the chip structure provided in the embodiments of the present application includes: a first substrate, a light-emitting unit, and a color conversion unit. The light-shielding layer in the color conversion unit may include: a main body portion and an extension portion distributed around the main body portion. Light emitted from each sub-light-emitting functional layer in the light-emitting unit is directed toward the second semiconductor layer. After the light generates an optical waveguide phenomenon within the second semiconductor layer, the light emitted from the edge of the second semiconductor layer is absorbed by the extension portion of the light-shielding layer. This reduces the probability of light leakage in the chip structure, resulting in a better display quality for a display panel integrating such a chip structure. Furthermore, a first encapsulation layer is provided between the light-shielding layer and the limiting dam layer, and the first encapsulation layer covers the main body portion of the light-shielding layer. Furthermore, the main body portion of the light-shielding layer overlaps with the orthographic projection of the isolation dam layer on the first substrate. Therefore, after water and oxygen from the external environment intrudes into the light-shielding layer, the water and oxygen that intrudes into the light-shielding layer can be isolated by the first encapsulation layer, preventing it from invading the isolation layer. This ensures that the water and oxygen that intrudes into the light-shielding layer does not corrode the optical functional layer, further improving the reliability of the optical functional layer and thereby enhancing the stability of the chip structure.

[0098] Optionally, as shown in Figure 2, the materials of both the first encapsulation layer 304 and the second encapsulation layer 305 in the color conversion unit 300 can be inorganic insulating materials. For example, the inorganic insulating material can include one or more of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the first encapsulation layer 304 and the second encapsulation layer 305 can both range from 0.5 microns to 5 microns. In this way, through the cooperation of the first encapsulation layer 304 and the second encapsulation layer 305, the dam layer 302 and the optical functional layer 303 can be isolated from the external environment, preventing water and oxygen from corroding the optical functional layer 303.

[0099] In the embodiment of the present application, the material of the first substrate 100 is glass. For example, the first substrate 100 can transmit visible light.

[0100] In the embodiment of the present application, the extension surface of the first substrate 100 (ie, the upper surface or the lower surface of the first substrate 100 ) may be a plane.

[0101] In an embodiment of the present application, the shape of the area enclosed by the outer contour of the first substrate 100 in the chip structure 000 is a rectangle, and the length and width of the rectangle are both less than or equal to 500 microns. It should be noted that the length and width of the rectangle can also be the same, that is, the shape of the area enclosed by the outer contour of the first substrate 100 can also be a square. In this case, the overall size of the chip structure 000 is relatively small. After a plurality of such chip structures 000 are fixed on the driving backplane, the resolution of the resulting display panel can be guaranteed to be high. For example, the length and width of the rectangle can both range from 200 microns to 400 microns. In this case, the preparation process of the chip structure 000 can be simplified while ensuring that the overall size of the chip structure 000 is relatively small.

[0102] Optionally, in the color conversion unit 300 in the chip structure 000 , the first contact region 305 a where the second encapsulation layer 305 contacts the first encapsulation layer 304 may be ring-shaped, and the width of the ring ranges from 0.5 micrometers to 60 micrometers.

[0103] In one possible implementation, the minimum width of the first contact region 305a where the second encapsulation layer 305 contacts the first encapsulation layer 304 is equal to the thickness of the second encapsulation layer 305 itself. In this case, as shown in FIG2 , the second encapsulation layer 305 in the color conversion unit 300 may include a first encapsulation portion 3051 and a second encapsulation portion 3052 connected to each other. The first encapsulation portion 3051 may cover the side of the dam layer 302 and the optical functional layer 303 facing away from the first substrate 100. That is, the orthographic projections of the dam layer 302 and the optical functional layer 303 on the first substrate 100 are both located within the orthographic projection of the first encapsulation portion 3051 on the first substrate 100. The second encapsulation portion 3052 may cover the outer side of the dam layer 302. The side of the second encapsulation portion 3052 in the second encapsulation layer 305 facing the first substrate 100 may contact the first encapsulation layer 304. That is, the area of ​​the second encapsulation portion 3052 in contact with the first encapsulation layer 304 is the first contact region 305a. Here, the width of the first contact region 305a is equal to the thickness of the second encapsulation portion 3052, and the thickness of the second encapsulation portion 3052 is equal to the thickness of the second encapsulation layer 305. Therefore, the minimum width of the first contact region 305a where the second encapsulation layer 305 contacts the first encapsulation layer 304 may also be in the range of 0.5 μm to 5 μm.

[0104] In another possible implementation, as shown in FIG4 , which is a schematic diagram of another film layer structure at the AA′ position of the chip structure shown in FIG1 , the second encapsulation layer 305 may further include a third encapsulation portion 3053. The third encapsulation portion 3053 may be connected to a side of the second encapsulation portion 3052 facing away from the first encapsulation portion 3051, and the third encapsulation portion 3053 may be located on a side of the first encapsulation layer 304 facing away from the first substrate 100. In this way, the first contact region 305a in the second encapsulation layer 305 that contacts the first encapsulation layer 304 may include not only the side of the second encapsulation portion 3052 facing the first substrate 100, but also the third encapsulation portion 3053. In this case, the side of the third encapsulation portion 3053 facing away from the second encapsulation portion defines the outer contour of the second encapsulation layer 305. When the outer contour of the second encapsulation layer 305 is flush with the outer contour of the first encapsulation layer 304, and the outer contours of both the first encapsulation layer 304 and the second encapsulation layer 305 are flush with the outer contour of the first substrate 100, the width of the first contact area 305a where the second encapsulation layer 305 contacts the first encapsulation layer 304 is the maximum width. This maximum width is equal to the distance between the outer contour of the dam layer 302 and the outer contour of the first substrate 100. Furthermore, since the distance between the outer contour of the dam layer 302 and the outer contour of the first substrate 100 must be less than or equal to 60 microns to ensure a close distance between two pixels in the subsequent display panel, the maximum width of the first contact area 305a where the second encapsulation layer 305 contacts the first encapsulation layer 304 must also be less than or equal to 60 microns.

[0105] It can be seen that the width of the first contact region 305 a where the second encapsulation layer 305 contacts the first encapsulation layer 304 is in a range of 0.5 μm to 60 μm.

[0106] It should be noted that, during the preparation process, the first encapsulation layer 304 and the second encapsulation layer 305 in the color conversion unit 300 may both be patterned, or both not be patterned, or one may be patterned while the other is not.

[0107] For example, when the first encapsulation layer 304 and the second encapsulation layer 305 are patterned to form the second scribe line pattern described in subsequent embodiments, the first encapsulation layer 304 and the second encapsulation layer 305 can be formed using the same patterning process. That is, after both the first encapsulation layer 304 and the second encapsulation layer 305 are formed, the patterning process is performed simultaneously. In this case, the outer contour of the second encapsulation layer 305 is flush with the outer contour of the first encapsulation layer 304.

[0108] For another example, when neither the first encapsulation layer 304 nor the second encapsulation layer 305 is patterned, in the subsequent embodiments, when forming a single chip structure 000 through a cutting process, it is necessary to simultaneously cut the first encapsulation layer 304 and the second encapsulation layer 305. In this case, the outer contour of the second encapsulation layer 305 is also flush with the outer contour of the first encapsulation layer 304.

[0109] Optionally, the chip structure 000 may further include: a connection layer 400 located on the side of the second encapsulation layer 305 facing away from the first substrate 100. Here, the light-emitting unit 200 in the chip structure 000 may be located on the side of the connection layer 400 facing away from the first substrate 100, and the light-emitting unit 200 may be fixed to the side of the second encapsulation layer 305 facing away from the first substrate 100 via the connection layer 400.

[0110] It should be noted that the color conversion unit 300 and the light emitting unit 200 in the chip structure 000 of the present application are manufactured separately and independently, and then the two are fixed together through the connection layer 400 to obtain the chip structure 000.

[0111] In some examples, multiple color conversion units 300 can first be formed on a second substrate that is connected to a larger area, and a connection layer 400 can be formed on the side of each color conversion unit 300 facing away from the second substrate. Subsequently, multiple light-emitting units 200 can be formed on a third substrate (typically a sapphire substrate or a silicon-based substrate). The third substrate is then removed, and the light-emitting units 200 are secured to the side of the corresponding color conversion unit 300 facing away from the second substrate via the connection layer 400. Finally, the second substrate can be cut using a dicing process to obtain multiple chip structures 000.

[0112] Optionally, the connection layer 400 in the chip structure 000 may include any one of an indium zinc oxide connection layer, a metal connection layer, and an adhesive layer. The principles by which the connection layer 400 secures the color conversion unit 300 and the light-emitting unit 200 together vary depending on the type of connection layer 400. Therefore, the present application will use the following three possible scenarios as examples for schematic illustration:

[0113] In the first possible scenario, when the connection layer 400 includes an adhesive layer, the connection layer 400 is a single-layer structure, and the color conversion unit 300 and the light-emitting unit 200 are bonded together through the adhesive layer. Exemplarily, the adhesive layer 133 is made of an organic adhesive material such as epoxy resin. This adhesive layer is transparent. Therefore, even if the adhesive layer covers each sub-light-emitting functional layer 200a in the light-emitting unit 200, each sub-light-emitting functional layer 200a can pass through the adhesive layer and emit light toward the corresponding opening area K2.

[0114] Regarding the second possible scenario, please refer to FIG5 , which is a schematic diagram of the film layer structure of another chip structure provided by the present application. When the connection layer 400 includes an indium zinc oxide connection layer, the connection layer 400 may include: a first indium zinc oxide layer 401 and a second indium zinc oxide layer 402 stacked together. Here, the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 may be connected by molecular bonding.

[0115] The first indium zinc oxide layer 401 can be fixed to the side of the color conversion unit 300 facing away from the first substrate 100, and the second indium zinc oxide layer 402 can be fixed to the light-emitting side of the light-emitting unit 200. In this way, the color conversion unit 300 and the light-emitting unit 200 can be fixed together through the molecular bonding between the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402.

[0116] It should be noted that the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 are both transparent conductive layers. Therefore, even if the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 cover each sub-light-emitting functional layer 200a in the light-emitting unit 200, it can be ensured that each sub-light-emitting functional layer 200a can pass through the second indium zinc oxide layer 402 and the first indium zinc oxide layer 401 and emit light toward the corresponding opening area K2.

[0117] For the third possible situation, please refer to Figure 6, which is a schematic diagram of the membrane layer structure of another chip structure provided in the present application. When the connection layer 400 includes a metal connection layer, the connection layer 400 may include: a first sub-metal layer 403, a second sub-metal layer 404 and a third sub-metal layer 405 that are stacked. The second sub-metal layer 404 may be located between the first sub-metal layer 403 and the third sub-metal layer 405, and may serve as a eutectic alloy layer connecting the first sub-metal layer 403 and the third sub-metal layer 405.

[0118] The first sub-metal layer 403 can be fixed to the side of the color conversion unit 300 facing away from the first substrate 100, and the third sub-metal layer 405 can be fixed to the light-emitting side of the light-emitting unit 200. In this way, the first sub-metal layer 403 and the third sub-metal layer 405 can be connected as a whole through the eutectic alloy layer (also known as the second sub-metal layer 404), thereby achieving fixation between the color conversion unit 300 and the light-emitting unit 200.

[0119] It should be noted that the first sub-metal layer 403, the second sub-metal layer 404 and the third sub-metal layer 405 are all reflective conductive layers. Therefore, it is necessary to set a plurality of avoidance holes K4 corresponding to the multiple sub-light-emitting functional layers 200a in the light-emitting unit 200 in the connecting layer 400 to ensure that the light emitted by each sub-light-emitting functional layer 200a can pass through the corresponding avoidance hole K4 and then be emitted to the corresponding opening area K2.

[0120] Optionally, the light-emitting unit 200 in the chip structure 000 may include multiple light-emitting chips, and each light-emitting chip may have a sub-light-emitting functional layer 200a. Here, the light-emitting chip is an LED chip. It should be noted that the LED chip can be an LED chip of ordinary size, or a mini light-emitting diode (English: mini Light-Emitting Diode, referred to as: mini-LED) chip, or a micro LED (English: Micro Light-Emitting Diode, referred to as: Micro-LED) chip. The embodiments of the present application are not limited to this.

[0121] The following embodiment will take the connection layer 400 including: a first indium zinc oxide layer 401 and a second indium zinc oxide layer 402 as an example to schematically illustrate the preparation process of the chip structure 000. Here, the preparation process of the chip structure 000 may include the following structural steps:

[0122] Step S101 : forming a first indium zinc oxide layer 401 on the color conversion unit 300 .

[0123] In an embodiment of the present application, during the preparation of the color conversion unit 300, as shown in FIG7 , which is a schematic structural diagram of a first large plate provided in an embodiment of the present application, a first large plate M comprising a plurality of color conversion units 300 arranged in an array can be simultaneously formed. Subsequently, a first indium zinc oxide layer 401 is formed on each color conversion unit 300 in the first large plate M. For example, the first indium zinc oxide layer 401 can be formed on each color conversion unit 300 through a photolithography process. The first large plate M is then cut to obtain a plurality of first initial wafers E. Each first initial wafer E can include: a second substrate, color conversion units 300 distributed on the second substrate, and a first indium zinc oxide layer 401 distributed on the side of each color conversion unit 300 facing away from the second substrate.

[0124] For example, as shown in Figures 7 and 8, Figure 8 is a schematic diagram of the structure of a first initial wafer provided in an embodiment of the present application. The first initial wafer E can be circular in shape, and the first large plate M can be cut into multiple first initial wafers E by anisotropic cutting.

[0125] Step S102 : forming a second indium zinc oxide layer 402 on the light-emitting side of the light-emitting unit 200 .

[0126] In the embodiment of the present application, the light-emitting unit 200 is formed on a third substrate. Before removing the third substrate, a temporary substrate is formed on the side of the light-emitting unit 200 facing away from the third substrate. After the temporary substrate is formed, the third substrate can be peeled off from the light-emitting unit 200. It should be noted that the light-emitting unit 200 with the temporary substrate can be referred to as the initial light-emitting unit. In other words, after removing the temporary substrate from the initial light-emitting unit, the light-emitting unit 200 can be obtained.

[0127] In one example, as shown in Figure 9, Figure 9 is a structural schematic diagram of a second initial wafer provided by an embodiment of the present application. During the preparation of the initial light-emitting unit, a plurality of light-emitting units 200 arranged in an array can be formed on a circular third substrate, and then a temporary substrate is formed on the side of the plurality of light-emitting units 200 facing away from the third substrate to obtain a plurality of initial light-emitting units. Here, the temporary substrates in each initial light-emitting unit can be connected as one, that is, the temporary substrate can be a whole substrate with a larger area, and the shape of the temporary substrate can also be circular. Finally, a second indium zinc oxide layer 402 can be formed on the side of each initial light-emitting unit facing away from the temporary substrate, and a second initial wafer containing a plurality of initial light-emitting units can be obtained.

[0128] In another example, during the preparation of the initial light-emitting units, as shown in FIG10 , which is a schematic structural diagram of a second large plate provided in an embodiment of the present application, a second large plate N comprising a plurality of arrayed initial light-emitting units can be simultaneously formed. Subsequently, a second indium zinc oxide layer 402 is formed on each initial light-emitting unit in the second large plate N. Here, the second indium zinc oxide layer 402 can be formed on the side of the light-emitting unit 200 in each initial light-emitting unit facing away from the temporary substrate. For example, a first indium zinc oxide layer 401 can be formed on each color conversion unit 300 through a photolithography process. The second large plate N is then cut to obtain a plurality of second initial wafers F. Each second initial wafer F can include a plurality of initial light-emitting units and a second indium zinc oxide layer 402 located on each initial light-emitting unit.

[0129] For example, the second initial wafer F may be circular in shape, and the second large plate N may be cut anisotropically to obtain a plurality of second initial wafers F. The shape of each second initial wafer F may refer to the second initial wafer F shown in FIG. 9 .

[0130] It should be noted that the temporary substrates within the initial light-emitting units in the second initial wafer F can be connected as one. In other words, the temporary substrate can be a larger substrate with the same shape as the second initial wafer F, and the light-emitting units 200 in the second initial wafer F can all be located on this temporary substrate.

[0131] Step S103 : bonding the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 .

[0132] In an embodiment of the present application, the bonding of the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 can be achieved, and the multiple color conversion units 300 in the first initial chip E and the multiple initial light-emitting units in the second initial chip F are bonded one-to-one.

[0133] It should be noted that the step of bonding the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 includes the following sub-steps:

[0134] Sub-step S103a: treating the surface of the first indium zinc oxide layer 401 away from the temporary substrate with oxygen plasma to activate the surface of the first indium zinc oxide layer 401.

[0135] Sub-step S103b: treating the surface of the second indium zinc oxide layer 402 away from the initial second substrate with oxygen plasma to activate the surface of the second indium zinc oxide layer 402.

[0136] Sub-step S103c: pressing the first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 together under certain temperature conditions to form the connecting layer 400.

[0137] The first indium zinc oxide layer 401 and the second indium zinc oxide layer 402 can be bonded together through the above sub-steps 103 a to 103 c.

[0138] Step S104: removing the temporary substrate to obtain a motherboard wafer.

[0139] In this embodiment of the present application, after the temporary substrate is removed from the second initial wafer F, the second substrate, the multiple color conversion units 300 located on the second substrate, and the light-emitting units 200 located on the side of each color conversion unit 300 facing away from the second substrate can be obtained. Here, the second substrate, the multiple color conversion units 300, and the multiple light-emitting units 200 located on the second substrate can be referred to as a motherboard wafer.

[0140] Step S105 , cutting the motherboard wafer to obtain a plurality of chip structures 000 .

[0141] In the embodiment of the present application, a single chip structure 000 is obtained by cutting a motherboard wafer. Please refer to Figure 11, which is a schematic diagram of the structure of a motherboard wafer provided in the embodiment of the present application. The motherboard wafer may contain multiple chip structures 000. After cutting the motherboard wafer along the cutting line L, multiple chip structures 000 are obtained. Each chip structure 000 includes the first substrate 100, the light-emitting unit 200, and the color conversion unit 300 in the above-mentioned embodiment. Here, during the cutting process of the motherboard wafer, it is necessary to cut the second substrate of the motherboard wafer that is connected to the motherboard wafer and has a larger area. After cutting the second substrate, multiple chip structures 000 are obtained, and the first substrate 100 in each chip structure 000 is a portion of the second substrate in the motherboard wafer.

[0142] In the present application, since the defined dam layer 302 in the color conversion unit 300 needs to be encapsulated by the first encapsulation layer 304 and the second encapsulation layer 305. Therefore, before the motherboard wafer is cut, the defined dam layers 302 in each chip structure 000 are distributed independently of each other. In this way, after the motherboard wafer is cut, each position in the defined dam layer 302 in each chip structure 000 can be encapsulated by the first encapsulation layer 304 and the second encapsulation layer 305. It should be noted that before the motherboard is cut, the first substrates 101 in each chip structure 000 are connected to each other. Here, the structure obtained after the first substrates 101 in each chip structure 000 are connected together is the second substrate, and each of the light shielding layer 301, the first encapsulation layer 304 and the second encapsulation layer 305 in adjacent chip structures 000 can be connected together or not. Preferably, the remaining structures in adjacent chip structures 000 are not connected to each other to ensure easy separation after cutting. To this end, the embodiments of the present application will be described in the following three possible implementation methods:

[0143] In a first possible implementation, before the mother wafer is cut, only the first substrate 101 in each chip structure 000 is interconnected; the light shielding layer 301, first packaging layer 304, and second packaging layer 305 in each chip structure 000 are not connected. In this case, as shown in FIG12 , which is a partial enlarged view of the mother wafer at position B in FIG11 , before the mother wafer is cut, a first scribe line pattern L0 and a second scribe line pattern need to be formed during the preparation of the first large board M. Here, the first scribe line pattern L0 can be located between the light shielding layers 301 in two adjacent chip structures 000, and the second scribe line pattern can be located between the first packaging layer 304 and the second packaging layer 305 in two adjacent chip structures 000. That is, before cutting the motherboard wafer, the light-shielding layers 301 in each chip structure 000 can be separated and set by the first cutting line pattern L0, the first packaging layers 304 in each chip structure 000 can be separated and set by the second cutting line pattern, and the second packaging layers 305 in each chip structure 000 can also be separated and set by the second cutting line pattern.

[0144] The motherboard wafer is then cut according to the first scribe line pattern L0 and the second scribe line pattern L0. This allows only the second substrate to be cut during the motherboard wafer cutting process. This ensures that within each chip structure 000 obtained after cutting the motherboard wafer, a certain distance may exist between the outer contour of the light shielding layer 301 and the outer contour of the first substrate 100 in a direction parallel to the first substrate 100. For example, referring to FIG. 2 , the distance d0 between the outer contour of the light shielding layer 301 and the outer contour of the first substrate 100 in a direction parallel to the first substrate 100 may be less than or equal to 20 microns. This ensures that light leakage from the edge of the second semiconductor layer 200b is absorbed by the extension 3012 of the light shielding layer 301.

[0145] It should be noted that when a first scribe line pattern L0 is formed between the light shielding layer 301 within two adjacent chip structures 000 in the motherboard wafer, the operator can cut the second substrate in the motherboard according to the position of the first scribe line pattern L0. This simplifies the difficulty of cutting the second substrate in the motherboard wafer. Furthermore, it ensures that the outer contour of the light shielding layer 301 in each chip structure 000 after cutting is not burned, allowing the light shielding layer 301 to better perform its light shielding effect.

[0146] It should also be noted that the second cutting street pattern is similar to the first cutting street pattern in the light shielding layer 301. By providing the second cutting street, it is ensured that the first encapsulation layer 304 and the second encapsulation layer 305 are not cut during the cutting process of the motherboard wafer, thereby effectively preventing the microcracks in the first encapsulation layer 304 and the second encapsulation layer 305 from extending into the interior of the chip structure 000 when the first encapsulation layer 304 and the second encapsulation layer 305 are cut, thereby effectively improving the product stability of the chip structure 000.

[0147] In a second possible implementation, before the mother wafer is cut, the first substrates 101 in each chip structure 000 are interconnected, and the light shielding layers 301 in each chip structure 000 are also connected, but the first encapsulation layers 304 and second encapsulation layers 305 in each chip structure 000 are not connected. In this case, as shown in FIG13 , which is another partially enlarged view of the mother wafer at position B in FIG12 , before the mother wafer is cut, the first scribe line pattern L0 may not be formed during the preparation of the first large board M, but a second scribe line pattern may be formed. That is, before the mother wafer is cut, the first encapsulation layers 304 in each chip structure 000 may be separated by the second scribe line pattern, and the second encapsulation layers 305 in each chip structure 000 may also be separated by the second scribe line pattern.

[0148] In this way, during the dicing process of the mother wafer, the second substrate in the mother wafer can be diced. After the second substrate is diced to obtain multiple chip structures 000, the connected light shielding layers can be disconnected along the outer contours of the first substrate 100 in each chip structure 000. In this case, in each chip structure 000 obtained after dicing the mother wafer, the outer contour of the light shielding layer 301 is flush with the outer contour of the first substrate 100. In this way, light leakage emitted from the edge of the second semiconductor layer 200b is guaranteed to be absorbed by the extension portion 3012 in the light shielding layer 301.

[0149] In a third possible implementation, before the mother wafer is cut, the first substrates 101 in each chip structure 000 are interconnected, and the light shielding layer 301, first encapsulation layer 304, and second encapsulation layer 305 in each chip structure 000 are also connected. In this case, before the mother wafer is cut, the first scribe line pattern L0 and the second scribe line pattern may not be formed during the preparation of the first large board M. Thus, neither the first encapsulation layer nor the second encapsulation layer requires patterning. Furthermore, during the mother wafer cut, the second substrate in the mother wafer can be cut. After the second substrate is cut to obtain multiple chip structures 000, the connected light shielding layer, first encapsulation layer, and second encapsulation layer can be disconnected along the outer contours of the first substrate 100 in each chip structure 000. In this case, within each chip structure 000 obtained after the mother wafer is cut, the outer contours of the first substrate 100, the light shielding layer 301, the first encapsulation layer 304, and the second encapsulation layer 305 are all flush. In this way, the leaked light emitted from the edge of the second semiconductor layer 200 b can be absorbed by the extension portion 3012 in the light shielding layer 301 .

[0150] It should be noted that since the shape enclosed by the outer contour of the light shielding layer 301 and the shape enclosed by the first substrate 100 can both be rectangular, the distance between each side of the light shielding layer 301 and the adjacent side of the first substrate 100 in a direction parallel to the first substrate 100 must be less than or equal to 20 microns.

[0151] In the present application, the relationship between the outer contour of at least one of the first encapsulation layer 304 and the second encapsulation layer 305 in the color conversion unit 300 and the outer contour of the light shielding layer 301 satisfies any of the following conditions:

[0152] In the first case, the outer contour of at least one of the first encapsulation layer 304 and the second encapsulation layer 305 is flush with the outer contour of the light shielding layer 301. For example, the outer contour of the first encapsulation layer 304 can be flush with the outer contour of the light shielding layer 301, or the outer contour of the second encapsulation layer 305 can be flush with the outer contour of the light shielding layer 301, or the outer contours of the first encapsulation layer 304 and the second encapsulation layer 305 can be flush with the outer contour of the light shielding layer 301.

[0153] In the second case, there is a distance between the outer contour of at least one of the first encapsulation layer 304 and the second encapsulation layer 305 and the outer contour of the first substrate 100 .

[0154] For example, the outer contour of the first encapsulation layer 304 is closer to the outer contour of the first substrate 100 than the outer contour of the light shielding layer 301 .

[0155] For example, the outer contour of the second encapsulation layer 305 is closer to the outer contour of the first substrate 100 than the outer contour of the light shielding layer 301 .

[0156] For example, the outer contours of the first encapsulation layer 304 and the second encapsulation layer 305 are closer to the outer contour of the first substrate 100 than the outer contour of the light shielding layer 301 .

[0157] For example, the outer contour of the light shielding layer 301 is closer to the outer contour of the first substrate 100 than the outer contour of the first encapsulation layer 304 .

[0158] For example, the outer contour of the light shielding layer 301 is closer to the outer contour of the first substrate 100 than the outer contour of the second encapsulation layer 305 .

[0159] For example, the outer contour of the light shielding layer 301 is closer to the outer contour of the first substrate 100 than the outer contour of the first encapsulation layer 304 and is closer to the outer contour of the first substrate 100 than the outer contour of the second encapsulation layer 305 .

[0160] For example, the outer contour of the first encapsulation layer 304 is closer to the outer contour of the first substrate 100 than the outer contour of the second encapsulation layer 305 .

[0161] For example, the outer contour of the second encapsulation layer 305 is closer to the outer contour of the first substrate 100 than the outer contour of the first encapsulation layer 304 .

[0162] For example, the outer contour of the first encapsulation layer 304 and the outer contour of the first substrate 100 may be spaced apart.

[0163] The chip structure 000 may have a first side and a second side that are relatively arranged. Within the chip structure 000, in a direction parallel to the first substrate 100, the distance between the boundary contours of the outer contours of the first packaging layer 304 and the first substrate 100 adjacent to the first side is a third distance, and the distance between the boundary contours of the outer contours of the first packaging layer 304 and the first substrate 100 adjacent to the second side is a fourth distance.

[0164] Here, the sum of the third and fourth distances is substantially the same as the width of the second scribe line pattern shown in the above embodiment. Furthermore, since the width of the second scribe line pattern in subsequent embodiments needs to be greater than or equal to 5 microns, the sum of the third and fourth distances is also greater than or equal to 5 microns. Preferably, the sum of the third and fourth distances is greater than or equal to 10 microns.

[0165] It should be noted that when the motherboard chip is cut, whether a second cutting line pattern is formed in at least one of the first packaging layer 304 and the second packaging layer 305 in the motherboard chip, and whether a first cutting line pattern is formed in the light-shielding layer 301 will ultimately determine the relationship between the outer contour of the first packaging layer 304 and the outer contour of the light-shielding layer 301.

[0166] For example, if the second cutting line pattern is not formed in at least one of the first packaging layer 304 and the second packaging layer 305 in the motherboard chip, and the first cutting line pattern is not formed in the light shielding layer 301, then in the chip structure 000 obtained after cutting the motherboard chip, the outer contour of the first packaging layer 304 is flush with the outer contour of the light shielding layer 301, and both are flush with the outer contour of the first substrate 100.

[0167] If the second cutting line pattern is not formed in at least one of the first packaging layer 304 and the second packaging layer 305 in the motherboard chip, and the first cutting line pattern is formed in the light-shielding layer 301, then in the chip structure 000 obtained after cutting the motherboard chip, the outer contour of at least one of the first packaging layer 304 and the second packaging layer 305 is closer to the outer contour of the first substrate 100 relative to the outer contour of the light-shielding layer 301, and the outer contour of at least one of the first packaging layer 304 and the second packaging layer 305 is flush with the outer contour of the first substrate 100.

[0168] If a second scribe line pattern is formed in at least one of the first encapsulation layer 304 and the second encapsulation layer 305 in the motherboard wafer, and a first scribe line pattern is formed in the light shielding layer 301, then if the width of the second scribe line pattern is smaller than the first scribe line pattern, the outer contour of at least one of the first encapsulation layer 304 and the second encapsulation layer 305 is closer to the outer contour of the first substrate 100 relative to the outer contour of the light shielding layer 301. If the width of the second scribe line pattern is larger than the first scribe line pattern, the outer contour of the light shielding layer 301 is closer to the outer contour of the first substrate 100 relative to the outer contour of at least one of the first encapsulation layer 304 and the second encapsulation layer 305. If the width of the second scribe line pattern is equal to the first scribe line pattern, the outer contour of the light shielding layer 301 is flush with the outer contour of at least one of the first encapsulation layer 304 and the second encapsulation layer 305.

[0169] It should be noted that when a second cutting line is formed in both the first encapsulation layer 304 and the second encapsulation layer 305, and a first cutting line pattern is formed in the light shielding layer 301, in order to simplify the cutting process, it is necessary to cut as far as possible along the center line of the first cutting line pattern during the cutting of the motherboard wafer. During this process, in order to ensure that the first encapsulation layer 304 and the second encapsulation layer 305 are not cut, the width of the second cutting line pattern can be made greater than the width of the first cutting line pattern. In this way, during the cutting process according to the first cutting line pattern, the first encapsulation layer 304 and the second encapsulation layer 305 will definitely not be cut, so that no microcracks will be generated in the first encapsulation layer 304 and the second encapsulation layer 305. Therefore, the drawings in the embodiments of the present application are all illustrated by taking the outer contour of the light shielding layer 301 as an example, which is closer to the outer contour of the first substrate 100 than the outer contours of the first encapsulation layer 304 and the second encapsulation layer 305.

[0170] In this case, for the individual chip structures 000 obtained after cutting the second substrate in the motherboard wafer, please refer to FIG14 . FIG14 is a top view of another chip structure provided in an embodiment of the present application. This chip structure 000 may have a first side and a second side that are arranged opposite to each other. Within this chip structure 000, in a direction parallel to the first substrate 100, the distance between the light shielding layer 301 and the boundary contour of the outer contour of the first substrate 100 adjacent to the first side is a first distance d1, and the distance between the light shielding layer 301 and the boundary contour of the outer contour of the first substrate 100 adjacent to the second side is a second distance d2. It should be noted that FIG14 is a schematic illustration using the example of the first side being the left side of the chip structure 000 and the second side being the right side of the chip structure 000.

[0171] Here, the sum of the first distance d1 and the second distance d2 is substantially the same as the width of the first scribe line pattern L0 shown in FIG12 . Furthermore, since the width of the first scribe line pattern L0 shown in FIG12 needs to be greater than or equal to 5 microns, the sum of the first distance d1 and the second distance d2 is also greater than or equal to 5 microns. Preferably, the sum of the first distance d1 and the second distance d2 is greater than or equal to 10 microns.

[0172] In an embodiment of the present application, the second substrate in the motherboard wafer can be cut by laser hidden cutting. Here, during the cutting process, the laser cutting beam can be focused to the middle position of the second substrate in the thickness direction of the second substrate, so that the middle position of the second substrate can be melted or vaporized. After that, a tool can be used to apply force to the upper surface and / or lower surface of the second substrate, so that the portion of the second substrate belonging to the first substrate 100 in the single chip structure 000 can be separated. It should be noted that in this process, because the laser cutting beam reaches the middle position of the second substrate, no extra debris (for example, cutting sparks) will be generated during the cutting process and splashed onto the light-emitting unit 200 or the color conversion unit 300, so that the chip structure 000 obtained by subsequent cutting has higher reliability.

[0173] In this case, after the motherboard wafer second substrate is cut, the outer side surface of the first substrate 100 in the resulting chip structure 000 is a fracture surface. Here, please refer to Figure 15, which is a schematic diagram of the outer side surface of a first substrate provided in an embodiment of the present application. This fracture surface may include: a first fracture portion S1 and a second fracture portion S2, and a laser-cut portion S3 located between the first fracture portion S1 and the second fracture portion S2. The first fracture portion S1 and the second fracture portion S2 may show signs of stress fracture, and the laser-cut portion S3 may show signs of laser cutting ablation.

[0174] In the present application, since the laser cutting beam is focused on the middle position of the second substrate during the cutting process, a laser cutting ablation mark will appear at the middle position of the outer side surface of the first substrate 101 in the single chip structure 000 obtained after the second substrate is cut. Furthermore, since during the cutting process of the second substrate, after the laser cutting beam melts or vaporizes the middle position of the second substrate, a cutting blade is required to apply force to the upper and / or lower surfaces of the second substrate to achieve the cutting of the second substrate. Therefore, on the outer side surface of the first substrate 101 in the single chip structure 000 obtained after the second substrate is cut, stress fracture marks will appear on both sides of the ablation mark.

[0175] It should be noted that, for the first substrate 100 in the single chip structure 000 obtained by cutting, since the middle position of the outer side surface of the first substrate 100 will show ablation marks of laser cutting, the outer side surface of the first substrate 100 on both sides of the middle position will show fracture marks. Therefore, the outer side surface of the first substrate 100 is not a complete plane. For this reason, the distance between the outer contour of the first substrate 100 and the outer contour of other film layers (for example, the light-shielding layer 301) is not a fixed value. For this reason, the distance between the outer contour of the first substrate 100 and the outer contour of other film layers may be referred to in this application as: the average distance between the outer contour of the first substrate 100 and the outer contour of other film layers.

[0176] In an embodiment of the present application, as shown in Figures 16, 17 and 18, Figure 16 is a top view of another chip structure provided in an embodiment of the present application, Figure 17 is a schematic diagram of the film layer structure of the chip structure shown in Figure 16 at C-C', and Figure 18 is a schematic diagram of the film layer structure of the chip structure shown in Figure 16 at D-D'. The multiple sub-light-emitting functional layers in the light-emitting unit 200 may include: a first sub-light-emitting functional layer 200a1, a second sub-light-emitting functional layer 200a2 and a third sub-light-emitting functional layer 200a3. Here, the first sub-light-emitting functional layer 200a1, the second sub-light-emitting functional layer 200a2 and the third sub-light-emitting functional layer 200a3 are all used to emit a first light in a working state.

[0177] Accordingly, the plurality of opening regions defined in the dam layer 302 may include a first opening region K21, a second opening region K22, and a third opening region K23. The first opening region K21 may be disposed opposite the first sub-light-emitting functional layer 200a1, the second opening region K22 may be disposed opposite the second sub-light-emitting functional layer 200a2, and the third opening region K23 may be disposed opposite the third sub-light-emitting functional layer 200a3.

[0178] The optical functional layer 303 in the color conversion unit 300 may include a first color conversion portion 303a, a second color conversion portion 303b, and a third color conversion portion 303c. The first color conversion portion 303a may be located within the first opening area K21, the second color conversion portion 303b may be located within the second opening area K22, and the third color conversion portion 303c may be located within the third opening area K23.

[0179] In this case, the first light emitted by the first sub-light-emitting functional layer 200a1 can be directed toward the first color conversion region 303a, where it is converted into light of another color by the first color conversion region 303a. The first light emitted by the second sub-light-emitting functional layer 200a1 can be directed toward the second color conversion region 303b, where it is converted into light of another color by the second color conversion region 303b. The first light emitted by the third sub-light-emitting functional layer 200a3 can be directed toward the third color conversion region 303c, where it can transmit through or be converted by the third color conversion region 303c.

[0180] For example, the chip structure 000 may have a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The first light emitted by the first sub-light emitting functional layer 200a1, the second sub-light emitting functional layer 200a2, and the third sub-light emitting functional layer 200a3 in the light emitting unit 200 includes at least one of blue light and ultraviolet light.

[0181] Here, the first color conversion unit 303a is used to convert the first light into red light. For example, the first color conversion unit 303a includes red quantum dots that convert the first light into red light. Preferably, the first color conversion unit 303a also includes scattering particles for scattering the light. Here, after the first light emitted by the first sub-light-emitting functional layer 200a1 strikes the first color conversion unit 303a distributed within the first opening area K21, it is converted into red light by the red quantum dots. The scattering particles scatter the first light and red light, ensuring that more of the first light is converted into red light by the red quantum dots. This also ensures that the output angle of the converted red light is wide, thereby ensuring a wide viewing angle for a display panel incorporating this chip structure 000. To this end, the red sub-pixel R in the chip structure 000 may include: the first sub-light-emitting functional layer 200a2 and the first color conversion unit 303a.

[0182] The second color conversion portion 303b is used to convert the first light into green light. For example, the second color conversion portion 303b includes green quantum dots that convert the first light into green light. Preferably, the second color conversion portion 303b also includes scattering particles for scattering light. Here, after the first light emitted from the second sub-light-emitting functional layer 200a2 reaches the second color conversion portion 303b distributed within the second opening area K22, it is converted into green light by the green quantum dots. The scattering particles scatter the first and green light, ensuring that more of the first light is converted into green light by the green quantum dots. This also ensures that the emitted green light has a wide emission angle, thereby ensuring a wide viewing angle for a display panel incorporating this chip structure 000. To this end, the red sub-pixel R in the chip structure 000 may include: the first sub-light-emitting functional layer 200a1 and the first color conversion portion 303a. To this end, the green sub-pixel G in the chip structure 000 may include: the second sub-light-emitting functional layer 200a2 and the second color conversion portion 303b.

[0183] The third color conversion portion 303c is used to convert the first light into blue light or maintain blue light emission. For example, when the first light only contains blue light, the third color conversion portion 303c can be a transparent portion or can include blue quantum dots; the transparent portion is used to directly transmit the first light, and the blue quantum dots are used to convert the first light into blue light of a different wavelength than the first light. Preferably, the third color conversion portion 303c also includes scattering particles that scatter light. Here, after the first light emitted from the third sub-light-emitting functional layer 200a3 reaches the third color conversion portion 303c distributed within the third opening area K23, the scattering particles can scatter the first light, ensuring a larger emission angle of the blue light, thereby ensuring a wider viewing angle for the display panel integrated with this chip structure 000. For another example, when the first light contains ultraviolet light, the third color conversion region 303c includes blue quantum dots that convert the first light into blue light, or the third color conversion region 303c includes both scattering particles for scattering light and blue quantum dots for converting ultraviolet light into blue light. Here, after the first light emitted by the second sub-light-emitting functional layer 200a2 strikes the third color conversion region 303c distributed within the third opening region K23, the blue quantum dots convert the ultraviolet light in the first light into blue light. The scattering particles scatter the first light and the blue light, ensuring that more ultraviolet light is converted into blue light by the blue quantum dots. This also ensures that the output angle of the converted blue light is larger, thereby ensuring a wider viewing angle for a display panel incorporating this chip structure 000. To this end, the blue sub-pixel B in the chip structure 000 may include the third sub-light-emitting functional layer 200a3 and the third color conversion region 303c.

[0184] In the embodiment of the present application, the color conversion unit 300 in the chip structure 000 may further include a filter layer 306 located between the first substrate 100 and the optical functional layer 200. The filter layer 306 may include a plurality of filter units corresponding one-to-one to the plurality of light passage holes K1, and the orthographic projection of each filter unit on the first substrate 100 may overlap with the orthographic projection of the corresponding light passage hole on the first substrate 100.

[0185] For example, the multiple filter units in the filter layer 306 may include a first filter unit 306a, a second filter unit 306b, and a third filter unit 306c. Here, the first filter unit 306a may be provided corresponding to the first color conversion unit 303a, the second filter unit 306b may be provided corresponding to the second color conversion unit 303b, and the third filter unit 306c may be provided corresponding to the third color conversion unit 303c. To this end, the red sub-pixel R in the chip structure 000 may further include the first filter unit 306a; the green sub-pixel G in the chip structure 000 may further include the second filter unit 306b; and the blue sub-pixel B in the chip structure 000 may further include the third filter unit 306c.

[0186] For example, the first light emitted by the first sub-light-emitting functional layer 200a1, the second sub-light-emitting functional layer 200a2, and the third sub-light-emitting functional layer 200a3 in the light-emitting unit 200 is all blue light. The first filter unit 306a can be a red color block that transmits red light and absorbs light of other colors. In this way, the light emitted from the first color conversion unit 303a can pass through the first filter unit 306a before being emitted. The first filter unit 306a can filter out light of other colors except red light, ensuring that the red sub-pixel R in the chip structure 000 can filter out the blue light component. It should be noted that, in other possible implementations, the first filter unit 306a may also be a film layer for transmitting red light and reflecting blue light. In this way, after the light emitted from the first color conversion portion 303a hits the first filter unit 306a, the red light in this light can pass through the first filter unit 306a before being emitted, while the blue light in this light can be reflected back to the first color conversion portion 303a by the first filter unit 306a. The red quantum dots in the first color conversion portion 303a can then excite the blue light into red light, thereby further improving the excitation efficiency of the red quantum dots.

[0187] For example, the first light emitted by the first sub-light-emitting functional layer 200a1, the second sub-light-emitting functional layer 200a2, and the third sub-light-emitting functional layer 200a3 in the light-emitting unit 200 is all blue light. The second filter unit 306b can be a green color block that transmits green light and absorbs light of other colors. In this way, the light emitted from the second color conversion unit 303b can pass through the second filter unit 306b before being emitted. The second filter unit 306b can filter out light of other colors except green light, ensuring that the green sub-pixel G in the chip structure 000 can filter out blue light components. It should be noted that, in other possible implementations, the second filter unit 306b may also be a film layer for transmitting green light and reflecting blue light. In this way, after the light emitted from the second color conversion unit 303b hits the second filter unit 306b, the green light in this light can pass through the second filter unit 306b before being emitted, while the blue light in this light can be reflected back to the second color conversion unit 303b by the second filter unit 306b. The green quantum dots in the second color conversion unit 303b can then excite the blue light into green light, thereby further improving the excitation efficiency of the green quantum dots.

[0188] It should be noted that the film structures of the first filter unit 306a and the second filter unit 306b can be the same and can be manufactured through the same process; for example, the first filter unit 306a and the second filter unit 306b are both films that transmit red and green light and reflect blue light.

[0189] For example, the first light emitted by the first sub-light-emitting functional layer 200a1, the second sub-light-emitting functional layer 200a2, and the third sub-light-emitting functional layer 200a3 in the light-emitting unit 200 is all blue light. The third filter unit 306c can be a blue color block that transmits blue light and absorbs light of other colors. In this way, the light emitted from the third color conversion unit 303c can pass through the third filter unit 306c before being emitted. The third filter unit 306c can filter out light of other colors except blue light, thereby ensuring that the blue sub-pixel B in the chip structure 000 can emit relatively pure blue light.

[0190] For example, the first light emitted by the first sub-light-emitting functional layer 200a1, the second sub-light-emitting functional layer 200a2 and the third sub-light-emitting functional layer 200a3 in the light-emitting unit 200 is blue light, and the third filter unit 306c can be a transparent block that can transmit blue light.

[0191] It should be noted that, because the orthographic projections of the respective filter units in the filter layer 306 on the first substrate 100 overlap with the orthographic projections of the corresponding light holes K1 in the light shielding layer 301 on the first substrate 100, portions of the light shielding layer 301 are distributed between two adjacent filter units in the filter layer 306 in a direction parallel to the first substrate 100. In this way, light emitted from the side of a filter unit in the filter layer 306 can be absorbed by the light shielding layer 301, thereby ensuring that light emitted from each sub-pixel does not strike adjacent sub-pixels, effectively reducing the probability of color crosstalk in the chip structure 000.

[0192] In the embodiment of the present application, there are various structures of the first encapsulation layer 304 in the color conversion unit 300. The embodiment of the present application will be schematically described using the following two implementations as examples:

[0193] In the first implementation, as shown in FIG19 , which is a schematic diagram of the film layer structure of a chip structure provided in another embodiment of the present application, the first encapsulation layer 304 in the color conversion unit 300 is a film layer structure provided as a whole layer on the first substrate 100. That is, the first encapsulation layer 304 located on the first substrate 100 is not patterned. In this case, the orthographic projections of the optical functional layer 303 and the limiting dam layer 302 in the color conversion unit 300 on the first substrate 100 can both be located at the orthographic projection of the first encapsulation layer 304 on the substrate 100. In this way, the first encapsulation layer 304 can cover the side of the optical functional layer 303 facing the first substrate 100, and cover the side of the limiting dam layer 302 facing the first substrate 100, so that after the water and oxygen in the external environment invade the light-shielding layer 301, the water and oxygen invading the light-shielding layer 301 can be isolated by the first encapsulation layer 304, and thus the water and oxygen invading the light-shielding layer 301 will not invade the limiting dam layer 302 from the side of the limiting dam layer 302 facing the first substrate 100, nor will it invade the optical functional layer 303 from the side of the optical functional layer 303 facing the first substrate 100.

[0194] Here, the first encapsulation layer 304 in the color conversion unit 300 is located between the light shielding layer 301 and the definition dam layer 303. The positional relationship between the first encapsulation layer 304 and the filter layer 306 in the color conversion unit 300 can be varied. The present application uses the following two cases as examples for schematic illustration:

[0195] In the first case, as shown in FIG19 , the filter layer 306 in the color conversion unit 300 can be located on the side of the first encapsulation layer 304 facing away from the first substrate 100, and a portion of the first encapsulation layer 304 can be located within the light-through hole K1 in the light-shielding layer 301. Here, the side of the filter layer 306 facing away from the first substrate 100 can be in direct contact with the side of the optical functional layer 303 facing the first substrate 100.

[0196] Optionally, the orthographic projections of the respective filter units in the filter layer 306 on the first substrate 100 may overlap the orthographic projections of the corresponding openings K2 in the limiting dam layer 302 on the first substrate 100. In this way, all light emitted from the optical functional layer 303 distributed within the openings K2 of the limiting dam layer 302 may be directed toward the corresponding filter units in the filter layer 306, thereby ensuring that the filter units have a better light filtering effect, resulting in a purer color of the light subsequently emitted from the corresponding light holes K1 in the light shielding layer 301.

[0197] In the second case, as shown in FIG20 , which is a schematic diagram of the film layer structure of another chip structure provided in another embodiment of the present application, the filter layer 306 in the color conversion unit 300 can be located on the side of the first encapsulation layer 304 facing the first substrate 100, and at least a portion of each filter unit in the filter layer 306 can be located within the corresponding light hole K1 in the light shielding layer 301. Here, the side of the first encapsulation layer 304 in the color conversion unit 300 facing the first substrate 100 can directly contact the side of the light shielding layer 301 facing away from the first substrate 100, and directly contact the side of the filter layer 306 facing away from the first substrate 100; the side of the first encapsulation layer 304 in the color conversion unit 300 facing away from the first substrate 100 can directly contact the side of the dam layer 302 facing the first substrate 100, and directly contact the side of the optical functional layer 303 facing the first substrate 100.

[0198] Optionally, the orthographic projections of the respective filter units in the filter layer 306 on the first substrate 100 may cover the orthographic projections of the corresponding light holes K1 in the light shielding layer 301 on the first substrate 100. Here, within the filter layer 306, a portion of each filter unit may be distributed within the corresponding light hole K1 in the light shielding layer 301, and another portion may be distributed outside the corresponding light hole K1. In this way, light emitted from the optical functional layer 303 distributed within the opening area K2 of the limiting dam layer 302, after emitting to the corresponding light hole K1 in the light shielding layer 301, may all be filtered by the corresponding filter units in the filter layer 306. This ensures that the filter units have a better filtering effect on light, making the color of the light emitted from the corresponding light hole K1 in the light shielding layer 301 purer.

[0199] A second implementation is shown in FIG21, which is a schematic diagram of the film structure of another chip structure provided by another embodiment of the present application. The film structure of the first encapsulation layer 304 in the color conversion unit 300 after patterning on the first substrate 100, that is, the first encapsulation layer 304 located on the first substrate 100 needs to be patterned. In this case, the first encapsulation layer 304 can have multiple auxiliary openings K3 that correspond one-to-one with the multiple light-through holes K1 in the light-shielding layer 301. The orthographic projection of each auxiliary opening K3 in the first encapsulation layer 304 on the first substrate 100 can overlap with the orthographic projection of the corresponding light-through hole K1 in the light-shielding layer 301 on the first substrate 100.

[0200] Here, at least a portion of each filter unit in the filter layer 306 can be located within the corresponding auxiliary opening K3 in the first encapsulation layer 304 and can be located within the corresponding light-through hole K1 in the light-shielding layer 301. Two opposing surfaces of each filter unit in the filter layer 306 can contact the first substrate 100 and the optically functional layer 303. For example, the portion of each filter unit in the filter layer 306 located within the corresponding light-through hole K1 facing the first substrate 100 can directly contact the first substrate 100; the side of each filter unit in the filter layer 306 facing away from the substrate 100 can directly contact the side of the optically functional layer 304 located within the corresponding opening area K2 in the definition dam layer 303 facing the first substrate 100.

[0201] In this case, because multiple auxiliary openings K3 are provided in the first encapsulation layer 304, and two opposing surfaces of each filter unit in the filter layer 306 are in direct contact with the first substrate 100 and the optical function layer 303, light emitted from the optical function layer 303 distributed within the opening area K2 of the limiting dam layer 302 can directly be emitted toward the corresponding filter unit in the filter layer 306, and light emitted from the filter unit can directly pass through the first substrate 100 before being emitted. Therefore, light emitted from the optical function layer 303 does not pass through the first encapsulation layer 304, thus preventing light emitted toward the first encapsulation layer 304 from generating optical waveguides within the first encapsulation layer 304. This ensures that light emitted from the optical function layer 303 distributed within a certain opening area K2 does not propagate to the sub-pixel where the adjacent opening area K2 is located, further reducing the probability of color crosstalk in the chip structure 000.

[0202] Optionally, the orthographic projections of the respective filter units in the filter layer 306 on the first substrate 100 may cover the orthographic projections of the corresponding opening areas K2 in the limiting dam layer 302 on the first substrate 100, thereby ensuring that the color of the light emitted from the optical functional layer 303 is purer after passing through the first substrate 100.

[0203] In one optional implementation, when the first encapsulation layer 304 in the color conversion unit 300 is patterned on the first substrate 100, the orthographic projection of each auxiliary opening K3 in the first encapsulation layer 304 on the first substrate 100 can be located within the orthographic projection of the corresponding light-through hole K1 in the light-shielding layer 301 on the first substrate 100. Furthermore, a portion of the first encapsulation layer 304 can extend into the light-through hole K1 in the light-shielding layer 301, and the portion of the first encapsulation layer 304 extending into the light-through hole K1 can cover the inner wall of the light-through hole K1. This ensures that the filter unit is spaced apart from the light-shielding layer 301. The portion of the first encapsulation layer 304 extending into the light-through hole K1 can isolate water and oxygen from intruding into the light-shielding layer 301 in a direction parallel to the first substrate 100. In this way, even if the two opposite surfaces of each filter unit in the filter layer 306 are in direct contact with the first substrate 100 and the optical function layer 303, it can be ensured that water and oxygen that penetrate into the light shielding layer 301 will not corrode the optical function layer 303 through the filter layer 306.

[0204] In an embodiment of the present application, please refer to FIG22 , which is a top view of a chip structure provided in another embodiment of the present application. The light shielding layer 301 in the color conversion unit 300 within the chip structure 000 may include at least one annular through-groove U. The orthographic projections of the multiple light holes K1 in the light shielding layer 301 on the first substrate 100 are all located within the area enclosed by the orthographic projections of the annular through-groove U on the first substrate 100. To this end, the orthographic projections of the multiple filter units in the filter layer 306 within the color conversion unit 300 on the first substrate 100 may also be located within the area enclosed by the orthographic projections of the annular through-groove U on the first substrate 100. A portion of the first encapsulation layer 304 in the color conversion unit 300 may be located within the annular through-groove U. Specifically, the first encapsulation layer 304 located within the area enclosed by the annular through-groove U contacts the first substrate 100. In this case, the portion of the first packaging layer 304 distributed in the annular groove U is a blocking dam, which can block water and oxygen invading from the edge of the light-shielding layer 301 in a direction parallel to the first substrate 100, thereby ensuring that water and oxygen will not invade the internal area of ​​the light-shielding layer 301, thereby further reducing the probability of water and oxygen in the external environment corroding the optical functional layer 303.

[0205] In addition, by allowing part of the first packaging layer 304 to be located within the annular groove U, it can also be ensured that during the process of cutting to obtain the chip structure 000, microcracks generated in the first substrate 100 or the first packaging layer 304 are blocked by the blocking dam located within the annular groove U, so that the microcracks will not spread to the internal area of ​​the light-shielding layer 301, thereby improving the product yield of the chip structure 000 obtained after the cutting process.

[0206] It should be noted that since the above embodiments are all described based on the example of the light shielding layer 301 in the film structure of the color conversion unit 300 not including the annular through groove U, and there are various ways of structure and distribution of the first encapsulation layer 304 in the color conversion unit 300, the embodiments of this application will schematically illustrate the film structure of the color conversion unit 300 in which the light shielding layer 301 with the annular through groove U is located using the following three exemplary implementations:

[0207] For the first exemplary implementation, please refer to FIG. 23 , which is a schematic diagram of the film layer structure at the E-E′ position of the chip structure shown in FIG. 22 . When the first packaging layer 304 in the color conversion unit 300 is a film layer structure provided as a whole layer on the first substrate 100, and the filter layer 306 in the color conversion unit 300 is located on the side of the first packaging layer 304 facing away from the first substrate 100, a portion of the first packaging layer 304 can simultaneously extend into the annular groove U and the light hole K1 of the light shielding layer 301.

[0208] For a second exemplary implementation, please refer to FIG. 24 , which is a schematic diagram of another film layer structure at the E-E′ position of the chip structure shown in FIG. 22 . When the first packaging layer 304 in the color conversion unit 300 is a film layer structure provided as a whole layer on the first substrate 100, and the filter layer 306 in the color conversion unit 300 is located on the side of the first packaging layer 304 facing the first substrate 100, a portion of the first packaging layer 304 can extend into the annular groove U of the light-shielding layer 301, and each filter unit in the filter layer 306 can extend into the corresponding light hole K1 in the light-shielding layer 301.

[0209] Referring to FIG. 25 , a third exemplary implementation is shown, which is a schematic diagram of another film layer structure at the EE′ line of the chip structure shown in FIG. 22 . When the first encapsulation layer 304 in the color conversion unit 300 has a plurality of auxiliary openings K3 corresponding one-to-one with the plurality of light holes K1 in the light shielding layer 301, each filter unit in the filter layer 306 can extend into the corresponding light hole K1 in the light shielding layer 301. In this case, to ensure that the color of light emitted from the light hole K1 in the light shielding layer 301 is purer, the orthographic projection of the light hole K1 on the first substrate 100 must overlap the orthographic projection of the corresponding auxiliary opening K3 on the first substrate 100, thereby ensuring that the orthographic projection of each filter unit in the filter layer 306 on the first substrate 100 covers the orthographic projection of the corresponding light hole K1 in the light shielding layer 301 on the first substrate 100. That is, a portion of each filter unit in the filter layer 306 can extend into the corresponding light hole K1 in the light shielding layer 301, while another portion can be located outside the corresponding light hole K1. In this way, it can be ensured that light emitted from the optical functional layer 303 distributed within the opening area K2 of the limiting dam layer 302 can be completely filtered by the corresponding filter unit in the filter layer 306 after it reaches the corresponding light hole K1 in the light shielding layer 301.

[0210] In the embodiment of the present application, the orthographic projection of the annular through-groove U on the first substrate 100 may be located within the orthographic projection of the dam layer 302 on the first substrate 100. Preferably, the orthographic projection of the annular through-groove U on the first substrate 100 may be located within the orthographic projection of the side of the dam layer 302 facing the first substrate 100 on the first substrate 100.

[0211] In this case, the boundary between the orthographic projection of the main portion 3011 of the light-shielding layer 301 and the orthographic projection of the extension portion 3012 of the light-shielding layer 301 on the first substrate 100 defines the outer contour of the orthographic projection of the dam layer 302 on the first substrate 100. Therefore, when the orthographic projection of the annular groove U on the first substrate 100 lies within the orthographic projection of the dam layer 302 on the first substrate 100, it is ensured that the annular groove U is only located within the main portion 3011 of the light-shielding layer 301 and not within the extension portion 3012 of the light-shielding layer 301. This ensures that, while the annular groove U can be properly disposed within the light-shielding layer 301, light emitted from the edge of the second semiconductor layer, after generating an optical waveguide phenomenon within the second semiconductor layer, can still be properly absorbed by the extension portion 3012 of the light-shielding layer 301.

[0212] Optionally, as shown in Figures 22 to 25 , when the light shielding layer 301 in the color conversion unit 300 has multiple annular through-grooves U, the multiple annular through-grooves U can be nested in sequence. It should be noted that the present embodiment is schematically illustrated using an example in which two annular through-grooves U are distributed in the light shielding layer 301.

[0213] For example, assuming that the two annular grooves U are respectively annular groove U1 and annular groove U2, and the area enclosed by annular groove U1 is larger than the area enclosed by annular groove U2, then the orthographic projection of the filter layer 306 in the color conversion unit 300 on the first substrate 100 can be located within the area enclosed by the orthographic projection of the annular groove U2 on the first substrate 100, and the orthographic projection of the annular groove U2 on the first substrate 100 can be located within the area enclosed by the orthographic projection of the annular groove U1 on the first substrate 100.

[0214] In this case, when the light shielding layer 300 includes a plurality of nested annular grooves U, since portions of the first encapsulation layer 304 can extend into each of the annular grooves U, and the portions of the first encapsulation layer 304 extending into the annular grooves U can serve as barrier dams, a plurality of sequentially nested barrier dams are provided at the edge of the light shielding layer 300. These sequentially nested barrier dams can further block water and oxygen from invading from the edge of the light shielding layer 301 in a direction parallel to the first substrate 100.

[0215] In an embodiment of the present application, when the light-shielding layer 300 includes a plurality of nested annular grooves U, the width of each annular groove U can be in the range of 3 microns to 5 microns, the distance between two adjacent annular grooves U (for example, annular groove U1 and annular groove U2) is in the range of 3 microns to 5 microns, and the distance between the annular groove closest to the outer contour of the first substrate 100 among the plurality of annular grooves U (for example, annular groove U1) and the outer contour of the first substrate 100 is in the range of 5 microns to 15 microns.

[0216] In the embodiment of the present application, as shown in Figures 19 to 25 , since the second encapsulation layer 305 in the color conversion unit 300 can be located on the side of the dam layer 302 and the optical functional layer 303 facing away from the first substrate 100, and the color conversion unit 300 in the chip structure 000 is distributed between the first substrate 100 and the light-emitting unit 200, the light-emitting unit 200 in the chip structure 000 can be located on the side of the second encapsulation layer 305 facing away from the first substrate 100.

[0217] In the embodiments of the present application, please refer to Figures 26 and 27. Figure 26 is a top view of a light-emitting unit located on a connection layer provided in an embodiment of the present application, and Figure 27 is a schematic diagram of the film layer structure of the light-emitting unit shown in Figure 26 at the F-F' position. Each sub-light-emitting functional layer 200a in the light-emitting unit 200 may include: a first electrode 201, a first semiconductor layer 202, and a light-emitting layer 203 stacked in a direction perpendicular to and toward the first substrate 100.

[0218] Here, since the second semiconductor layer 200b in the light-emitting unit 200 is located on the light-emitting side of each sub-light-emitting functional layer 200a, and the second semiconductor layer 200b is closer to the first substrate 100 than each sub-light-emitting functional layer 200a, the second semiconductor layer 200b can contact the side of the light-emitting layer 203 in each sub-light-emitting functional layer 200a that is away from the first semiconductor layer 202.

[0219] In an embodiment of the present application, please refer to Figures 28 and 29. Figure 28 is a top view of another light-emitting unit located on a connecting layer provided in an embodiment of the present application, and Figure 29 is a schematic diagram of the film layer structure of the light-emitting unit shown in Figure 28 at the G-G' position. The second semiconductor layer 200b may include: a connecting portion 200b1 and an auxiliary portion 200b2 arranged in a direction parallel to the first substrate 100. There are multiple connecting portions 200b1 in the second semiconductor layer 200b, and the multiple connecting portions 200b1 can correspond one-to-one to multiple sub-light-emitting functional layers 200a. Each connecting portion 200b1 can be connected to the corresponding sub-light-emitting functional layer 200a. For example, each connecting portion 200b1 can be connected to the side of the light-emitting layer 203 in the corresponding sub-light-emitting functional layer 200a that is away from the first semiconductor layer 202. The auxiliary portion 200b2 in the second semiconductor layer 200b can connect multiple connecting portions 200b1.

[0220] It should be noted that the second semiconductor layer 200b, except for the portions between the multiple connecting portions 200b1, can all be auxiliary portions 200b2. For example, the auxiliary portion 200b2 includes a first auxiliary portion 200b21 and a second auxiliary portion 200b22, wherein the first auxiliary portion 200b21 is located between adjacent connecting portions 200b1, and the second auxiliary portion 200b22 is disposed entirely around the first auxiliary portion 200b21 and the connecting portions 200b1. Specifically, the connecting portions 200b1 and the auxiliary portion 200b2 are made of the same material and are an integral structure. In the above embodiment, the light emitted by each sub-light-emitting functional layer 200a is directed toward the second semiconductor layer 200b, easily generating an optical waveguide within the second semiconductor layer and emitting at the edge of the second semiconductor layer 200b. The light emitted from the edge of the second semiconductor layer 200b can be absorbed by the extension portion 3012 in the light-shielding side 301, thereby reducing or avoiding light leakage in the chip structure 000.

[0221] In the present application, the light emitting unit 200 may further include a common electrode layer 200c, wherein the common electrode layer 200c may be connected to the auxiliary portion 200b2 in the second semiconductor layer 200b.

[0222] Optionally, in the light-emitting unit 200, the material of the first semiconductor layer 202 in each sub-light-emitting functional layer 200a may include: P-type doped gallium nitride; the light-emitting layer 203 in each sub-light-emitting functional layer 200a may be a multi-quantum well layer. The second semiconductor layer 200b may include: a first sublayer 200b3 and a second sublayer 200b4 stacked in a direction perpendicular to and toward the first substrate 100. That is, the first sublayer 200b3 is closer to the sub-light-emitting functional layer 200a than the second sublayer 200b4. In other words, the first sublayer 200b3 may be located between the second sublayer 200b3 and the light-emitting layer 203 in the sub-light-emitting functional layer 200a. Here, the material of the first sublayer 200b1 in the second semiconductor layer 200b may be N-type doped gallium nitride, and the second sublayer 200bb in the second semiconductor layer 200b may be a gallium nitride buffer layer.

[0223] In this case, in the light-emitting unit 200, after the common electrode layer 200c is loaded with a cathode signal, if the first electrode 201 in a sub-light-emitting functional layer 200a is loaded with an anode signal, the light-emitting layer 203 in the sub-light-emitting functional layer 200a can emit the first light.

[0224] In the embodiment of the present application, each sub-light-emitting functional layer 200a in the light-emitting unit 200 may further include a current spreading layer 204 located between the first electrode 201 and the first semiconductor layer 202. Here, one side of the current spreading layer 204 in each sub-light-emitting functional layer 200a may be in contact with the first semiconductor layer 202, and the other side may be electrically connected to the first electrode 201. Optionally, the current spreading layer 204 may be made of ITO (indium tin oxide). Providing the current spreading layer 204 in the sub-light-emitting functional layer 200a facilitates hole transport and improves the electrical performance of the chip structure 000.

[0225] In the present application, the common electrode layer 200c in the light-emitting unit 200 may include: a first common electrode layer 200c01 disposed in contact with the second semiconductor 200b, and a second common electrode layer 200c02 electrically connected to a side of the first common electrode layer 200c01 facing away from the second semiconductor 200b. Here, the second common electrode layer 200c02 may be disposed in the same layer and made of the same material as the first electrode 201 in each sub-light-emitting functional layer 200a, that is, the second common electrode layer 200c02 and each first electrode 201 are formed using the same patterning process.

[0226] In an embodiment of the present application, the light-emitting unit 200 may further include: an insulating protective layer 206 located on the side of the first common electrode layer 200c01 and each sub-light-emitting functional layer 200a away from the second semiconductor layer 200b. Here, the insulating protective layer 206 may have a plurality of first connection holes V1 arranged in a one-to-one correspondence with the plurality of sub-light-emitting functional layers 200a, and a second connection hole V2 arranged in a corresponding manner with the first common electrode layer 200c01. The plurality of first connection holes V1 may also correspond one-to-one with the plurality of first electrodes 201, and each first electrode 201 may be electrically connected to the current spreading layer 204 in the corresponding sub-light-emitting functional layer 200a through the corresponding first connection hole V1. The second connection hole V2 may correspond to the second common electrode layer 200c02, and the second common electrode layer 200c02 may be electrically connected to the first common electrode layer 200c01 and the common electrode layer 200c through the second connection hole V2. It should be noted that, for ease of viewing, the insulating protective layer 206 is shown in the light-emitting unit shown in FIG. 26 , but the insulating protective layer 206 is not shown in the light-emitting unit shown in FIG. 28 .

[0227] For example, the first common electrode layer 200c01 may function as a current spreader.

[0228] For example, the materials of the first common electrode layer 200c01 and the second common electrode layer 200c02 are both metal.

[0229] Optionally, the thickness of the first common electrode layer 200c01 can be significantly greater than the thickness of the current spreading layer 204. For example, the thickness of the first common electrode layer 200c01 can be equal to the thickness of the sub-light-emitting functional layer 200a. That is, the side of the first common electrode layer 200c01 facing away from the second semiconductor layer 200b can be flush with the side of the current spreading layer 204 facing away from the second semiconductor layer 200b. In this way, the sides of the first electrode 201 and the second common electrode layer 200c02 in the light-emitting unit 200 facing away from the connection layer 400 are also flush. Because the first electrode 201 and the second common electrode layer 200c02 in the chip structure 000 will need to be soldered to the driver backplane when the chip structure 000 is subsequently connected to the driver backplane, when the sides of the first electrode 201 and the second common electrode layer 200c02 facing away from the connection layer 400 are flush, the chip structure 000 can be stably fixed to the driver backplane.

[0230] In the embodiment of the present application, the first common electrode layer 200c01 may include: a common electrode body 200c1, a first support portion 200c2 fixedly connected to the common electrode body 200c1, and two second support portions 200c3 fixedly connected to the first support portion 200c2. The common electrode body 200c1 may be electrically connected to the second common electrode layer 200c02. The first support portions 200c2 may be located around the common electrode body 200c1. Each second support portion 200c3 may be located on a side of the first support portion 200c2 facing away from the common electrode body 200c1. Of the two second support portions 200c3, one may be located between the first pixel light-emitting functional layer 200a1 and the second pixel light-emitting functional layer 200a2 in the row direction, and the other may be located between the second pixel light-emitting functional layer 200a2 and the third pixel light-emitting functional layer 200a3 in the column direction. In this way, the intensity of the entire light-emitting unit 200 can be ensured to be high, and the volume of the common electrode layer 200 c can be ensured to be large, thereby reducing the resistance for transmitting the common cathode signal in the light-emitting unit 200 .

[0231] In summary, the chip structure provided in the embodiments of the present application includes: a first substrate, a light-emitting unit, and a color conversion unit. The light-shielding layer in the color conversion unit may include: a main body portion and an extension portion distributed around the main body portion. Light emitted from each sub-light-emitting functional layer in the light-emitting unit is directed toward the second semiconductor layer. After the light generates an optical waveguide phenomenon within the second semiconductor layer, the light emitted from the edge of the second semiconductor layer is absorbed by the extension portion of the light-shielding layer. This reduces the probability of light leakage in the chip structure, resulting in a better display quality for a display panel integrating such a chip structure. Furthermore, a first encapsulation layer is provided between the light-shielding layer and the limiting dam layer, and the first encapsulation layer covers the main body portion of the light-shielding layer. Furthermore, the main body portion of the light-shielding layer overlaps with the orthographic projection of the isolation dam layer on the first substrate. Therefore, after water and oxygen from the external environment intrudes into the light-shielding layer, the water and oxygen that intrudes into the light-shielding layer can be isolated by the first encapsulation layer, preventing it from invading the isolation layer. This ensures that the water and oxygen that intrudes into the light-shielding layer does not corrode the optical functional layer, further improving the reliability of the optical functional layer and thereby enhancing the stability of the chip structure.

[0232] The embodiment of the present application also provides a display panel, which can be a display screen in a mobile phone, a laptop or a flat-panel computer, or an outdoor advertising screen. The display panel may include: a driving backplane, and a plurality of chip structures located on one side of the driving backplane. Here, each chip structure in the display panel can be the chip structure in the above embodiment. And each anode pad and cathode pad in the chip structure can be fixed on the driving backplane by welding to be electrically connected to the driving backplane. It should be noted that the driving backplane can provide corresponding driving signals to each chip structure, so that the light-emitting unit in the chip structure emits light, thereby allowing the display panel to present a corresponding display screen.

[0233] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0234] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless expressly limited otherwise.

[0235] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip structure, characterized in that: include: A first substrate, a light-emitting unit and a color conversion unit, wherein the color conversion unit is located at a light-emitting side of the light-emitting unit; The color conversion unit comprises: A light shielding layer located on one side of the first substrate, the light shielding layer comprising: a main body portion and an extension portion arranged around the main body portion, the main body portion having a plurality of light through holes; a defining dam layer located on a side of the light shielding layer away from the first substrate, the defining dam layer having a plurality of opening areas corresponding to the plurality of light through holes one by one, an orthographic projection of the opening areas on the first substrate overlapping with an orthographic projection of the corresponding light through holes on the first substrate, an orthographic projection of the body portion on the first substrate overlapping with an orthographic projection of the defining dam layer on the first substrate, and the extension portion protruding from an outer contour of the defining dam layer in a direction parallel to the first substrate; a first encapsulation layer located between the light shielding layer and the defining dam layer, the first encapsulation layer covering the main body portion and covering at least a portion of the extending portion; An optical functional layer located inside the opening area, at least a portion of the optical functional layer is used to convert the color of light entering the optical functional layer; and a second encapsulation layer located on a side of the definition dam layer away from the first substrate, the second encapsulation layer having a first contact region in contact with the first encapsulation layer, and the first contact region being arranged around the definition dam layer.

2. The chip structure according to claim 1, characterized in that: The first contact area is in the shape of a ring, and the width of the ring ranges from 0.5 micrometers to 60 micrometers; The shape enclosed by the outer contour of the first substrate is a rectangle, and the length and width of the rectangle are both less than or equal to 500 micrometers.

3. The chip structure according to claim 1, characterized in that: In a direction parallel to the first substrate, a distance between an outer contour of the light shielding layer and an outer contour of the first substrate is less than or equal to 20 micrometers.

4. The chip structure according to claim 1, characterized in that: The outer contour of the first substrate is flush with the outer contour of the light shielding layer.

5. The chip structure according to claim 3, characterized in that: The chip structure has a first side and a second side that are relatively arranged. In a direction parallel to the first substrate, the distance between the boundary contour of the light-shielding layer and the outer contour of the first substrate adjacent to the first side is a first distance, and the distance between the light-shielding layer and the boundary contour of the outer contour of the first substrate adjacent to the second side is a second distance. The sum of the first distance and the second distance is greater than or equal to 5 microns.

6. The chip structure according to claim 1, characterized in that: An outer contour of at least one of the first encapsulation layer and the second encapsulation layer is flush with an outer contour of the first substrate.

7. The chip structure according to claim 1, characterized in that: There is a distance between an outer contour of at least one of the first encapsulation layer and the second encapsulation layer and an outer contour of the first substrate.

8. The chip structure according to any one of claims 1 to 7, characterized in that: The outer side of the first substrate is a fracture surface, and the fracture surface includes: a first fracture portion, a second fracture portion, and a laser cutting portion located between the first fracture portion and the second fracture portion; The first fracture portion and the second fracture portion show traces of stress fracture, and the laser cut portion shows traces of laser cutting ablation.

9. The chip structure according to any one of claims 1 to 7, characterized in that: The color conversion unit also includes: a filter layer located between the first substrate and the optical functional layer; the filter layer includes a plurality of filter units corresponding one by one to the plurality of light holes, and the orthographic projection of the filter unit on the first substrate overlaps with the orthographic projection of the corresponding light hole on the first substrate.

10. The chip structure according to claim 9, characterized in that: The orthographic projections of the optical function layer and the definition dam layer on the first substrate are both located within the orthographic projection of the first encapsulation layer on the first substrate; The filter unit is located on a side of the first packaging layer away from the first substrate, and a portion of the first packaging layer is located in the light through hole; Alternatively, the filter unit is located on a side of the first packaging layer facing the first substrate. At least a portion of the filter layer is located in the light-through hole.

11. The chip structure according to claim 9, characterized in that: The first encapsulation layer has a plurality of auxiliary openings corresponding to the plurality of light-through holes one by one, and the orthographic projections of the auxiliary openings on the first substrate overlap with the orthographic projections of the corresponding light-through holes on the first substrate; At least a portion of the filter unit is located in the auxiliary opening, and two oppositely disposed surfaces of the filter unit are in contact with the first substrate and the optical functional layer respectively.

12. The chip structure according to claim 11, characterized in that: The orthographic projection of the auxiliary opening on the first substrate is located within the orthographic projection of the light-through hole on the first substrate, and a portion of the first packaging layer extends into the light-through hole and covers the inner wall of the light-through hole, so that the filter unit is spaced apart from the light-shielding layer.

13. The chip structure according to any one of claims 1-7, 10-12, characterized in that: The light shielding layer has at least one annular through groove, and the orthographic projections of the plurality of light through holes on the first substrate are located within the area enclosed by the orthographic projections of the annular through groove on the first substrate; A portion of the first packaging layer is located in the annular through groove.

14. The chip structure according to claim 13, characterized in that: The orthographic projection of the annular through groove on the first substrate is located within the orthographic projection of the defining dam layer on the first substrate.

15. The chip structure according to any one of claims 1-7, 10-12, and 14, characterized in that: The second packaging layer covers the side of the defining dam layer and the optical functional layer away from the first substrate, and covers the outer side of the defining dam layer; the light-emitting unit is located on the side of the second packaging layer away from the first substrate; The orthographic projections of the definition dam layer and the optical functional layer on the first substrate are both located within the orthographic projection of the second encapsulation layer on the first substrate.

16. The chip structure according to claim 15, characterized in that: The materials of the first encapsulation layer and the second encapsulation layer are both inorganic materials.

17. The chip structure according to any one of claims 1-7, 10-12, 14, and 16, characterized in that: The chip structure also includes: a connection layer located on the side of the second packaging layer away from the first substrate, the light-emitting unit is located on the side of the connection layer away from the first substrate, and the light-emitting unit is fixed to the side of the second packaging layer away from the first substrate through the connection layer.

18. The chip structure according to claim 17, characterized in that: The light-emitting unit includes: a plurality of sub-light-emitting functional layers corresponding to the plurality of opening areas one by one, and the orthographic projections of the sub-light-emitting functional layers on the first substrate overlap with the orthographic projections of the corresponding opening areas on the first substrate.

19. The chip structure according to claim 18, characterized in that: The plurality of sub-light-emitting functional layers include: a first sub-light-emitting functional layer, a second sub-light-emitting functional layer and a third sub-light-emitting functional layer; the plurality of sub-light-emitting functional layers emit a first light in a working state, and the first light includes at least one of blue light and ultraviolet light; The plurality of opening regions include: a first opening region, a second opening region and a third opening region; the first opening region is arranged corresponding to the first sub-light-emitting functional layer, the second opening region is arranged corresponding to the second sub-light-emitting functional layer, and the third opening region is arranged corresponding to the third sub-light-emitting functional layer; The optical functional layer includes: a first color conversion unit for converting the first light into red light, a second color conversion unit for converting the first light into green light, and a third color conversion unit for converting the first light into blue light or maintaining blue light; the first color conversion unit is located in the first opening area, the second color conversion unit is located in the second opening area, and the third color conversion unit is located in the third opening area.

20. The chip structure according to claim 19, characterized in that: Each of the plurality of sub-light-emitting functional layers comprises: a first electrode, a first semiconductor layer and a light-emitting layer stacked in a direction perpendicular to and toward the first substrate; The light emitting portion further comprises a second semiconductor layer and a common electrode layer, wherein the second semiconductor layer is located at the light emitting side of the plurality of sub-light emitting functional layers; The second semiconductor layer includes: a connecting portion and an auxiliary portion arranged in a direction parallel to the first substrate, the connecting portion is connected to the sub-light-emitting functional layer, the auxiliary portion connects the connecting portions to each other, the connecting portion and the auxiliary portion are an integral structure, and the common electrode layer is connected to the auxiliary portion. Internal connection settings.

21. The chip structure according to claim 20, characterized in that: The material of the first semiconductor layer includes P-type doped gallium nitride, and the light-emitting layer is a multi-quantum well layer; The second semiconductor layer includes: a first sublayer and a second sublayer stacked in a direction vertical to and toward the first substrate, the first sublayer is located between the second sublayer and the light-emitting layer, the material of the first sublayer is N-type doped gallium nitride, and the second sublayer is a gallium nitride buffer layer.

22. The chip structure according to claim 20, characterized in that: Each of the sub-light-emitting functional layers further includes: a current spreading layer located between the first electrode and the first semiconductor layer.

23. A display panel, characterized in that: include: A driving backplane, and a plurality of chip structures arranged in an array on one side of the driving backplane, wherein the chip structure is the chip structure according to any one of claims 1 to 22.

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