Display device

Abstract

The invention relates to a display device comprising pixels arranged in a display area consisting of a first conductive layer comprising a first voltage line, a second conductive layer arranged on top of the first conductive layer and comprising a first conductive pattern superimposed on the first voltage line, a semiconductor layer arranged on top of the second conductive layer and comprising a first semiconductor pattern superimposed on the first conductive pattern, a third conductive layer arranged on top of the semiconductor layer and comprising a second conductive pattern superimposed on the first conductive pattern, and a fourth conductive layer arranged on top of the third conductive layer and comprising a data line and a third conductive pattern superimposed on the second conductive pattern, wherein the first voltage line comprises a body extending in the first direction and a shield extending from the body in the second direction to superimpose the data line, wherein the second direction intersects the first direction.

Description

display device

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device with improved display quality.

[0002] In recent years, the uses of display devices have become increasingly diverse. Furthermore, as display devices become thinner and lighter, their applications are expanding.

[0003] As display devices are utilized in various ways, there are various methods for designing the form of display devices, and the functions that can be grafted or linked to display devices are increasing.

[0004] Embodiments of the present invention can provide a display device with improved display quality. However, these tasks are exemplary and do not limit the scope of the present invention.

[0005] According to one aspect of the present invention, a display device including pixels arranged in a display area is provided, the display device including a first conductive layer including a first voltage line, a second conductive layer disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line, a semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the first conductive pattern, a third conductive layer disposed on the semiconductor layer and including a second conductive pattern overlapping the first conductive pattern, and a fourth conductive layer disposed on the third conductive layer and including a third conductive pattern overlapping the second conductive pattern and a data line, wherein the first voltage line includes a body portion extending in a first direction and a shield portion extending in a second direction intersecting the first direction from the body portion so as to overlap the data line.

[0006] In one embodiment, the third conductive layer further includes a first connection electrode, the fourth conductive layer further includes a second connection electrode, and the shielding portion can be connected to the first semiconductor pattern through the first connection electrode and the second connection electrode.

[0007] In one embodiment, the shielding portion may be spaced apart from the first semiconductor pattern on the plane.

[0008] In one embodiment, the first conductive layer further includes a fourth conductive pattern overlapping the second conductive pattern, the second conductive pattern being connected to the fourth conductive pattern, and the first conductive pattern being connected to the third conductive pattern.

[0009] In one embodiment, the data line includes a first data line, a second data line, and a third data line, and the shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line, and the areas of the first shielding portion, the second shielding portion, and the third shielding portion may be the same.

[0010] In one embodiment, the data line includes a first data line, a second data line, and a third data line, and the shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line, and an area of ​​the first shielding portion may be different from an area of ​​the second shielding portion and an area of ​​the third shielding portion.

[0011] In one embodiment, the pixel includes a red pixel emitting red light, a blue pixel emitting blue light, and a green pixel emitting green light, and the first data line can be connected to the red pixel.

[0012] In one embodiment, the first conductive layer may further include a second voltage line extending in the first direction, and the semiconductor layer may further include a second semiconductor pattern connected between the data line and the second voltage line.

[0013] In one embodiment, the third conductive layer further includes a first gate line overlapping the first semiconductor pattern and transmitting a first gate signal and a second gate line overlapping the second semiconductor pattern and transmitting a second gate signal, and the pixel operates in a non-emission period and a light-emitting period during one frame period, and in the non-emission period, after an on voltage is supplied to the second gate signal, an on voltage may be supplied to the first gate signal, and after an off voltage is supplied to the second gate signal, an off voltage may be supplied to the first gate signal.

[0014] In one embodiment, when the second gate signal is at an on voltage, a reference voltage can be transmitted from the second voltage line to the second conductive pattern.

[0015] In one embodiment, the fifth conductive layer may further include a third voltage line disposed on the fourth conductive layer and extending in the second direction and overlapping the data line.

[0016] In one embodiment, the display device further includes a voltage supply line disposed in a peripheral area outside the display area and extending in the first direction, and the third voltage line can be connected to the voltage supply line in the peripheral area across the display area.

[0017] In one embodiment, the pixel includes a display element including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, and a voltage supplied to the third voltage line and a voltage supplied to the counter electrode may be the same.

[0018] In one embodiment, the pixel includes a display element including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, and a voltage supplied to the third voltage line and a voltage supplied to the counter electrode may be different.

[0019] In one embodiment, the display device may further include a fifth conductive layer disposed on the fourth conductive layer and including a fourth voltage line extending in the second direction, and a sixth conductive layer disposed on the fifth conductive layer and including pixel electrodes, auxiliary electrodes, and fifth voltage lines extending in the first direction and connecting adjacent auxiliary electrodes among the auxiliary electrodes.

[0020] In one embodiment, the display device further includes a pixel definition film disposed on the sixth conductive layer and defining pixel apertures and auxiliary apertures, wherein the pixel apertures overlap each of the pixel electrodes, and the auxiliary apertures overlap each of the auxiliary electrodes that overlap the fourth voltage line among the auxiliary electrodes.

[0021] According to another aspect of the present invention, a pixel circuit including a first pixel circuit connected to a first light-emitting diode and a second pixel circuit connected to a second light-emitting diode, wherein each of the first pixel circuit and the second pixel circuit includes a first voltage line extending in a first direction, a data line disposed on the first voltage line and extending in a second direction intersecting the first direction, a capacitor including a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode, a first transistor connected between the first voltage line and the capacitor, a second transistor connected to the data line and a gate electrode of the first transistor, a second voltage line extending in the first direction, a third transistor connected to the gate electrode of the first transistor, and a fourth transistor connected between the first voltage line and the first transistor, wherein the first voltage line includes a body portion and the data line and A display device is provided that includes a shield extending in the second direction from the body portion so as to overlap.

[0022] In one embodiment, the area of ​​the shielding portion of the first pixel circuit may be smaller than the area of ​​the shielding portion of the second pixel circuit.

[0023] In one embodiment, the first light-emitting diode can emit red light.

[0024] In one embodiment, the first voltage line and the second voltage line may be arranged on the same layer.

[0025] In one embodiment, the first pixel circuit and the second pixel circuit operate in a non-emission period and an emission period during one frame period, and the non-emission period may include a first period in which the third transistor and the fourth transistor are turned on before a writing period in which a data signal is supplied from the data line, and a second period in which the fourth transistor remains turned on after the third transistor is turned off.

[0026] In one embodiment, each of the first light-emitting diode and the second light-emitting diode includes a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, and the display device may further include auxiliary electrodes positioned on the same layer as the pixel electrode, and a third voltage line connecting the auxiliary electrodes and extending in the first direction.

[0027] In one embodiment, the device further includes a fourth voltage line disposed between the data line and the pixel electrode and extending in the second direction, and an auxiliary electrode overlapping the fourth voltage line among the auxiliary electrodes may be connected to the third voltage line.

[0028] In one embodiment, the auxiliary electrode overlapping the fourth voltage line can be in direct contact with the counter electrode.

[0029] In one embodiment, the display device further includes a fifth voltage line positioned on the same layer as the fourth voltage line and overlapping the data line, wherein the fifth voltage line can be separated from the third voltage line by at least one insulating layer.

[0030] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0031] According to embodiments of the present invention, a display device with improved display quality can be provided. Of course, the scope of the present invention is not limited by these effects.

[0032] Figures 1 and 2 are drawings schematically illustrating a display device.

[0033] FIG. 3 is an equivalent circuit diagram schematically showing one pixel included in a display device according to one embodiment of the present invention.

[0034] Figure 4 is a timing diagram of signals for explaining the operation of the pixel shown in Figure 3.

[0035] FIG. 5 is a circuit diagram schematically showing the connection relationship between pixels and second initialization voltage lines according to one embodiment of the present invention.

[0036] Figures 6 to 11 are schematic layer-by-layer layout diagrams showing pixels according to one embodiment of the present invention.

[0037] Fig. 12 is a layout diagram schematically showing the arrangement of pixel electrodes of pixels according to one embodiment of the present invention.

[0038] FIG. 13a, FIG. 13b and FIG. 14 are drawings schematically showing a first voltage line and a data line according to one embodiment of the present invention.

[0039] Fig. 15 is a layout diagram schematically showing the arrangement of vertical voltage lines according to one embodiment of the present invention.

[0040] FIG. 16 is a layout diagram schematically showing the arrangement of pixels and voltage lines according to one embodiment of the present invention.

[0041] FIGS. 17A and 17B are cross-sectional views schematically showing pixels and voltage lines according to one embodiment of the present invention.

[0042] FIGS. 18a and 18b are schematic drawings showing voltage lines according to one embodiment of the present invention.

[0043] Figures 19a to 19d are cross-sectional views showing the structure of a display element according to one embodiment of the present invention.

[0044] FIG. 20a and FIG. 20b are cross-sectional views showing the structure of a display element according to one embodiment of the present invention.

[0045] Fig. 21 is a cross-sectional view showing the structure of a pixel of a display device according to one embodiment of the present invention.

[0046] One embodiment of the present invention provides a display device including pixels arranged in a display area, the display device including a first conductive layer including a first voltage line, a second conductive layer disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line, a semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the first conductive pattern, a third conductive layer disposed on the semiconductor layer and including a second conductive pattern overlapping the first conductive pattern, and a fourth conductive layer disposed on the third conductive layer and including a third conductive pattern overlapping the second conductive pattern and a data line, wherein the first voltage line includes a body portion extending in a first direction and a shield portion extending in a second direction intersecting the first direction from the body portion so as to overlap the data line.

[0047] One embodiment of the present invention includes a first pixel circuit connected to a first light-emitting diode and a second pixel circuit connected to a second light-emitting diode, wherein each of the first pixel circuit and the second pixel circuit includes a first voltage line extending in a first direction, a data line disposed on the first voltage line and extending in a second direction intersecting the first direction, a capacitor including a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode, a first transistor connected between the first voltage line and the capacitor, a second transistor connected to the data line and a gate electrode of the first transistor, a second voltage line extending in the first direction, a third transistor connected to the gate electrode of the first transistor, and a fourth transistor connected between the first voltage line and the first transistor, wherein the first voltage line overlaps the body portion and the data line. A display device is provided that includes a shield extending from a body in the second direction.

[0048] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0050] In this specification, the terms "first," "second," "third," etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another. Although the terms "first," "second," "third," etc. may be used to describe various components, regions, layers, and / or zones, these components, regions, layers, and / or zones are not limited by these terms. Therefore, it will be understood that even if a "first" component, region, layer, or zone mentioned in this specification is referred to as a "second" component, region, layer, or zone, it falls within the technical protection scope of the present invention.

[0051] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0052] In this specification, terms such as “include” or “have” mean that a feature or component described in the specification exists, and do not preclude the possibility that one or more other features or components may be added.

[0053] In this specification, when it is said that a part such as a film, region, or component is on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

[0054] In this specification, when we say “planar”, it means when the target portion is viewed from above (e.g., when viewed in a direction perpendicular to the upper surface of the substrate), and when we say “cross-sectional”, it means when the target portion is viewed from the side in a cross-section cut vertically.

[0055] In this specification, the phrase "overlapping" a first component with a second component means that the first component is positioned above or below the second component, such that at least a portion of the first component overlaps the second component on a plane. In the drawings, the sizes of the components may be exaggerated or reduced for convenience of explanation. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and therefore, the present invention is not necessarily limited to what is shown.

[0056] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. In addition, in this specification, “at least one of A and B” refers to the case where it is A, or B, or both A and B.

[0057] In this specification, when X and Y are said to be connected, it may include cases where X and Y are functionally connected, cases where X and Y are directly connected, or cases where another component is interposed between X and Y and they are indirectly connected. Here, X and Y may be components (e.g., devices, elements, circuits, wiring, electrodes, terminals, films, layers, regions, etc.). For example, cases where X and Y are electrically connected may include cases where X and Y are directly electrically connected, and / or cases where X and Y are indirectly electrically connected with another component interposed between X and Y. For example, cases where X and Y are indirectly electrically connected may include cases where one or more elements (e.g., switches, transistors, capacitors, inductors, resistors, diodes, etc.) that enable electrical connection between X and Y are connected between X and Y. Therefore, the present invention is not limited to a given connection relationship, for example, a connection relationship shown in the drawings or detailed description, and may also include connection relationships other than those shown in the drawings or detailed description.

[0058] In this specification, "ON" used in connection with a device state may refer to an activated state of the device, and "OFF" may refer to a deactivated state of the device. "ON" used in connection with a signal received by a device may refer to a signal that activates the device, and "OFF" may refer to a signal that deactivates the device. A device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-type transistors and N-type transistors are opposite (lower versus higher) voltage levels.

[0059] In this specification, the x-direction, y-direction, and z-direction are not limited to directions along the three axes on the orthogonal coordinate system, and can be interpreted in a broad sense including these. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0060] Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted in their meanings appropriate to the relevant technical field and the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined otherwise.

[0061] A display device according to embodiments of the present invention is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), and the like, as well as a television, a laptop, a monitor, a billboard, and an Internet of Things (IOT) device. In addition, a display device according to an embodiment can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the display device according to one embodiment may be used as a dashboard of a vehicle, a CID (Center Information Display) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, and a display placed on the back of the front seat as entertainment for the rear seat of a vehicle. In addition, the display device may be a flexible device.

[0062] Figures 1 and 2 are drawings schematically illustrating a display device.

[0063] Referring to FIG. 1, a display device (10) may include a display area (DA) where an image is displayed and a peripheral area (PA) disposed around the display area (DA). The display device (10) may provide a predetermined image using light emitted from pixels disposed in the display area (DA). The peripheral area (PA) is an area disposed around the display area (DA) and may be a type of non-display area where pixels are not disposed. The display area (DA) may be entirely surrounded by the peripheral area (PA). Various wires for transmitting electrical signals to be applied to the display area (DA), and pads to which a printed circuit board or a driver IC chip is attached may be located in the peripheral area (PA).

[0064] Referring to FIG. 2, the display device (10) may include a pixel portion (11), a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0065] The pixel unit (11) may be provided in the display area (DA). The peripheral area (PA) may include various conductive lines for transmitting electrical signals to be applied to the display area (DA), external circuits electrically connected to the pixel circuits, and pads to which a printed circuit board or driver IC chip is attached. For example, the peripheral area (PA) may include a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0066] As illustrated in FIG. 2, a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of pixels (PX) connected thereto may be arranged in a pixel unit (11). The plurality of pixels (PX) may be arranged in various forms, such as a stripe arrangement, a pentile arrangement (diamond arrangement), and a mosaic arrangement, to implement an image. Each pixel (PX) includes an organic light-emitting diode (OLED) as a display element (light-emitting element), and the OLED may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel (PX) may emit light of, for example, red, green, blue, or white through the OLED. Each pixel (PX) may be connected to at least one corresponding gate line among the plurality of gate lines (GL) and to a corresponding data line among the plurality of data lines (DL).

[0067] The gate lines (GL) can each extend in the x direction (row direction) and be connected to pixels (PX) located in the same row. The gate lines (GL) can each transmit a gate signal to the pixels (PX) located in the same row. The data lines (DL) can each extend in the y direction (column direction) and be connected to pixels (PX) located in the same column. The data lines (DL) can each transmit a data signal to the pixels (PX) located in the same column in synchronization with the gate signal.

[0068] In one embodiment, the peripheral area (PA) may be a non-display area in which pixels (PX) are not arranged. In another embodiment, a portion of the peripheral area (PA) may be implemented as a display area (DA). For example, a plurality of pixels (PX) may be arranged in at least one corner of the peripheral area (PA) to overlap the gate driving circuit (13). This can reduce the dead area and expand the display area (DA).

[0069] The gate driving circuit (13) is connected to a plurality of gate lines (GL), and can generate a gate signal in response to a control signal (GCS) from a controller (19) and sequentially supply the same to the gate lines (GL). The gate line (GL) can be connected to a gate of a transistor included in a pixel (PX). The gate signal can be a gate control signal that controls turning on and off a transistor whose gate is connected to the gate line (GL). The gate signal can be a square wave signal including an on voltage that can turn on the transistor and an off voltage that can turn off the transistor. In one embodiment, the on voltage can be a high level voltage (first level voltage) or a low level voltage (second level voltage).

[0070] In FIG. 2, the pixel (PX) is illustrated as being connected to one gate line (GL), but this is merely exemplary, and the pixel (PX) may be connected to two or more gate lines, and the gate driving circuit (13) may supply two or more gate signals having different timings at which the on voltage is applied to the corresponding gate lines. For example, the pixel (PX) may be connected to the first to third gate lines and the first to second emission control lines, and the gate driving circuit (13) may apply the first gate signal (GW), the second gate signal (GI), the third gate signal (GR), the first emission control signal (EM), and the second emission control signal (EMB) to the first gate lines, the second gate lines, the third gate lines, the first emission control lines, and the second emission control lines, respectively. The first emission control signal (EM) may be a gate control signal that controls the turn-on and turn-off of a transistor whose gate is connected to the first emission control line, and the second emission control signal (EMB) may be a gate control signal that controls the turn-on and turn-off of a transistor whose gate is connected to the second emission control line.

[0071] The data driving circuit (15) is connected to a plurality of data lines (DL) and can supply a data signal (Vdata) to the data lines (DL) in response to a control signal (DCS) from a controller (19). The data signal (Vdata) supplied to the data line (DL) can be supplied to a pixel (PX) to which a gate signal is supplied. The data driving circuit (15) can convert input image data (DATA) having a grayscale input from the controller (19) into a data signal (Vdata) in the form of a voltage or current.

[0072] The power supply circuit (17) can generate voltages necessary for driving the pixels (PX) in response to a control signal (PCS) from the controller (19). The power supply circuit (170) can generate a first driving voltage (ELVDD) and a second driving voltage (ELVSS) and supply them to the pixels (PX). The first driving voltage (ELVDD) can be a high-level voltage provided to a first electrode (pixel electrode or anode) of a display element included in the pixel (PX). The second driving voltage (ELVSS) can be a low-level voltage provided to a second electrode (counter electrode or cathode) of a display element included in the pixel (PX). The power supply circuit (17) can generate a reference voltage (Vref) and an initialization voltage (Vaint) and supply them to the pixels (PX).

[0073] The voltage level of the first driving voltage (ELVDD) may be higher than the voltage level of the second driving voltage (ELVSS). The voltage level of the reference voltage (Vref) may be lower than the voltage level of the first driving voltage (ELVDD). The voltage level of the initialization voltage (Vaint) may be equal to or higher than the voltage level of the second driving voltage (ELVSS).

[0074] The controller (19) can generate control signals (GCS, DCS, PCS) based on signals input from the outside and supply them to the gate driving circuit (13), the data driving circuit (15), and the power supply circuit (17). The control signal (GCS) output to the gate driving circuit (13) can include a plurality of clock signals and a gate start signal. The control signal (DCS) output to the data driving circuit (15) can include a source start signal and clock signals.

[0075] The display device (10) includes a display panel, and the display panel may include a substrate. In the present specification, the fact that the substrate has a display area (DA) and a peripheral area (PA) means that the substrate has an area corresponding to the display area (DA) and an area corresponding to the peripheral area (PA). Pixels (PX) may be arranged in the display area (DA) of the substrate. Part or all of the gate driving circuit (13) may be formed directly in the peripheral area (PA) of the substrate during the process of forming transistors constituting the pixel circuit in the display area (DA) of the substrate. The data driving circuit (15), the power supply circuit (17), and the controller (19) may be formed in the form of separate integrated circuit chips or a single integrated circuit chip, respectively, and may be arranged on an FPCB (flexible printed circuit board) electrically connected to pads arranged on one side of the substrate. In another embodiment, the data drive circuit (15), power supply circuit (17), and controller (19) may be placed directly on the substrate in a COG (Chip On Glass) or COP (Chip On Plastic) manner.

[0076] In one embodiment, the plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors. In another embodiment, the plurality of transistors included in the pixel circuit may be P-type silicon thin film transistors. In another embodiment, some of the plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors, and other some may be P-type silicon thin film transistors.

[0077] An oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which an active pattern (semiconductor layer) includes an oxide. However, this is merely an example, and N-type transistors are not limited thereto. For example, an active pattern (semiconductor layer) included in an N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon), an organic semiconductor, etc. A silicon thin film transistor may be an LTPS (Low Temperature Poly-Silicon) thin film transistor in which an active pattern (semiconductor layer) includes amorphous silicon, polysilicon, etc.

[0078] FIG. 3 is an equivalent circuit diagram schematically showing one pixel included in a display device according to one embodiment of the present invention, and FIG. 4 is a timing diagram of signals for explaining the operation of the pixel shown in FIG. 3.

[0079] Referring to FIG. 3, a pixel (PX) may include an organic light-emitting diode (OLED) as a display element and a pixel circuit (PC) connected to the organic light-emitting diode (OLED). The pixel circuit (PC) may include first to sixth transistors (T1 to T6) and first and second capacitors (C1 and C2). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and each of the second to sixth transistors (T2 to T6) may be a switching transistor that transmits a signal. The first terminal (first electrode) of each of the first to sixth transistors (T1 to T6) may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, when the first terminal is a drain, the second terminal may be a source. The node to which the gate of the first transistor (T1) is connected may be defined as a first node (N1), and the node to which the second terminal (source terminal) of the first transistor (T1) is connected may be defined as a second node (N2). The node to which the pixel electrode (anode) of an organic light-emitting diode (OLED) is connected may be defined as a third node (N3).

[0080] A pixel (PX) may be connected to a first gate line (GWL) for transmitting a first gate signal (GW), a second gate line (GIL) for transmitting a second gate signal (GI), a third gate line (GRL) for transmitting a third gate signal (GR), a first emission control line (EML) for transmitting a first emission control signal (EM), a second emission control line (EMBL) for transmitting a second emission control signal (EMB), and a data line (DL) for transmitting a data signal (Vdata). In addition, the pixel (PX) may be connected to a driving voltage line (PL) for transmitting a first driving voltage (ELVDD), a reference voltage line (VL1) for transmitting a reference voltage (Vref), and an initialization voltage line (VL2) for transmitting an initialization voltage (Vaint).

[0081] A first transistor (T1) may be connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a gate, a first terminal connected to the driving voltage line (PL) via a fifth transistor (T5), and a second terminal connected to a second node (N2). The first transistor (T1) may include a first gate connected to the first node (N1) and a second gate connected to the second node (N2). The first gate and the second gate may be arranged to face each other in different layers. For example, the first gate and the second gate of the first transistor (T1) may be positioned to face each other with a semiconductor layer therebetween. Since the first capacitor (C1) is placed between the first node (N1) and the second node (N2), the first transistor (T1) can be placed between the driving voltage line (PL) and the first capacitor (C1). The first transistor (T1) can receive a data signal (Vdata) according to the switching operation of the second transistor (T2) and control the amount of driving current (Id) flowing to the organic light-emitting diode (OLED).

[0082] The second transistor (T2) may be connected between the data line (DL) and the first node (N1). The second transistor (T2) may be connected between the data line (DL) and the first gate of the first transistor (T1). The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on by the first gate signal (GW) transmitted to the first gate line (GWL) to electrically connect the data line (DL) and the first node (N1), and may transmit the data signal (Vdata) transmitted to the data line (DL) to the first node (N1).

[0083] A third transistor (T3) may be connected between a first node (N1) and a reference voltage line (VL1). The third transistor (T3) may be connected between the reference voltage line (VL1) and a first gate of the first transistor (T1). The third transistor (T3) may include a gate connected to a third gate line (GRL), a first terminal connected to the first node (N1), and a second terminal connected to the reference voltage line (VL1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit the reference voltage (Vref) transmitted to the reference voltage line (VL1) to the first node (N1).

[0084] The fourth transistor (T4) may be connected between the first transistor (T1) and the initialization voltage line (VL2). The fourth transistor (T4) may include a gate connected to the second gate line (GIL), a first terminal connected to the third node (N3), and a second terminal connected to the initialization voltage line (VL2). The fourth transistor (T4) may be turned on by a second gate signal (GI) transmitted to the second gate line (GIL) and may transmit the initialization voltage (Vaint) transmitted to the initialization voltage line (VL2) to the third node (N3).

[0085] The fifth transistor (T5) may be connected between the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the first emission control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to the first emission control signal (EM) transmitted to the first emission control line (EML).

[0086] The sixth transistor (T6) may be connected between the first transistor (T1) and the third node (N3). The sixth transistor (T6) may include a gate connected to the second emission control line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The sixth transistor (T6) may be turned on or off according to the second emission control signal (EMB) transmitted to the second emission control line (EMBL).

[0087] When the fifth transistor (T5) is turned on in response to the first emission control signal (EM) transmitted through the first emission control line (EML), and the sixth transistor (T6) is turned on in response to the second emission control signal (EMB) transmitted through the second emission control line (EMBL), a driving current (Id) can flow to the organic light-emitting diode (OLED).

[0088] A first capacitor (C1) may be connected between a first node (N1) and a second node (N2). A first electrode of the first capacitor (C1) may be connected to the first node (N1), and a second electrode may be connected to the second node (N2). The first capacitor (C1) may serve as a storage capacitor and may store a voltage corresponding to a threshold voltage of the first transistor (T1) and a data signal (Vdata).

[0089] A second capacitor (C2) may be connected between a driving voltage line (PL) and a second node (N2). A first electrode of the second capacitor (C2) may be connected to the driving voltage line (PL), and a second electrode may be connected to the second node (N2). In one embodiment, the capacitance of the first capacitor (C1) may be greater than the capacitance of the second capacitor (C2).

[0090] An organic light-emitting diode (OLED) includes a pixel electrode (anode) connected to a third node (N3) and a counter electrode (cathode) facing the pixel electrode, and the counter electrode can be supplied with a second driving voltage (ELVSS). The counter electrode can be a common electrode common to a plurality of pixels (PX).

[0091] A pixel (PX) can display an image for each frame section. Referring to FIG. 4, one frame section can include a non-emitting section (NEP) and an emitting section (EP) in which the pixel (PX) does not emit light. The non-emitting section (NEP) can include a first initialization section (P1), a compensation section (P2), a writing section (P3), and a second initialization section (P4).

[0092] Each of the first gate signal (GW), the second gate signal (GI), the third gate signal (GR), the first emission control signal (EM), and the second emission control signal (EMB) may have a high-level voltage for a portion of the period and a low-level voltage for a portion of the period. Here, the high-level voltage may be an on-voltage that turns on the transistor, and the low-level voltage may be an off-voltage that turns off the transistor.

[0093] In the first initialization section (P1), a second gate signal (GI) with an on voltage may be supplied to the second gate line (GIL), and a third gate signal (GR) with an on voltage may be supplied to the third gate line (GRL). The first initialization section (P1) may be defined as a section in which a period in which the on voltage of the second gate signal (GI) is maintained (hereinafter, referred to as an on voltage period) and a period in which the on voltage of the third gate signal (GR) overlap. In the first initialization section (P1), the second emission control signal (EMB) may be supplied with an on voltage and then inverted to an off voltage and supplied. The first gate signal (GW) and the first emission control signal (EM) may be supplied with an off voltage.

[0094] The fourth transistor (T4) may be turned on by the second gate signal (GI), and the third transistor (T3) may be turned on by the third gate signal (GR). The second emission control signal (EMB), which was supplied as an on voltage during the first initialization section (P1), may be inverted to an off voltage, and the sixth transistor (T6), which is in a turned-on state, may be turned off. The first node (N1), that is, the gate of the first transistor (T1), may be initialized to a reference voltage (Vref) by the turned-on third transistor (T3). The third node (N3), that is, the pixel electrode of the organic light-emitting diode (OLED), may be initialized to an initialization voltage (Vaint) by the turned-on fourth transistor (T4). The second node (N2) can be initialized to the initialization voltage (Vaint) by the turned-on fourth transistor (T4) and the turned-on sixth transistor (T6).

[0095] In the compensation section (P2), a third gate signal (GR) with an on voltage may be supplied to the third gate line (GRL), and a first emission control signal (EM) with an on voltage may be supplied to the first emission control line (EML). The compensation section (P2) may be defined as a section in which the on voltage period of the third gate signal (GR) and the on voltage period of the first emission control signal (EM) overlap. The first gate signal (GW), the second gate signal (GI), and the second emission control signal (EMB) may be supplied with an off voltage.

[0096] The third transistor (T3) can be turned on by the third gate signal (GR), and the fifth transistor (T5) can be turned on by the first emission control signal (EM). Accordingly, the reference voltage (Vref) is supplied to the first node (N1), and the first driving voltage (ELVDD) is supplied to the first terminal of the first transistor (T1), so that the first transistor (T1) can be turned on. When the voltage of the second terminal of the first transistor (T1), i.e., the second node (N2), falls below the difference (Vref-Vth) between the reference voltage (Vref) and the threshold voltage (Vth) of the first transistor (T1), the first transistor (T1) can be turned off. And, a voltage corresponding to the threshold voltage (Vth) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth) of the first transistor (T1) can be compensated.

[0097] The third gate signal (GR) can maintain the on voltage from the starting point of the first initialization section (P1) and can be reversed to the off voltage at the end point of the compensation section (P2). The first emission control signal (EM) can maintain the on voltage for a first time (t1) from the end point of the compensation section (P2). After the end point of the compensation section (P2), when the third gate signal (GR) is supplied with the off voltage, the third transistor (T3) is turned off, so that the first node (N1) can be electrically floating for the first time (t1). Therefore, when the first emission control signal (EM) is reversed to the off voltage thereafter, the gate-source voltage (Vgs) of the first transistor (T1) can be maintained relatively constant, and the kickback phenomenon caused by the turn-off of the fifth transistor (T5) can be reduced. In one embodiment, the first time (t1) may be 4 horizontal periods (4H).

[0098] In the write section (P3), the first gate signal (GW) of the on voltage may be supplied to the first gate line (GWL) to turn on the second transistor (T2). At this time, the second gate signal (GI), the third gate signal (GR), the first emission control signal (EM), and the second emission control signal (EMB) may be supplied with an off voltage, and the third to sixth transistors (T3, T4, T5, and T6) may be turned off. The second transistor (T2) may transfer the data signal (Vdata) from the data line (DL) to the first node (N1), i.e., the gate of the first transistor (T1). Accordingly, the voltage of the first node (N1) may be changed from the reference voltage (Vref) to a voltage corresponding to the data signal (Vdata).

[0099] The first gate signal (GW) applied to the pixel circuit of the nth row may partially overlap with the first gate signal (GW[n+1]) applied to the pixel circuit of the subsequent row (n+1th row). For example, the first gate signal (GW) applied to the pixel circuit of the nth row and the first gate signal (GW[n+1]) applied to the pixel circuit of the n+1th row may overlap for a second time period (t2). In one embodiment, the second time period (t2) may be at least two horizontal periods (2H). By partially overlapping the first gate signals (GW), high-frequency driving of the display device (10) may be possible.

[0100] In the second initialization section (P4), a second gate signal (GI) of an on voltage may be supplied to the second gate line (GIL). The second initialization section (P4) may be defined as an on voltage period of the second gate signal (GI) after the write section (P3). In the second initialization section (P4), the second emission control signal (EMB) may be supplied as an off voltage and then inverted to an on voltage and supplied. The first gate signal (GW), the third gate signal (GR), and the first emission control signal (EM) may be supplied as an off voltage, and the second transistor (T2), the third transistor (T3), and the fifth transistor (T5) may be turned off. The fourth transistor (T4) may be turned on by the second gate signal (GI), and thereafter, the sixth transistor (T6) may be turned on by the second emission control signal (EMB). The third node (N3), i.e., the pixel electrode of the organic light-emitting diode (OLED), can be initialized to the initialization voltage (Vaint) by the turned-on fourth transistor (T4). The second node (N2) can be initialized to the initialization voltage (Vaint) by the turned-on fourth transistor (T4) and the turned-on sixth transistor (T6). By initializing the second node (N2) before the emission period (EP), the variable refresh rate characteristics of the display device (10) can be improved.

[0101] Even after the end point of the second initialization section (P4), the second emission control signal (EMB) can maintain the on voltage. Thereafter, in the emission section (EP), the first emission control signal (EM) can be supplied with an on voltage, and the first gate signal (GW), the second gate signal (GI), and the third gate signal (GR) can be supplied with an off voltage. The second transistor (T2), the third transistor (T3), and the fourth transistor (T4) can be turned off by the first gate signal (GW), the second gate signal (GI), and the third gate signal (GR), and the fifth transistor (T5) and the sixth transistor (T6) can be turned on by the first emission control signal (EM) and the second emission control signal (EMB).

[0102] The first transistor (T1) outputs a driving current (Id) having a magnitude corresponding to the gate-source voltage (Vgs), and the organic light-emitting diode (OLED) can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0103] FIG. 5 is a drawing schematically showing the connection relationship between pixels and initialization voltage lines according to one embodiment of the present invention.

[0104] Referring to FIG. 5, the pixels may include a first pixel (PXr) that emits light in a first color, a second pixel (PXg) that emits light in a second color, and a third pixel (PXb) that emits light in a third color. For example, the first pixel (PXr) may be a red pixel, the second pixel (PXg) may be a green pixel, and the third pixel (PXb) may be a blue pixel. In one embodiment, considering the emission characteristics of the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb), initialization voltages (Vaint) of different sizes may be supplied to the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb).

[0105] As illustrated in FIG. 5, a first pixel (PXr) may be connected to a first initialization voltage line (VL21) that supplies a first initialization voltage (Vaint1), a second pixel (PXg) may be connected to a second initialization voltage line (VL22) that supplies a second initialization voltage (Vaint2), and a third pixel (PXb) may be connected to a third initialization voltage line (VL23) that supplies a third initialization voltage (Vaint3). The first initialization voltage (Vaint1), the second initialization voltage (Vaint2), and the third initialization voltage (Vaint3) may have different magnitudes.

[0106] In another embodiment, the third initialization voltage line may be omitted, the first pixel (PXr) and the third pixel (PXb) may be connected to the first initialization voltage line, and the second pixel (PXg) may be connected to the second initialization voltage line. In another embodiment, the third initialization voltage line may be omitted, the first pixel (PXr) and the second pixel (PXg) may be connected to the first initialization voltage line, and the third pixel (PXb) may be connected to the second initialization voltage line. In another embodiment, the third initialization voltage line may be omitted, the first pixel (PXr) may be connected to the first initialization voltage line, and the second pixel (PXg) and the third pixel (PXb) may be connected to the second initialization voltage line.

[0107] An embodiment of the present invention can improve issues of low-gray luminance change and color change due to differences in characteristics of an organic light-emitting diode (OLED) by providing two or more second initialization voltage lines (VL2) connected to at least one of a first pixel (PXr), a second pixel (PXg), and a third pixel (PXb) and supplying different initialization voltages (Vaint).

[0108] Figures 6 to 11 are schematic layout diagrams of pixels according to one embodiment of the present invention. Figure 6 is a layout diagram schematically showing the positions of transistors, capacitors, etc. of the pixel circuit illustrated in Figure 3. Figures 7 to 11 are layout diagrams schematically showing the components of the pixel circuit by layer.

[0109] A display area (DA) of a substrate is an area where rows (pixel rows) and columns (pixel columns) intersect, and may include a plurality of circuit areas in which pixel circuits are arranged. In one embodiment, a unit circuit area including two or more circuit areas adjacent in the x-direction is defined, and a unit pixel may be defined by pixels arranged in the circuit areas constituting the unit circuit area. For example, the unit circuit area may include three first circuit areas (PCA1), second circuit areas (PCA2), and third circuit areas (PCA3) adjacent in the x-direction, and the unit pixel may include a first pixel (PXr), a second pixel (PXg), and a third pixel (PXb). The first circuit area (PCA1) may be an area in which the pixel circuit of the first pixel (PXr) is arranged. The second circuit area (PCA2) may be an area in which the pixel circuit of the second pixel (PXg) is arranged. The third circuit area (PCA3) may be an area where the pixel circuit of the third pixel (PXb) is placed.

[0110] Identical or similar components may be arranged in each layer of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Hereinafter, for convenience of illustration and description, identical or similar pixel circuit (PC) components are assigned the same identification numbers, and the description will focus on the first circuit area (PCA1). This can be equally applied to identical components in the second circuit area (PCA2) and the third circuit area (PCA3).

[0111] In Fig. 6, the pixel circuits arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) may each correspond to the pixel circuit (PC) of the pixel (PX) illustrated in Fig. 3. Each of Figs. 7 to 11 illustrates one conductive layer or semiconductor layer. In the present specification, the phrase “located on the same layer” means that a component is formed through the same manufacturing process, includes the same material, and has the same layer structure, film quality, electrical characteristics, etc. At least one insulating layer may be arranged between the conductive layers and the semiconductor layer. Hereinafter, description will be made with reference to Figs. 7 to 11 together. Hereinafter, the connection electrode may be an electrode that electrically connects wires and conductive patterns arranged on different layers to transmit a signal.

[0112] A first conductive layer (1100) may be arranged on a substrate. As illustrated in FIG. 7, the first conductive layer (1100) may include a driving voltage line (PL), a reference voltage line (VL1), a repair line (RPL), and a first conductive pattern (1110).

[0113] The first conductive pattern (1110) is of an island type and may be arranged in each of the first circuit area (PCA1) and the second circuit area (PCA2). In one embodiment, the first conductive pattern (1110) may not be arranged in the third circuit area (PCA3). The first conductive pattern (1110) may be the first capacitor electrode of the first capacitor (C1).

[0114] A driving voltage line (PL) extends in a first direction (x direction) and can cross a first circuit area (PCA1), a second circuit area (PCA2), and a third circuit area (PCA3). A first driving voltage (ELVDD) can be applied to the driving voltage line (PL). The driving voltage line (PL) can include a body portion (1121) extending in a first direction (x direction) in each circuit area, an electrode portion (1123) protruding in a second direction (y direction) from the body portion (1121), and a shield portion (SHP) protruding in the second direction (y direction) from the body portion (1121).

[0115] In one embodiment, the width of the body portion (1121) of the driving voltage line (PL) in the second direction (y direction) may be different in each circuit area. For example, the width of the body portion (1121) in the first circuit area (PCA1) may be smaller than the width of the body portion (1121) in the second circuit area (PCA2), and the width of the body portion (1121) in the second circuit area (PCA2) may be smaller than the width of the body portion (1121) in the third circuit area (PCA3).

[0116] In one embodiment, the electrode portion (1123) may be disposed in each of the first circuit area (PCA1) and the second circuit area (PCA2). The electrode portion (1123) may overlap the first semiconductor pattern (1310, see FIG. 9) and may include the first capacitor electrode of the second capacitor (C2). The electrode portion (1123) may not be disposed in the third circuit area (PCA3).

[0117] The shielding portion (SHP) may include a first shielding portion (1125) and a second shielding portion (1127) extending in opposite directions. For example, the first shielding portion (1125) may extend in the -y direction, and the second shielding portion (1127) may extend in the +y direction. In one embodiment, the areas of the shielding portions (SHP) of each circuit area may be different from each other. For example, the area of ​​the shielding portion (SHP) of the first circuit area (PCA1) may be smaller than the area of ​​the shielding portion (SHP) of the second circuit area (PCA2) and the area of ​​the shielding portion (SHP) of the third circuit area (PCA3). In one embodiment, in the first circuit area (PCA1), the second shielding portion (1127) may be omitted. For example, the shielding portion (SHP) of the first circuit area (PCA1) may include only the first shielding portion (1125), and the second circuit area (PCA2) and the third circuit area (PCA3) may each include the first shielding portion (1125) and the second shielding portion (1127). In another embodiment, the areas of the shielding portions (SHP) of the respective circuit areas may be substantially the same. For example, the shielding portion (SHP) of the first circuit area (PCA1), the shielding portion (SHP) of the second circuit area (PCA2), and the shielding portion (SHP) of the third circuit area (PCA3) may each include the first shielding portion (1125) and the second shielding portion (1127).

[0118] On a plane, the shielding portion (SHP) may be spaced apart from the first semiconductor pattern (1310). In other words, the shielding portion (SHP) may not overlap with the first semiconductor pattern (1310). On a plane, the shielding portion (SHP) may overlap with the data line (DL).

[0119] The reference voltage line (VL1) extends in the first direction (x direction) and can cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The reference voltage line (VL1) can transmit the reference voltage (Vref) to the second terminal of the third transistor (T3).

[0120] When the data signal (Vdata) applied to the data line (DL) changes, the reference voltage (Vref) of the reference voltage line (VL1) may change instantaneously due to the coupling of the parasitic capacitor formed between the reference voltage line (VL1) and the data line (DL). Since the reference voltage line (VL1) is connected to the gate of the first transistor (T1), the gate-source voltage of the first transistor (T1) may change due to the voltage change of the reference voltage line (VL1). Therefore, pixels connected to the same reference voltage line (VL1) may emit light at a brightness different from a predetermined brightness, and horizontal line crosstalk may occur, which causes a line-shaped stain to appear on the image.

[0121] Embodiments of the present invention can increase the distance between the reference voltage line (VL1) and the data line (DL) by including the reference voltage line (VL1) in the first conductive layer (1100), which is the conductive layer located at the lowest position. Accordingly, the parasitic capacitance between the reference voltage line (VL1) and the data line (DL) of the display device (10) is reduced, so that high-quality images can be displayed while preventing or reducing line crosstalk.

[0122] The repair line (RPL) extends in the first direction (x direction) and can cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0123] A first insulating layer may be disposed on a first conductive layer (1100), and a second conductive layer (1200) may be disposed on the first insulating layer as illustrated in FIG. 8. The second conductive layer (1200) may include a lower first gate line (GWLa), a second initialization voltage line (VL22), a third initialization voltage line (VL23), and a second conductive pattern (1210).

[0124] The second conductive pattern (1210) is of an island type and can be arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), respectively. In each of the first circuit area (PCA1) and the second circuit area (PCA2), the second conductive pattern (1210) is arranged to overlap the first conductive pattern (1110), and can define a hole (1210H) that exposes a portion of the first conductive pattern (1110). The second conductive pattern (1210) can include a lower gate electrode of the first transistor (T1), a second capacitor electrode of the first capacitor (C1), and a second capacitor electrode of the second capacitor (C2). In other words, a part of the second challenge pattern (1210) and a part of the driving voltage line (PL) can overlap each other to form a second capacitor (C2).

[0125] Each of the lower first gate line (GWLa), the second initialization voltage line (VL22), and the third initialization voltage line (VL23) extends in the first direction (x direction) and can be arranged to cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0126] The second initialization voltage line (VL22) may be connected to the pixel circuit (PC) of the second pixel (PXg) located in the second circuit area (PCA2), and the third initialization voltage line (VL23) may be connected to the pixel circuit (PC) of the third pixel (PXb) located in the second circuit area (PCA2). The second initialization voltage (Vaint2) supplied to the second initialization voltage line (VL22) may be different from the third initialization voltage (Vaint3) supplied to the third initialization voltage line (VL23).

[0127] A second insulating layer may be disposed on a second conductive layer (1200), and a semiconductor layer (1300) may be disposed on the second insulating layer as illustrated in FIG. 9. A third insulating layer may be disposed on the semiconductor layer (1300), and a third conductive layer (1400) may be disposed on the third insulating layer. For convenience of explanation, FIG. 9 illustrates the semiconductor layer (1300) and the third conductive layer (1400) together.

[0128] The semiconductor layer (1300) may include an oxide semiconductor material. The semiconductor layer (1300) may include a first semiconductor pattern (1310), a second semiconductor pattern (1320), and a third semiconductor pattern (1330). Each of the first semiconductor pattern (1310), the second semiconductor pattern (1320), and the third semiconductor pattern (1330) may include a source region, a drain region, and a channel region between the source region and the drain region of each of the first to sixth transistors (T1 to T6).

[0129] The first semiconductor pattern (1310) may include a source region (S1) and a drain region (D1) of the first transistor (T1) and a source region (S5) and a drain region (D5) of the fifth transistor (T5). The second semiconductor pattern (1320) may include a source region (S2) and a drain region (D2) of the second transistor (T2) and a source region (S3) and a drain region (D3) of the third transistor (T3). The third semiconductor pattern (1330) may include a source region (S4) and a drain region (D4) of the fourth transistor (T4) and a source region (S6) and a drain region (D6) of the sixth transistor (T6).

[0130] The third conductive layer (1400) may include an upper first gate line (GWLb), a second gate line (GIL), a third gate line (GRL), a first emission control line (EML), a second emission control line (EMBL), a first initialization voltage line (VL21), a first connection electrode (1410), a third conductive pattern (1420), a fourth conductive pattern (1430), and a second connection electrode (1440).

[0131] The first connection electrode (1410) overlaps with the reference voltage line (VL1) and can be connected to the reference voltage line (VL1) through a contact hole.

[0132] Each of the third challenge pattern (1420) and the fourth challenge pattern (1430) may be provided in an island type. The third challenge pattern (1420) and the fourth challenge pattern (1430) may be arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), respectively.

[0133] The third conductive pattern (1420) overlaps with the second semiconductor pattern (1320) and may include a gate electrode of the second transistor (T2). The fourth conductive pattern (1430) overlaps with the first semiconductor pattern (1310) and may be connected to the first conductive pattern (1110) through a contact hole that overlaps with a hole (1210H) of the second conductive pattern (1210). The fourth conductive pattern (1430) may include an upper gate electrode (G1) of the first transistor (T1) and a third capacitor electrode of the first capacitor (C1).

[0134] The second connection electrode (1440) overlaps with the first shielding portion (1125) of the driving voltage line (PL) and can be connected to the driving voltage line (PL) through a contact hole.

[0135] The upper first gate line (GWLb), the second gate line (GIL), the third gate line (GRL), the first emission control line (EML), the second emission control line (EMBL), and the first initialization voltage line (VL21) extend in the first direction (x direction) and can cross the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3).

[0136] The upper first gate line (GWLb) roughly overlaps the lower first gate line (GWLa) and can be connected to the lower first gate line (GWLa) through a contact hole.

[0137] The second gate line (GIL) may overlap the third semiconductor pattern (1330). The second gate line (GIL) may include the gate electrode (G4) of the fourth transistor (T4). The third gate line (GRL) may overlap the second semiconductor pattern (1320). The third gate line (GRL) may include the gate electrode (G3) of the third transistor (T3). The first emission control line (EML) may overlap the first semiconductor pattern (1310). The first emission control line (EML) may include the gate electrode (G5) of the fifth transistor (T5). The second emission control line (EMBL) may overlap the third semiconductor pattern (1330). The second emission control line (EMBL) may include a gate electrode (G6) of the sixth transistor (T6).

[0138] The first initialization voltage line (VL21) may be connected to the pixel circuit (PC) of the first pixel (PXr) located in the first circuit area (PCA1). The first initialization voltage (Vaint1) supplied to the first initialization voltage line (VL21) may be different from the second initialization voltage (Vaint2) supplied to the second initialization voltage line (VL22) and the initialization voltage (Vaint3) supplied to the third initialization voltage line (VL23).

[0139] A fourth insulating layer may be disposed on a third conductive layer (1400), and a fourth conductive layer (1500) may be disposed on the fourth insulating layer as illustrated in FIG. 10. The fourth conductive layer (1500) may include a data line (DL), a third connection electrode (1510), a fourth connection electrode (1520), a fifth connection electrode (1530), a fifth conductive pattern (1540), a sixth connection electrode (1550), a seventh connection electrode (1560), and an eighth connection electrode (1570).

[0140] A data line (DL) may be arranged to extend in the second direction (y direction) in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The data line (DL) may be electrically connected to the drain area (D2) of the second transistor (T2) through a contact hole penetrating the insulating layers. The data line (DL) may overlap the shielding portion (SHP) of the driving voltage line (PL).

[0141] The third connection electrode (1510) can connect the upper first gate line (GWLb) and the third conductive pattern (1420) through contact holes. The third conductive pattern (1420) can transmit the first gate signal (GW) from the lower first gate line (GWLa) and the upper first gate line (GWLb) to the gate electrode G2) of the second transistor (T2).

[0142] The fourth connection electrode (1520) can connect the first connection electrode (1410) and the second semiconductor pattern (1320) through contact holes. The fourth connection electrode (1520) is connected to the reference voltage line (VL1) through the first connection electrode (1410) and can transmit the reference voltage (Vref) from the reference voltage line (VL1) to the source region (S3) of the third transistor (T3). Since one end of the second semiconductor pattern (1320) is connected to the data line (DL) and the other end of the second semiconductor pattern (1320) is connected to the reference voltage line (VL1), the second semiconductor pattern (1320) can be connected between the data line (DL) and the reference voltage line (VL1).

[0143] The fifth connection electrode (1530) can connect the second semiconductor pattern (1320) and the fourth conductive pattern (1430) through contact holes. The fifth connection electrode (1530) can connect the source region (S2) of the second transistor (T2), the drain region (D3) of the third transistor (T3), the upper gate electrode (G1) of the first transistor (T1), and the third capacitor electrode of the first capacitor (C1).

[0144] The fifth conductive pattern (1540) overlaps the fourth conductive pattern (1430) and can connect the second conductive pattern (1210), the first semiconductor pattern (1310), and the third semiconductor pattern (1330) through contact holes. The fifth conductive pattern (1540) can include the fourth capacitor electrode of the first capacitor (C1). The fifth conductive pattern (1540) can connect the lower gate electrode of the first transistor (T1), the second capacitor electrode of the first capacitor (C1), the second capacitor electrode of the second capacitor (C2), the source region (S1) of the first transistor (T1), and the drain region (D6) of the sixth transistor (T6). A portion of the first conductive pattern (1110), a portion of the second conductive pattern (1210), a portion of the fourth conductive pattern (1430), and a portion of the fifth conductive pattern (1540) that overlap each other can form a first capacitor (C1).

[0145] The sixth connection electrode (1550) can connect the first semiconductor pattern (1310) and the second connection electrode (1440) through contact holes. Since the second connection electrode (1440) is connected to the first shielding portion (1125) of the driving voltage line (PL), the sixth connection electrode (1550) can transmit the first driving voltage (ELVDD) from the driving voltage line (PL) to the drain region (D5) of the fifth transistor (T5).

[0146] The seventh connection electrode (1560) can be connected to the third semiconductor pattern (1330) through a contact hole. The seventh connection electrode (1560) can connect a pixel electrode of an organic light-emitting diode (OLED), a drain region (D4) of a fourth transistor (T4), and a source region (S6) of a sixth transistor (T6).

[0147] The eighth connection electrode (1570) may be connected to an initialization voltage line and a third semiconductor pattern (1330) through contact holes. The eighth connection electrode (1570) of the first circuit area (PCA1) may be connected to the first initialization voltage line (VL21), the eighth connection electrode (1570) of the second circuit area (PCA2) may be connected to the second initialization voltage line (VL22), and the eighth connection electrode (1570) of the third circuit area (PCA3) may be connected to the third initialization voltage line (VL23). The eighth connection electrode (1570) may connect the initialization voltage line and the source area (S4) of the fourth transistor (T4).

[0148] A fifth insulating layer may be disposed on a fourth conductive layer (1500), and a fifth conductive layer (1600) may be disposed on the fifth insulating layer as illustrated in FIG. 11. The fifth conductive layer (1600) may include a plurality of vertical voltage lines (VLv), a sixth conductive pattern (1610), and a ninth connection electrode (1620).

[0149] The sixth conductive pattern (1610) is of an island type and can be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The sixth conductive pattern (1610) overlaps the fifth connection electrode (1530) and can be connected to the fifth conductive pattern (1540) through a contact hole.

[0150] The ninth connecting electrode (1620) can be connected to the seventh connecting electrode (1560) through a contact hole. The ninth connecting electrode (1620) can connect the pixel electrode of the organic light-emitting diode (OLED) to the drain region (D4) of the fourth transistor (T4) and the source region (S6) of the sixth transistor (T6) through the seventh connecting electrode (1560).

[0151] The vertical voltage lines (VLv) extend in the second direction (y direction) and may be arranged in two each in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Each of the odd-numbered voltage lines (VLv1, VLv3, and VLv5) of the vertical voltage lines (VLv) may overlap the data line (DL), and each of the even-numbered voltage lines (VLv2, VLv4, and VLv6) may overlap the first semiconductor pattern (1310). In one embodiment, some adjacent vertical voltage lines of the vertical voltage lines (VLv) may be provided as an integral part. For example, as illustrated in FIG. 11, the second vertical voltage line (VLv2), the third vertical voltage line (VLv3), and the fourth vertical voltage line (VLv4) may be connected to each other by connecting portions and provided as an integral part.

[0152] Some of the odd-numbered voltage lines (VLv1, VLv3, VLv5) may be shield lines that are not electrically connected to other wires, semiconductor patterns, and conductive patterns within the display area (DA). The shield lines may be connected to voltage supply lines arranged in the peripheral area (PA) across the display area (DA) through contact holes. In one embodiment, the voltage supply lines may be common voltage supply lines that transmit a second driving voltage (ELVSS). In another embodiment, the voltage supply lines may be driving voltage supply lines that transmit a first driving voltage (ELVDD), a first initialization voltage supply line that transmits a first initialization voltage (Vaint1), a second initialization voltage supply line that transmits a second initialization voltage (Vaint2), or a third initialization voltage supply line that supplies a third initialization voltage (Vaint3).

[0153] Each of the vertical voltage lines (VLv) can receive a plurality of voltages supplied to the pixels (PXr, PXg, PXb), for example, a first driving voltage (ELVDD), a second driving voltage (ELVSS), a reference voltage (Vref), a first initialization voltage (Vaint1), a second initialization voltage (Vaint2), or a third initialization voltage (Vaint3). The vertical voltage lines (VLv) can be arranged along the first direction (x direction) according to a predetermined rule. The arrangement rule of the vertical voltage lines (VLv) will be described later in the description of Fig. 15.

[0154] Fig. 12 is a layout diagram schematically showing the arrangement of pixel electrodes of pixels according to one embodiment of the present invention.

[0155] Referring to FIG. 12, a sixth insulating layer may be disposed on a fifth conductive layer (1600), and a sixth conductive layer (1700) may be disposed on the sixth insulating layer. The sixth conductive layer (1700) may include pixel electrodes (PE), auxiliary electrodes (AE), and horizontal voltage lines (VLh).

[0156] The pixel electrodes (PE) may include a first pixel electrode (210r) included in an organic light-emitting diode (OLED) of a first pixel (PXr), a second pixel electrode (210g) included in an organic light-emitting diode (OLED) of a second pixel (PXg), and a third pixel electrode (210b) included in an organic light-emitting diode (OLED) of a third pixel (PXb).

[0157] Pixel electrodes (PE) may form rows and columns in the display area (DA). Second pixel electrodes (210g) and first pixel electrodes (210r) may be arranged in odd columns (M1, M3), and third pixel electrodes (210b) may be arranged in even columns (M2, M4). In even columns (M2, M4), auxiliary electrodes (AE) may be arranged between the third pixel electrodes (210b). Second pixel electrodes (210g) may be arranged in odd rows (N1, N3), and first pixel electrodes (210r) may be arranged in even rows (N2, N4). The third pixel electrode (210b) has a long rectangular shape in the second direction (y direction) and may be arranged across adjacent odd rows and even rows.

[0158] Neighboring auxiliary electrodes (AE) in the first direction (x direction) can be connected by horizontal voltage lines (VLh). Some of the auxiliary electrodes (AE) can be in direct contact with the counter electrode of the organic light-emitting diode (OLED) through holes formed through a laser drilling process.

[0159] The horizontal voltage lines (VLh) extend in the first direction (x direction) and can be arranged with a two-row spacing. For example, the first row (N1) and the second row (N2) can be arranged between the first horizontal voltage line (VLh1) and the second horizontal voltage line (VLh2), and the third row (N3) and the fourth row (N4) can be arranged between the second horizontal voltage line (VLh2) and the third horizontal voltage line (VLh3).

[0160] In one embodiment, each of the horizontal voltage lines (VLh) may receive a plurality of voltages supplied to the pixels (PXr, PXg, PXb), for example, a first driving voltage (ELVDD), a second driving voltage (ELVSS), a reference voltage (Vref), a first initialization voltage (Vaint1), a second initialization voltage (Vaint2), or a third initialization voltage (Vaint3). Each of the horizontal voltage lines (VLh) may be connected to a corresponding vertical voltage line (VLv) through a contact hole within the display area (DA) to form a mesh structure.

[0161] FIGS. 13A, 13B, and 14 are schematic drawings illustrating a first voltage line and a data line according to an embodiment of the present invention. FIGS. 13A and 14 are schematic plan views illustrating a driving voltage line (PL) and a data line (DL) for convenience of explanation, and FIG. 13B is a cross-sectional view schematically illustrating a cross-section along line I-I' of the display device (10) illustrated in FIG. 13A.

[0162] Referring to FIG. 13A, a driving voltage line (PL) may extend in a first direction (x direction) and cross a first circuit area (PCA1), a second circuit area (PCA2), and a third circuit area (PCA3). The driving voltage line (PL) may include a body portion (1121) extending in the first direction (x direction) in each circuit area, an electrode portion (1123) protruding in a second direction (y direction) from the body portion (1121), and a shield portion (SHP) protruding in the second direction (y direction) from the body portion (1121).

[0163] In one embodiment, the width of the body portion (1121) of the driving voltage line (PL) in the second direction (y direction) may be different in each circuit area. For example, the width of the body portion (1121) in the first circuit area (PCA1) may be smaller than the width of the body portion (1121) in the second circuit area (PCA2), and the width of the body portion (1121) in the second circuit area (PCA2) may be smaller than the width of the body portion (1121) in the third circuit area (PCA3).

[0164] In one embodiment, the electrode portion (1123) may protrude in the second direction (y direction) from the body portion (1121). The electrode portion (1123) may be disposed in each of the first circuit area (PCA1) and the second circuit area (PCA2). The electrode portion (1123) may not be disposed in the third circuit area (PCA3).

[0165] The shielding portion (SHP) may protrude from the body portion (1121) in a second direction (y direction). The shielding portion (SHP) may be spaced apart from the electrode portion (1123) in a first direction (x direction). The shielding portion (SHP) may include a first shielding portion (1125) and a second shielding portion (1127) extending in opposite directions from the body portion (1121). For example, the first shielding portion (1125) may extend in the -y direction, and the second shielding portion (1127) may extend in the +y direction. In one embodiment, the area of ​​the shielding portion (SHP) of each circuit region may be substantially the same. For example, the shielding portion (SHP) of the first circuit area (PCA1), the shielding portion (SHP) of the second circuit area (PCA2), and the shielding portion (SHP) of the third circuit area (PCA3) may each include a first shielding portion (1125) and a second shielding portion (1127).

[0166] The data line (DL) extends in the second direction (y direction) and can be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The data line (DL) can overlap the shielding portion (SHP).

[0167] Referring to FIG. 13b, a driving voltage line (PL) and a first conductive pattern (1110) may be arranged on a substrate (100). The driving voltage line (PL) may include an electrode portion (1123) and a second shield portion (1127).

[0168] A first insulating layer (111) may be disposed on the driving voltage line (PL) and the first conductive pattern (1110), and a second conductive pattern (1210) may be disposed on the first insulating layer (111). The second conductive pattern (1210) may overlap the electrode portion (1123) and the first conductive pattern (1110). The electrode portion (1123) and a portion of the second conductive pattern (1210) overlapping the electrode portion (1123) may form a second capacitor (C2).

[0169] A second insulating layer (113) may be placed on a second conductive pattern (1210), and a first semiconductor pattern (1310) may be placed on the second insulating layer (113). The first semiconductor pattern (1310) may overlap an electrode portion (1123).

[0170] A third insulating layer (115) may be disposed on a first semiconductor pattern (1310). A fourth conductive pattern (1430) may be disposed on the third insulating layer (115). The fourth conductive pattern (1430) may overlap the second conductive pattern (1210). The fourth conductive pattern (1430) may be connected to the first conductive pattern (1110) through a contact hole penetrating the first insulating layer (111), the second insulating layer (113), and the third insulating layer (115).

[0171] A fourth insulating layer (117) may be disposed on a fourth conductive pattern (1430), and a fifth conductive pattern (1540) and a data line (DL) may be disposed on the fourth insulating layer (117). The fifth conductive pattern (1540) may overlap the fourth conductive pattern (1430). The fifth conductive pattern (1540) may be connected to the second conductive pattern (1210) through a contact hole penetrating the third insulating layer (115) and the fourth insulating layer (117).

[0172] The first conductive pattern (1110), the second conductive pattern (1210), the fourth conductive pattern (1430), and the fifth conductive pattern (1540) that overlap each other can form a first capacitor (C1). For example, the sum of the capacitance between the first conductive pattern (1110) and the second conductive pattern (1210), the capacitance between the second conductive pattern (1210) and the fourth conductive pattern (1430), and the capacitance between the fourth conductive pattern (1430) and the fifth conductive pattern (1540) can be the total capacitance of the first capacitor (C1).

[0173] The data line (DL) may overlap with the second shielding portion (1127) of the driving voltage line (PL). A first parasitic capacitor (Cp1) may be formed between the data line (DL) and the second shielding portion (1127), and a second parasitic capacitor (Cp2) may be formed between the data line (DL) and the first conductive pattern (1110).

[0174] As a comparative example, when the driving voltage line does not include the second shielding portion, the capacitance of the second parasitic capacitor between the data line and the first conductive pattern may increase, which may deteriorate the front of screen (FOS) characteristics of the display device. In addition, due to the coupling of the second parasitic capacitor, pixels connected to the same data line (DL) may emit light at a brightness different from the set brightness, which may cause vertical line crosstalk, which displays a line-shaped stain on the image.

[0175] Embodiments of the present invention include a second shielding portion (1127) in which a driving voltage line (PL) overlaps a data line (DL), so that the capacitance of a second parasitic capacitor (Cp2) can be reduced by the first parasitic capacitor (Cp1) formed by the data line (DL) and the second shielding portion (1127). Accordingly, the FOS characteristic of the display device (10) can be improved, and the display device (10) can display a high-quality image that prevents or reduces vertical line crosstalk.

[0176] A fifth insulating layer (118) may be arranged on the fifth conductive pattern (1540) and the data line (DL), and vertical voltage lines (VLv4, VLv5) may be arranged on the fifth insulating layer (118). The fourth vertical voltage line (VLv4) may overlap the first semiconductor pattern (1310) of the second circuit area (PCA2), and the fifth vertical voltage line (VLv5) may overlap the data line (DL) of the third circuit area (PCA3).

[0177] A sixth insulating layer (119) may be placed on the fourth vertical voltage line (VLv4) and the fifth vertical voltage line (VLv5).

[0178] Referring to FIG. 14, the driving voltage line (PL) may not include the second shielding portion (1127) in at least one of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). In this regard, FIG. 14 illustrates that the driving voltage line (PL) does not include the second shielding portion (1127) in the first circuit area (PCA1).

[0179] Therefore, the area of ​​the shielding portion (SHP) in the first circuit area (PCA1) may be different from the area of ​​the shielding portion (SHP) in the second circuit area (PCA2) and the area of ​​the shielding portion (SHP) in the third circuit area (PCA3). The area of ​​the shielding portion (SHP) in the first circuit area (PCA1) may be smaller than the area of ​​the shielding portion (SHP) in the second circuit area (PCA2) and the area of ​​the shielding portion (SHP) in the third circuit area (PCA3).

[0180] As described above, the second shielding portion (1127) can form a data line (DL) and a first parasitic capacitor (Cp1). When a data signal applied to the data line (DL) changes, the first driving voltage (ELVDD) of the driving voltage line (PL) can change instantaneously due to the coupling of the first parasitic capacitor (Cp1). The voltage of the second terminal of the first transistor (T1), i.e., the voltage of the second node (N2), changes due to the coupling of the second capacitor (C2) connected to the driving voltage line (PL), and this can change the gate-source voltage of the first transistor (T1). Therefore, pixels connected to the same driving voltage line (PL) may emit light at a brightness different from a predetermined brightness, and horizontal linear crosstalk may occur, which causes linear spots to appear on the image.

[0181] In order to prevent or reduce such horizontal line crosstalk, embodiments of the present invention can reduce the first parasitic capacitance (Cp1) of the pixel circuit by omitting the second shielding portion (1127) of the driving voltage line (PL) in at least one circuit area. In one embodiment, the second shielding portion (1127) of the driving voltage line (PL) can be omitted in the first circuit area (PCA1) where the pixel circuit of the first pixel (PXr) emitting red light is arranged.

[0182] Image Pattern E1E2E3CE1Black Box 0.24 %0.28 %0.32 %0.35 %White Box 0.20 %0.25 %0.30 %0.33 %

[0183] Table 1 shows the results of measuring the luminance deviation of pixels due to vertical line crosstalk of display devices according to embodiments (E1, E2, E3) of the present invention and comparative example (CE1).

[0184] In the first embodiment (E1), as illustrated in Fig. 13a, the areas of the shielding portion (SHP) of the first circuit area (PCA1), the shielding portion (SHP) of the second circuit area (PCA2), and the shielding portion (SHP) of the third circuit area (PCA3) are formed to be the same. In the second embodiment (E2), as illustrated in Fig. 14, the second shielding portion (1127) of the first circuit area (PCA1) is omitted, so that the area of ​​the shielding portion (SHP) of the first circuit area (PCA1) is formed to be smaller than the areas of the shielding portion (SHP) of the second circuit area (PCA2) and the shielding portion (SHP) of the third circuit area (PCA3). In the third embodiment (E3), the second shielding portion (1127) of the second circuit area (PCA2) was omitted, so that the area of ​​the shielding portion (SHP) of the second circuit area (PCA2) was formed smaller than the area of ​​the shielding portion (SHP) of the first circuit area (PCA1) and the area of ​​the shielding portion (SHP) of the third circuit area (PCA3). In the comparative example (CE1), the driving voltage line was formed such that the driving voltage line included the first shielding portions in each of the first to third circuit areas, but did not include the second shielding portion.

[0185] Referring to Table 1, it can be confirmed that the luminance deviation due to vertical line crosstalk is the lowest in the first embodiment (E1) in which the second shielding portion (1127) is formed in the driving voltage line (PL) in all circuit areas. When one second shielding portion (1127) is omitted in consideration of horizontal line crosstalk, it can be confirmed that the luminance deviation of the second embodiment (E2) in which the second shielding portion (1127) is omitted in the first circuit area (PCA1) is lower than the luminance deviation of the third embodiment (E3) in which the second shielding portion (1127) is omitted in the second circuit area (PCA2). That is, when the area of ​​the shielding portion (SHP) overlapping the data line (DL) connected to the first pixel (PXr) is different from the area of ​​the shielding portion (SHP) overlapping the data line (DL) connected to the second pixel (PXg) and the area of ​​the shielding portion (SHP) overlapping the data line (DL) connected to the third pixel (PXb), vertical line crosstalk and horizontal line crosstalk can be reduced together.

[0186] Fig. 15 is a schematic diagram illustrating an arrangement of vertical voltage lines according to one embodiment of the present invention. Fig. 15 illustrates a fifth conductive layer (1600) on which vertical voltage lines (VLv) are arranged.

[0187] Referring to Fig. 15, two vertical voltage lines (VLv) extending in the second direction (y direction) may be arranged in one pixel circuit. For example, a first vertical voltage line (VLv1) overlapping a data line and a second vertical voltage line (VLv2) overlapping a first semiconductor pattern may be arranged in a first circuit area (PCA1). Some adjacent vertical voltage lines among the vertical voltage lines (VLv) may be connected to each other and formed as one body.

[0188] The vertical voltage lines (VLv) can be arranged along the first direction (x direction) according to a predetermined rule. In one embodiment, the vertical voltage lines (VLv) can be arranged repeatedly in units of 12 circuit areas (PCA1, PCA2, ..., PCA12). Here, a pixel circuit of a first pixel (PXr) that emits red light may be arranged in the first circuit area (PCA1), the fourth circuit area (PCA4), the seventh circuit area (PCA7), and the tenth circuit area (PCA10), a pixel circuit of a second pixel (PXg) that emits green light may be arranged in the second circuit area (PCA2), the fifth circuit area (PCA5), the eighth circuit area (PCA8), and the eleventh circuit area (PCA11), and a pixel circuit of a third pixel (PXb) that emits blue light may be arranged in the third circuit area (PCA3), the sixth circuit area (PCA6), the ninth circuit area (PCA9), and the twelfth circuit area (PCA12).

[0189] A shield line (SVL) and a first auxiliary initialization voltage line (VL21a) may be arranged in a first circuit area (PCA1), a shield line (SVL) and an auxiliary reference voltage line (VL1a) may be arranged in a second circuit area (PCA2), and an auxiliary driving voltage line (PLa) may be arranged in a third circuit area (PCA3). A shield line (SVL) and an auxiliary driving voltage line (PLa) may be arranged in a fourth circuit area (PCA4), an auxiliary driving voltage line (PLa) may be arranged in a fifth circuit area (PCA5), and a shield line (SVL) and a third auxiliary initialization voltage line (VL23a) may be arranged in a sixth circuit area (PCA6). A shield line (SVL) and an auxiliary driving voltage line (PLa) may be arranged in the seventh circuit area (PCA7), a shield line (SVL) and a second auxiliary initialization voltage line (VL22a) may be arranged in the eighth circuit area (PCA8), and an auxiliary driving voltage line (PLa) may be arranged in the ninth circuit area (PCA9). An auxiliary driving voltage line (PLa) may be arranged in the tenth circuit area (PCA10), an auxiliary common voltage line (VSSL2) may be arranged in the eleventh circuit area (PCA11), and an auxiliary common voltage line (VSSL2) and an auxiliary driving voltage line (PLa) may be arranged in the twelfth circuit area.

[0190] A shield line (SVL) is a wire to which a shielding voltage is applied and may be a wire that is not electrically connected to other wires, semiconductor patterns, or conductive patterns within the display area (DA). The shield line (SVL) may be connected to a voltage supply line arranged in the peripheral area (PA) across the display area (DA).

[0191] Since the shield line (SVL) is not connected to the wires extending in the first direction (x direction) within the display area (DA), the influence of changes in the data signal may not be transmitted to the surrounding pixels. Accordingly, the display device can reduce or prevent multi-line horizontal crosstalk by having the shield line (SVL) overlapping the data line.

[0192] In one embodiment, the voltage supply line connected to the shield line (SVL) may be a common voltage supply line transmitting a second driving voltage (ELVSS). In another embodiment, the voltage supply line may be a first driving voltage supply line transmitting a first driving voltage (ELVDD), a first initialization voltage supply line transmitting a first initialization voltage (Vaint1), a second initialization voltage supply line transmitting a second initialization voltage (Vaint2), or a third initialization voltage supply line supplying a third initialization voltage (Vaint3).

[0193] The auxiliary driving voltage line (PLa) may be a wire that transmits the first driving voltage (ELVDD). The auxiliary driving voltage line (PLa) may be connected to the overlapping sixth connection electrode (1550) through a contact hole. The auxiliary driving voltage line (PLa) may form a mesh structure in the driving voltage line (PL) and the display area (DA).

[0194] The first auxiliary initialization voltage line (VL21a) may be a wire that transmits the first initialization voltage (Vaint1). The first auxiliary initialization voltage line (VL21a) may be connected to the overlapping eighth connection electrode (1570) through a contact hole. The first auxiliary initialization voltage line (VL21a) may form a mesh structure in the display area (DA) with the first initialization voltage line (VL21).

[0195] The second auxiliary initialization voltage line (VL22a) may be a wire that transmits the second initialization voltage (Vaint2). The second auxiliary initialization voltage line (VL22a) may be connected to the overlapping eighth connection electrode (1570) through a contact hole. The second auxiliary initialization voltage line (VL22a) may form a mesh structure in the display area (DA) with the second initialization voltage line (VL22).

[0196] The third auxiliary initialization voltage line (VL23a) may be a wire that transmits the third initialization voltage (Vaint3). The third auxiliary initialization voltage line (VL23a) may be connected to the overlapping eighth connection electrode (1570) through a contact hole. The third auxiliary initialization voltage line (VL23a) may form a mesh structure in the display area (DA) with the third initialization voltage line (VL23).

[0197] The auxiliary reference voltage line (VL1a) may be a wire that transmits the reference voltage (Vref). The auxiliary reference voltage line (VL1a) may be connected to a fourth connecting electrode (1520) that overlaps through a contact hole. The auxiliary reference voltage line (VL1a) may form a mesh structure in the reference voltage line (VL1) and the display area (DA).

[0198] The auxiliary common voltage line (VSSL2) may be a wire that transmits the second driving voltage (ELVSS). The auxiliary common voltage line (VSSL2) may be connected to the first horizontal voltage line (VLh1) through a contact hole. The auxiliary common voltage line (VSSL2) may form a mesh structure in the display area (DA) with the first horizontal voltage line (VLh1).

[0199] FIG. 16 is a layout diagram schematically showing the arrangement of pixels and voltage lines according to one embodiment of the present invention, and FIGS. 17a and 17b are cross-sectional views schematically showing pixels and voltage lines according to one embodiment of the present invention.

[0200] Fig. 16 illustrates a fifth conductive layer (1600) on which vertical voltage lines (VLv) are arranged and a sixth conductive layer (1700) on which pixel electrodes (210r, 210g, 210b) are arranged. Fig. 17a illustrates a cross-section along line II-II' of the display device illustrated in Fig. 16, and Fig. 17b illustrates a cross-section along line III-III' of the display device illustrated in Fig. 16.

[0201] Referring to FIG. 16, FIG. 17a and FIG. 17b, a sixth insulating layer (119) may be placed on a fifth conductive layer (1600), and a sixth conductive layer (1700) may be placed on a sixth insulating layer (119).

[0202] The fifth conductive layer (1600) may include a shield line (SVL), a first auxiliary initialization voltage line (VL21a), a second auxiliary initialization voltage line (VL22a), a third auxiliary initialization voltage line (VL23a), an auxiliary reference voltage line (VL1a), an auxiliary driving voltage line (PLa), and an auxiliary common voltage line (VSSL2) arranged according to a predetermined rule.

[0203] The sixth conductive layer (1700) may include pixel electrodes (PE), auxiliary electrodes (AE), and horizontal voltage lines (VLh).

[0204] The pixel electrodes (PE) may include a first pixel electrode (210r) included in an organic light-emitting diode (OLED) of a first pixel (PXr), a second pixel electrode (210g) included in an organic light-emitting diode (OLED) of a second pixel (PXg), and a third pixel electrode (210b) included in an organic light-emitting diode (OLED) of a third pixel (PXb). The organic light-emitting diode (OLED) may further include a counter electrode (230) disposed on the pixel electrode (PE) and an intermediate layer (220) between the pixel electrode (PE) and the counter electrode (230).

[0205] A pixel definition layer (PDL) covering the edge of each pixel electrode (PE) may be disposed on the sixth conductive layer (1700). The pixel definition layer (PDL) may define a pixel aperture (OP) exposing the central portion of each pixel electrode (PE) and an auxiliary aperture (OPa) exposing the central portion of the first auxiliary electrode (AE1). The light-emitting area of ​​the organic light-emitting diode (OLED), i.e., the size and shape of each pixel, may be defined by the pixel aperture (OP).

[0206] The pixel defining layer (PDL) can prevent arcs from occurring at the edges of the pixel electrodes (PE) by increasing the distance between the edges of each pixel electrode (PE) and the counter electrode (230).

[0207] The intermediate layer (220) may include a light-emitting layer (222) formed corresponding to each of the pixel electrodes (PE). The light-emitting layer (222) may include a polymer material or a low-molecular material, and may emit red, green, blue, or white light. A first functional layer (221) and a second functional layer (223) may be disposed below and / or above the light-emitting layer (222), respectively. The first functional layer (221) may be a hole transport layer (HTL). Alternatively, the first functional layer (221) may include a hole injection layer (HIL) and a hole transport layer (HTL). The second functional layer (223) may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer (221) and the second functional layer (223) can be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0208] The counter electrode (230) may be formed of a conductive material having a relatively low work function. The counter electrode (230) may be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0209] Pixel electrodes (PE) can form rows and columns in the display area (DA). Second pixel electrodes (210g) and first pixel electrodes (210r) can be arranged in odd columns (M1, M3, ...), and third pixel electrodes (210b) can be arranged in even columns (M2, M4, ...). In the even columns (M2, M4, ...), auxiliary electrodes (AE) can be arranged between the third pixel electrodes (210b). Third pixel electrodes (210b) adjacent in the second direction (y direction) can be arranged to be spaced apart by a first distance (d1) or a second distance (d2). The first distance (d1) can be smaller than the second distance (d2). Auxiliary electrodes (AE) can be placed between third pixel electrodes (210b) spaced apart by a second distance (d2).

[0210] Auxiliary electrodes (AE) adjacent in a first direction (x direction) may be connected by horizontal voltage lines (VLh1, VLh2). The horizontal voltage lines (VLh1, VLh2) may extend only in the first direction (x direction). The auxiliary electrodes (AE) may include a first auxiliary electrode (AE1) connected to a lower vertical voltage line through a contact hole (CTm) and a second auxiliary electrode (AE2) in which a contact hole (CTm) is not formed. In one embodiment, the first auxiliary electrode (AE1) may be an auxiliary electrode overlapping an auxiliary common voltage line (VSSL2) among the auxiliary electrodes (AE).

[0211] For example, as illustrated in FIG. 17b, the first auxiliary electrode (AE1) may be connected to an auxiliary common voltage line (VSSL2) located below the first auxiliary electrode (AE1) through a contact hole (CTm) penetrating the sixth insulating layer (119). On the other hand, as illustrated in FIG. 17a, the second auxiliary electrode (AE2) may be separated from the voltage lines below it, for example, the auxiliary driving voltage line (PLa), the shielding line (SVL), and the third auxiliary initialization voltage line (VL23a), by the sixth insulating layer (119).

[0212] A pixel defining layer (PDL) can expose an upper surface of a first auxiliary electrode (AE1) through an auxiliary opening (OPa). An intermediate layer (220) is disposed on the exposed upper surface of the first auxiliary electrode (AE1), and the intermediate layer (220) can define a hole (220h) overlapping with the first auxiliary electrode (AE1). In one embodiment, the hole (220h) of the intermediate layer (220) may be formed through a laser drilling process. The counter electrode (230) can be in direct contact with the first auxiliary electrode (AE1) through the hole (220h) of the intermediate layer (220). Therefore, the counter electrode (230) can receive a second driving voltage (ELVSS) through the auxiliary common voltage line (VSSL2) and the first horizontal voltage line (VLh1). On the other hand, the pixel defining layer (PDL) can completely cover the second auxiliary electrode (AE2), and the second auxiliary electrode (AE2) does not come into contact with the counter electrode (230) due to the pixel defining layer (PDL) and the intermediate layer (220).

[0213] FIGS. 18a and 18b are schematic drawings showing voltage lines according to one embodiment of the present invention.

[0214] For convenience of explanation and illustration, FIGS. 18a and 18b illustrate twelve shield lines (SVL), two auxiliary common voltage lines (VSSL2), and five common voltage lines (VSSL1) spaced at regular intervals, but the present invention is not limited thereto. The number of lines arranged in the display area (DA) may be greater, and the spacing between the lines may also be different.

[0215] Referring to FIGS. 18a and 18b, a common voltage line (VSSL1) extending in a first direction (x direction) and a shield line (SVL) and an auxiliary common voltage line (VSSL2) extending in a second direction (y direction) may be arranged in the display area (DA). The common voltage line (VSSL1) may be the first horizontal voltage line (VLh1) illustrated in FIG. 17.

[0216] Common voltage supply lines (VSSLo) extending in the first direction (x direction) may be arranged in the peripheral area (PA) outside the display area (DA). In one embodiment, the common voltage supply lines (VSSLo) may be arranged on the upper side (+y direction side) and the lower side (-y direction side) of the peripheral area (PA) with the display area (DA) interposed therebetween. The common voltage supply lines (VSSLo) may be wirings that transmit the second driving voltage (ELVSS).

[0217] Shielding lines (SVL) are vertical voltage lines that overlap with data lines and may not be electrically connected to other wires, semiconductor patterns, or conductive patterns in the display area (DA). The shielding lines (SVL) may be connected to voltage supply lines located in the peripheral area (PA) outside the display area (DA) to receive shielding voltage.

[0218] In one embodiment, as illustrated in FIG. 18a, the shield lines (SVL) can be connected to the common voltage supply lines (VSSLo) through a contact hole (CTo1) located in the peripheral area (PA).

[0219] The auxiliary common voltage lines (VSSL2) may be connected to the common voltage supply lines (VSSLo) through the contact hole (CTo2) located in the peripheral area (PA) and may be connected to the common voltage lines (VSSL1) through the contact hole (CTm) located in the display area (DA). In the display area (DA), the auxiliary common voltage lines (VSSL2) and the common voltage lines (VSSL1) may be connected to each other to form a mesh structure. The common voltage lines (VSSL1) may be connected to the counter electrode (230) through the first auxiliary electrode (AE1) to transmit the second driving voltage (ELVSS) to the counter electrode (230). The shield line (SVL) may be separated from the common voltage line (VSSL1) in the thickness direction (z direction) by at least one insulating layer.

[0220] In one embodiment, as illustrated in FIG. 18b, the display device (10) further includes voltage supply lines (VLo) extending in a first direction (x direction) in the peripheral area (PA), and shielding lines (SVL) can be connected to the voltage supply lines (VLo) through contact holes (CTo3) located in the peripheral area (PA). The voltage supply lines (VLo) can be respectively arranged on the upper side (+y direction side) and the lower side (-y direction side) of the peripheral area (PA) with the display area (DA) interposed therebetween.

[0221] In one embodiment, the voltage supply line (VLo) may be a first driving voltage supply line that transmits a first driving voltage (ELVDD), a first initialization voltage supply line that transmits a first initialization voltage (Vaint1), a second initialization voltage supply line that transmits a second initialization voltage (Vaint2), or a third initialization voltage supply line that supplies a third initialization voltage (Vaint3). Alternatively, the voltage supply line (VLo) may be a power line that supplies a separate shielding voltage.

[0222] According to embodiments of the present invention, since the shield line (SVL) is not connected to wires extending in the first direction (x direction) within the display area (DA), the influence of changes in the data signal may not be transmitted to surrounding pixels. Accordingly, the display device may reduce or prevent multi-line horizontal crosstalk by having the shield line (SVL) overlapping the data line.

[0223] Figures 19a to 20b are cross-sectional views showing the structure of a display element according to one embodiment of the present invention.

[0224] As a display element according to one embodiment, an organic light-emitting diode (OLED) may include a pixel electrode (210), a counter electrode (230), and an intermediate layer (220m) between the pixel electrode (210) (anode) and the counter electrode (230) (cathode).

[0225] The pixel electrode (210) may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode (210) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the pixel electrode (210) may have a three-layer structure of ITO / Ag / ITO.

[0226] The counter electrode (230) may be disposed on the intermediate layer (220 m). The counter electrode (230) may include a metal, alloy, electrically conductive compound, or any combination thereof having a low work function. For example, the counter electrode (230) may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode (230) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0227] The intermediate layer (220 m) may include a polymer or low-molecular organic material that emits light of a predetermined color. In addition to various organic materials, the intermediate layer (220 m) may also include metal-containing compounds such as organometallic compounds and inorganic materials such as quantum dots.

[0228] In one embodiment, the intermediate layer (220m) may include a light-emitting layer and a first functional layer and a second functional layer below and above the light-emitting layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer or the second functional layer may be omitted. The first functional layer and the second functional layer may be formed integrally to correspond to a plurality of organic light-emitting diodes (OLEDs) included in the display area (DA).

[0229] In one embodiment, the intermediate layer (220m) may include two or more emitting units sequentially stacked between the pixel electrode (210) and the counter electrode (230), and a charge generation layer (CGL) disposed between the two emitting units. When the intermediate layer (220m) includes the emitting units and the charge generation layer, the organic light-emitting diode (OLED) may be a tandem light-emitting element. The organic light-emitting diode (OLED) may improve color purity and luminous efficiency by having a stacked structure of a plurality of emitting units.

[0230] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer above and below the light-emitting layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The light-emitting efficiency of an organic light-emitting diode (OLED), which is a tandem light-emitting device having a plurality of light-emitting layers, can be further increased by the negative charge generation layer and the positive charge generation layer.

[0231] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0232] In one embodiment, as illustrated in FIG. 19A, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1) including a first light-emitting layer (EML1) that is sequentially stacked, and a second light-emitting unit (EU2) including a second light-emitting layer (EML2). A charge generation layer (CGL) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2). For example, the organic light-emitting diode (OLED) may include a pixel electrode (211), a first light-emitting layer (EML1), a charge generation layer (CGL), a second light-emitting layer (EML2), and a counter electrode (230), which are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first light-emitting layer (EML1), respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer (EML2), respectively. The first light-emitting layer (EML1) may be a blue light-emitting layer, and the second light-emitting layer (EML2) may be a yellow light-emitting layer.

[0233] In one embodiment, as illustrated in FIG. 19b, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1) including a first light-emitting layer (EML1), a third light-emitting unit (EU3), and a second light-emitting unit (EU2) including a second light-emitting layer (EML2). A first charge generation layer (CGL1) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2), and a second charge generation layer (CGL2) may be provided between the second light-emitting unit (EU2) and the third light-emitting unit (EU3). For example, an organic light-emitting diode (OLED) may include a pixel electrode (210), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a second light-emitting layer (EML2), a second charge generation layer (CGL2), the first light-emitting layer (EML1), and a counter electrode (230) that are sequentially stacked. A first functional layer and a second functional layer may be included below and above the first light-emitting layer (EML1), respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer (EML2), respectively. The first light-emitting layer (EML1) may be a blue light-emitting layer, and the second light-emitting layer (EML2) may be a yellow light-emitting layer.

[0234] In one embodiment, the organic light emitting diode (OLED) may further include a third light emitting layer (EML3) and / or a fourth light emitting layer (EML4) that directly contacts, in addition to the second light emitting layer (EML2), the second light emitting unit (EU2) below and / or above the second light emitting layer (EML2). Here, direct contact may mean that no other layer is disposed between the second light emitting layer (EML2) and the third light emitting layer (EML3) and / or between the second light emitting layer (EML2) and the fourth light emitting layer (EML4). The third light emitting layer (EML3) may be a red light emitting layer, and the fourth light emitting layer (EML4) may be a green light emitting layer.

[0235] For example, as illustrated in FIG. 19c, the organic light-emitting diode (OLED) may include a pixel electrode (210), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a third light-emitting layer (EML3), a second light-emitting layer (EML2), a second charge generation layer (CGL2), a first light-emitting layer (EML1), and a counter electrode (230) that are sequentially stacked. Alternatively, as illustrated in FIG. 19d, the organic light-emitting diode (OLED) may include a pixel electrode (210), a first light-emitting layer (EML1), a first charge generation layer (CGL1), a third light-emitting layer (EML3), a second light-emitting layer (EML2), a fourth light-emitting layer (EML4), a second charge generation layer (CGL2), a first light-emitting layer (EML1), and a counter electrode (230) that are sequentially stacked.

[0236] Fig. 20a is a cross-sectional view showing an example of the organic light-emitting diode of Fig. 19c, and Fig. 20b is a cross-sectional view showing an example of the organic light-emitting diode of Fig. 19d.

[0237] Referring to FIG. 20A, an organic light-emitting diode (OLED) may include a first light-emitting unit (EU1), a second light-emitting unit (EU2), and a third light-emitting unit (EU3) that are sequentially stacked. A first charge generation layer (CGL1) may be provided between the first light-emitting unit (EU1) and the second light-emitting unit (EU2), and a second charge generation layer (CGL2) may be provided between the second light-emitting unit (EU2) and the third light-emitting unit (EU3). The first charge generation layer (CGL1) and the second charge generation layer (CGL2) may each include a negative charge generation layer (nCGL) and a positive charge generation layer (pCGL).

[0238] The first light-emitting unit (EU1) may include a blue light-emitting layer (BEML). The first light-emitting unit (EU1) may further include a hole injection layer (HIL) and a hole transport layer (HTL) between the pixel electrode (211) and the blue light-emitting layer (BEML). In one embodiment, a p-doped layer may further be included between the hole injection layer (HIL) and the hole transport layer (HTL). The p-doped layer may be formed by doping the hole injection layer (HIL) with a p-type doping material. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer (BEML) and the hole transport layer (HTL). The blue light auxiliary layer may increase the light output efficiency of the blue light-emitting layer (BEML). The blue light auxiliary layer may increase the light output efficiency of the blue light-emitting layer (BEML) by controlling a hole charge balance. The electron blocking layer may prevent electron injection into the hole transport layer (HTL). The buffer layer can compensate for the resonance distance according to the wavelength of light emitted from the light-emitting layer.

[0239] The second light-emitting unit (EU2) may include a yellow light-emitting layer (YEML) and a red light-emitting layer (REML) directly in contact with the yellow light-emitting layer (YEML) under the yellow light-emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and may further include an electron transport layer (ETL) between the yellow light-emitting layer (YEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0240] The third light-emitting unit (EU3) may include a blue light-emitting layer (BEML). The third light-emitting unit (EU3) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the second charge generation layer (CGL2) and the blue light-emitting layer (BEML). The third light-emitting unit (EU3) may further include an electron transport layer (ETL) and an electron injection layer (EIL) between the blue light-emitting layer (BEML) and the counter electrode (230). The electron transport layer (ETL) may be a single layer or a multilayer. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer (BEML) and the hole transport layer (HTL). At least one of a hole blocking layer and a buffer layer may further be included between the blue light-emitting layer (BEML) and the electron transport layer (ETL). The hole blocking layer may prevent hole injection into the electron transport layer (ETL).

[0241] The organic light emitting diode (OLED) illustrated in FIG. 20b differs from the organic light emitting diode (OLED) illustrated in FIG. 20a in the stacked structure of the second light emitting unit (EU2), but otherwise has the same configuration. Referring to FIG. 20b, the second light emitting unit (EU2) may include a yellow light emitting layer (YEML), a red light emitting layer (REML) located below the yellow light emitting layer (YEML) and in direct contact with the yellow light emitting layer (YEML), and a green light emitting layer (GEML) located above the yellow light emitting layer (YEML) and in direct contact with the yellow light emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and may further include an electron transport layer (ETL) between the green light-emitting layer (GEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0242] Fig. 21 is a cross-sectional view showing the structure of a pixel of a display device according to one embodiment of the present invention.

[0243] Referring to FIG. 21, a display device may include a plurality of pixels. The plurality of pixels may include a first pixel (PXr), a second pixel (PXg), and a third pixel (PXb). The first pixel (PXr), the second pixel (PXg), and the third pixel (PXb) may each include a pixel electrode (210), a counter electrode (230), and an intermediate layer (220m). In one embodiment, the first pixel (PXr) may be a red pixel, the second pixel (PXg) may be a green pixel, and the third pixel (PXb) may be a blue pixel. Here, the pixel includes an organic light-emitting diode (OLED) as a display element, and the organic light-emitting diode (OLED) of each pixel may be electrically connected to a corresponding pixel circuit.

[0244] The pixel electrode (210) can be independently provided for each of the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb).

[0245] The middle layer (220m) of the organic light-emitting diode (OLED) of each of the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb) may include a first light-emitting unit (EU1), a second light-emitting unit (EU2) that are sequentially stacked, and a charge generation layer (CGL) between the first light-emitting unit (EU1) and the second light-emitting unit (EU2). The charge generation layer (CGL) may include a negative charge generation layer (nCGL) and a positive charge generation layer (pCGL). The charge generation layer (CGL) may be a common layer that is formed continuously in the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb).

[0246] The first light-emitting unit (EU1) of the first pixel (PXr) may include a hole injection layer (HIL), a hole transport layer (HTL), a red emission layer (REML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (210). The first light-emitting unit (EU1) of the second pixel (PXg) may include a hole injection layer (HIL), a hole transport layer (HTL), a green emission layer (GEML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (210). The first light-emitting unit (EU1) of the third pixel (PXb) may include a hole injection layer (HIL), a hole transport layer (HTL), a blue emission layer (BEML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (210). Each of the hole injection layer (HIL), hole transport layer (HTL) and electron transport layer (ETL) of the first light-emitting units (EU1) may be a common layer formed continuously in the first pixel (PXr), the second pixel (PXg) and the third pixel (PXb).

[0247] The second light-emitting unit (EU2) of the first pixel (PXr) may include a hole transport layer (HTL), an auxiliary layer (AXL), a red light-emitting layer (REML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). The second light-emitting unit (EU2) of the second pixel (PXg) may include a hole transport layer (HTL), a green light-emitting layer (GEML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). The second light-emitting unit (EU2) of the third pixel (PXb) may include a hole transport layer (HTL), a blue light-emitting layer (BEML), and an electron transport layer (ETL) sequentially stacked on a charge generation layer (CGL). Each of the hole transport layer (HTL) and electron transport layer (ETL) of the second light-emitting units (EU2) may be a common layer formed continuously in the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb). In one embodiment, at least one of a hole blocking layer and a buffer layer may be further included between the light-emitting layer and the electron transport layer (ETL) in the second light-emitting units (EU2) of the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb).

[0248] The thickness (H1) of the red emitting layer (REML), the thickness (H2) of the green emitting layer (GEML), and the thickness (H3) of the blue emitting layer (BEML) can be determined according to the resonance distance. The auxiliary layer (AXL) is a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer (AXL) may include the same material as the hole transport layer (HTL).

[0249] In Fig. 21, the auxiliary layer (AXL) is provided only in the first pixel (PXr), but the embodiment of the present invention is not limited thereto. For example, the auxiliary layer (AXL) may be provided in at least one of the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb) in order to match the resonance distances of each of the first pixel (PXr), the second pixel (PXg), and the third pixel (PXb).

[0250] The display device may further include a capping layer (240) disposed on the outer side of the counter electrode (230). The capping layer (240) may serve to improve luminous efficiency by the principle of constructive interference. As a result, the light extraction efficiency of the organic light-emitting diode (OLED) may be increased, thereby improving the luminous efficiency of the organic light-emitting diode (OLED).

[0251] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. In a display device including pixels arranged in a display area, A first conductive layer including a first voltage line; A second conductive layer including a first conductive pattern disposed on the first conductive layer and overlapping the first voltage line; A semiconductor layer including a first semiconductor pattern disposed on the second conductive layer and overlapping the first conductive pattern; A third conductive layer disposed on the semiconductor layer and including a second conductive pattern overlapping the first conductive pattern; and A fourth conductive layer including a third conductive pattern and a data line, which is disposed on the third conductive layer and overlaps the second conductive pattern; A display device, wherein the first voltage line includes a body portion extending in a first direction and a shield portion extending in a second direction intersecting the first direction from the body portion so as to overlap the data line.

2. In paragraph 1, The third conductive layer further includes a first connecting electrode, The fourth conductive layer further includes a second connecting electrode, A display device, wherein the above shielding portion is connected to the first semiconductor pattern through the first connection electrode and the second connection electrode.

3. In paragraph 1, A display device, wherein the shielding portion is spaced apart from the first semiconductor pattern on a plane.

4. In paragraph 1, The above first conductive layer further includes a fourth conductive pattern overlapping the above second conductive pattern, A display device, wherein the second challenge pattern is connected to the fourth challenge pattern, and the first challenge pattern is connected to the third challenge pattern.

5. In paragraph 1, The above data lines include a first data line, a second data line, and a third data line, The above shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line. A display device wherein the areas of the first shielding section, the second shielding section, and the third shielding section are the same.

6. In paragraph 1, The above data lines include a first data line, a second data line, and a third data line, The above shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line. A display device, wherein the area of ​​the first shielding portion is different from the area of ​​the second shielding portion and the area of ​​the third shielding portion.

7. In paragraph 6, The above pixels include a red pixel emitting red light, a blue pixel emitting blue light, and a green pixel emitting green light, A display device, wherein the first data line is connected to the red pixel.

8. In paragraph 1, The above first conductive layer further includes a second voltage line extending in the first direction, A display device, wherein the semiconductor layer further includes a second semiconductor pattern connected between the data line and the second voltage line.

9. In paragraph 8, The third conductive layer further includes a first gate line overlapping the first semiconductor pattern and transmitting the first gate signal and a second gate line overlapping the second semiconductor pattern and transmitting the second gate signal. The above pixel operates in a non-emitting section and an emitting section during one frame period, A display device, wherein, in the non-light-emitting section, after the on voltage is supplied to the second gate signal, the on voltage is supplied to the first gate signal, and after the off voltage is supplied to the second gate signal, the off voltage is supplied to the first gate signal.

10. In paragraph 9, A display device in which a reference voltage is transmitted from the second voltage line to the second conductive pattern when the second gate signal is at an on voltage.

11. In paragraph 1, A display device further comprising a fifth conductive layer disposed on the fourth conductive layer, including a third voltage line extending in the second direction and overlapping the data line.

12. In paragraph 11, Further comprising a voltage supply line disposed in a peripheral area outside the above display area and extending in the first direction; A display device, wherein the third voltage line is connected to the voltage supply line in the peripheral area across the display area.

13. In paragraph 12, The above pixel includes a display element including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, A display device in which the voltage supplied to the third voltage line and the voltage supplied to the counter electrode are the same.

14. In paragraph 12, The above pixel includes a display element including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, A display device in which the voltage supplied to the third voltage line and the voltage supplied to the counter electrode are different.

15. In paragraph 1, A fifth conductive layer disposed on the fourth conductive layer and including a fourth voltage line extending in the second direction; and A display device further comprising: a sixth conductive layer disposed on the fifth conductive layer, the sixth conductive layer including pixel electrodes, auxiliary electrodes, and fifth voltage lines extending in the first direction and connecting adjacent auxiliary electrodes among the auxiliary electrodes.

16. In paragraph 15, Further comprising a pixel definition film disposed on the sixth challenging layer and defining pixel apertures and auxiliary apertures; The above pixel apertures overlap each of the above pixel electrodes, A display device in which the above auxiliary openings overlap each of the auxiliary electrodes that overlap the fourth voltage line among the above auxiliary electrodes.

17. Including a first pixel circuit connected to a first light-emitting diode and a second pixel circuit connected to a second light-emitting diode; Each of the above first pixel circuit and the above second pixel circuit, A first voltage line extending in the first direction; A data line disposed on the first voltage line and extending in a second direction intersecting the first direction; A capacitor including a first capacitor electrode and a second capacitor electrode disposed on the first capacitor electrode; A first transistor connected between the first voltage line and the capacitor; A second transistor connected to the data line and the gate electrode of the first transistor; A second voltage line extending in the first direction and a third transistor connected to the gate electrode of the first transistor; and A fourth transistor connected between the first voltage line and the first transistor; A display device, wherein the first voltage line includes a shield extending in the second direction from the body part so as to overlap the body part and the data line.

18. In paragraph 17, A display device, wherein the area of ​​the shielding portion of the first pixel circuit is smaller than the area of ​​the shielding portion of the second pixel circuit.

19. In paragraph 18, A display device, wherein the first light-emitting diode emits red light.

20. In paragraph 17, A display device wherein the first voltage line and the second voltage line are arranged on the same layer.

21. In paragraph 17, A frame includes a non-luminous period and a luminous period, The above non-luminous section is, A first section in which the third transistor and the fourth transistor are turned on before a writing section in which a data signal is supplied from the data line; and A display device, comprising: a second section in which the fourth transistor remains turned on after the third transistor is turned off.

22. In paragraph 17, Each of the first light-emitting diode and the second light-emitting diode includes a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode, Auxiliary electrodes positioned on the same layer as the pixel electrode; and A display device further comprising a third voltage line connecting the auxiliary electrodes and extending in the first direction.

23. In paragraph 22, Further comprising a fourth voltage line disposed between the data line and the pixel electrode and extending in the second direction; A display device, wherein among the above auxiliary electrodes, the auxiliary electrode overlapping the fourth voltage line is connected to the third voltage line.

24. In paragraph 23, A display device in which the auxiliary electrode overlapping the fourth voltage line is in direct contact with the counter electrode.

25. In paragraph 23, Further comprising a fifth voltage line located on the same layer as the fourth voltage line and overlapping the data line; A display device, wherein the fifth voltage line is separated from the third voltage line by at least one insulating layer.

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