Display devices and methods for manufacturing these display devices.

Abstract

The invention relates to a display device comprising: a substrate; a first transistor arranged on the substrate, and comprising a first active layer comprising a first part comprising a first channel region, and a second and third part set apart with the first part placed between them, and a first gate electrode arranged on the first part of the first active layer; at least one first dummy gate electrode arranged on a part of the second and / or third part of the first active layer, and separate from the first gate electrode; and a first gate isolation layer arranged between the first active layer and each of the first gate electrodes and at least one first dummy gate electrode.

Description

Display device and method for manufacturing the same

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

[0002] Display devices are becoming increasingly important with the development of multimedia. In response, various display devices, such as liquid crystal displays (LCDs) and light-emitting display devices (LEDs), are being developed.

[0003] The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that can uniformize the operating characteristics of a transistor and improve image quality.

[0004] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment may include: a substrate; a first transistor including a first active layer disposed on the substrate, the first active layer including a first portion including a first channel region and a second portion and a third portion spaced apart from each other with the first portion interposed therebetween; and a first gate electrode disposed on the first portion of the first active layer; at least one first dummy gate electrode disposed on at least one portion of the second portion and the third portion of the first active layer, the first dummy gate electrode being separated from the first gate electrode; and a first gate insulating layer disposed between each of the first gate electrode and the at least one first dummy gate electrode and the first active layer.

[0006] In one embodiment, the first gate insulating layer includes an insulating pattern disposed between the first active layer and the first gate electrode, and may expose a portion of each of the second portion and the third portion of the first active layer.

[0007] In one embodiment, the first gate insulating layer may further include at least one insulating pattern disposed between the at least one first dummy gate electrode and the first active layer.

[0008] In one embodiment, the first active layer further includes a first source region located in the second portion and located on one side of the first channel region, and a first drain region located in the third portion and located on the other side of the first channel region, wherein the first gate electrode covers at least the first channel region and can overlap a portion of the first source region and the first drain region by a section corresponding to a first length in the longitudinal direction of the first active layer.

[0009] In one embodiment, the first dummy gate electrode may have a length less than or equal to the first length in the longitudinal direction of the first active layer.

[0010] In one embodiment, the first dummy gate electrode has a length longer than the first length in the longitudinal direction of the first active layer, and the first active layer may further include at least one dummy channel region positioned in at least one of the second portion and the third portion and overlapping with the first dummy gate electrode.

[0011] In one embodiment, the first dummy gate electrode may cover the dummy channel region and overlap a portion of the first source region or the first drain region around the dummy channel region.

[0012] In one embodiment, the dummy channel region may have a short channel having a length that falls within a threshold voltage roll-off region of a dummy transistor including the first dummy gate electrode and the dummy channel region.

[0013] In one embodiment, the display device includes a pixel including a plurality of pixel transistors including the first transistor, and the dummy channel region may have a length shorter than a length of a channel region of each of the plurality of pixel transistors.

[0014] In one embodiment, the display device further includes an interlayer insulating layer disposed on the substrate and covering the first active layer, the first gate insulating layer, the first gate electrode, and the at least one dummy gate electrode, and the first transistor may further include at least one of a first source electrode disposed on the interlayer insulating layer and electrically connected to the first source region, and a first drain electrode disposed on the interlayer insulating layer and electrically connected to the first drain region.

[0015] In one embodiment, the display device may further include a power line electrically connected to the first dummy gate electrode and to which a gate-on voltage of the first transistor is applied.

[0016] In one embodiment, the display device includes a pixel circuit including the first transistor and a pixel including a light-emitting element connected to the pixel circuit, wherein the first transistor may be a driving transistor that controls a driving current flowing to the light-emitting element in response to a voltage applied to the first gate electrode.

[0017] In one embodiment, the at least one first dummy gate electrode may include a plurality of first dummy gate electrodes positioned on both sides of the first gate electrode and disposed on top of each of the second portion and the third portion of the first active layer.

[0018] In one embodiment, the pixel circuit further includes a second transistor electrically connected to the first gate electrode, the second transistor including a second active layer disposed on the substrate, the second active layer including a first portion including a second channel region, a second portion located on one side of the second channel region and including a second source region, and a third portion located on the other side of the second channel region and including a second drain region; and a second gate electrode disposed on the first portion of the second active layer.

[0019] In one embodiment, the pixel may further include at least one second dummy gate electrode disposed on at least one portion of the second portion and the third portion of the second active layer and spaced apart from the second gate electrode; and a second gate insulating layer including insulating patterns disposed between each of the second gate electrode and the at least one second dummy gate electrode and the second active layer.

[0020] In one embodiment, the second gate insulating layer exposes a portion of each of the second portion and the third portion of the second active layer, and the second gate electrode covers at least the second channel region and overlaps a portion of each of the second source region and the second drain region around the second channel region.

[0021] In one embodiment, the at least one second dummy gate electrode may include a plurality of second dummy gate electrodes positioned on both sides of the second gate electrode and disposed on top of each of the second portion and the third portion of the second active layer.

[0022] In one embodiment, the second source region is electrically connected to the first gate electrode, and the pixel may include a single second dummy gate electrode disposed only on the second portion of the second active layer.

[0023] In one embodiment, the first active layer and the second active layer may include an oxide semiconductor.

[0024] A method for manufacturing a display device according to one embodiment may include: forming an active layer including an oxide semiconductor on a substrate; forming a gate insulating layer covering the active layer on the substrate; forming a gate electrode and at least one dummy gate electrode on the gate insulating layer, the gate electrode and at least one dummy gate electrode overlapping and separated from different portions of the active layer; forming insulating patterns under each of the gate electrode and the at least one dummy gate electrode by etching the gate insulating layer, and exposing a portion of the active layer that does not overlap with the gate electrode and the at least one dummy gate electrode; and forming an interlayer insulating layer covering the active layer, the insulating patterns, the gate electrode, and the at least one dummy gate electrode.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] A display device according to embodiments includes a transistor including an active layer and a gate electrode disposed on a portion of the active layer, a dummy gate electrode disposed on the active layer and separated from the gate electrode, and a gate insulating layer disposed between each of the gate electrode and the dummy gate electrode and the active layer. A method of manufacturing a display device according to embodiments includes steps of forming the active layer, the gate electrode, the dummy gate electrode, and the gate insulating layer.

[0027] According to the display device and the manufacturing method thereof according to the embodiments, the amount of diffusion of oxygen vacancies into a portion of an active layer located under a gate electrode during the manufacturing process of the display device and / or the length of a region into which oxygen vacancies diffuse under the gate electrode can be reduced. Accordingly, the overlapping area between the source and / or drain regions of the transistor and the gate electrode can be reduced, and the parasitic capacitance of the transistor can be reduced. As a result, the operating characteristics of the transistor can be uniformized and / or stabilized.

[0028] In some embodiments, the transistor may be a driving transistor of the pixel or a switching transistor connected to a gate electrode of the driving transistor. In some embodiments, at least one dummy gate electrode may be formed on each of the active layers of the driving transistor of the pixel and at least one switching transistor. According to embodiments, image staining due to luminance deviation of pixels, etc. may be prevented, reduced, or minimized, and the picture quality of the display device may be improved.

[0029] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0030] FIG. 1 is a plan view showing a display device according to one embodiment.

[0031] Figure 2 is a plan view showing the display panel of Figure 1.

[0032] Figure 3 is an equivalent circuit diagram showing a pixel according to one embodiment.

[0033] Figure 4 is an equivalent circuit diagram showing a pixel according to one embodiment.

[0034] FIG. 5 is a plan view showing a pixel transistor and a dummy gate electrode according to one embodiment.

[0035] FIG. 6 is a cross-sectional view showing a display panel according to one embodiment.

[0036] Fig. 7 is a cross-sectional view showing a display panel according to one embodiment.

[0037] FIG. 8 is a plan view showing a pixel transistor and a dummy gate electrode according to one embodiment.

[0038] Fig. 9 is a cross-sectional view showing a display panel according to one embodiment.

[0039] Fig. 10 is a cross-sectional view showing a display panel according to one embodiment.

[0040] FIGS. 11 to 18 are cross-sectional views showing a method of manufacturing a display device according to one embodiment.

[0041] Fig. 19 is a cross-sectional view showing a display panel according to one embodiment.

[0042] FIG. 20 is a cross-sectional view showing a display panel according to one embodiment.

[0043] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0044] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0045] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0046] Specific embodiments are described below with reference to the attached drawings.

[0047] Fig. 1 is a plan view showing a display device (100) according to one embodiment. Fig. 2 is a plan view showing a display panel (110) of Fig. 1.

[0048] Referring to FIGS. 1 and 2, the display device (100) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs), as well as televisions, laptops, monitors, billboards, and Internet of Things (IOT). These are presented only as examples, and the display device (100) can also be employed in other electronic devices.

[0049] In one embodiment, the display device (100) may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using an ultra-small light-emitting diode such as a micro or nano light emitting diode (micro LED or nano LED), but is not limited thereto. For example, the display device (100) may be a type of display device other than a light-emitting display device. Hereinafter, embodiments in which the display device (100) is an organic light-emitting display device are disclosed.

[0050] The display device (100) may include a display panel (110) including pixels (PX), and a first driving unit (120) and a second driving unit (130) that supply driving signals to the pixels (PX). The display device (100) may further include additional components. For example, the display device (100) may further include a power supply unit for supplying power voltages to the pixels (PX), the first driving unit (120) and the second driving unit (130), and a timing control unit for controlling the operations of the first driving unit (120) and the second driving unit (130).

[0051] The display panel (110) may include a display area (DA) and a non-display area (NDA) (also referred to as a "bezel area"). The display area (DA) may be an area that displays an image by including pixels (PX). The non-display area (NDA) is an area excluding the display area (DA), and an image may not be displayed in the non-display area (NDA). In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0052] In FIGS. 1 and 2, a first direction (D1), a second direction (D2), and a third direction (D3) are defined. In one embodiment, the first direction (D1) and the second direction (D2) may be perpendicular to each other, the first direction (D1) and the third direction (D3) may be perpendicular to each other, and the second direction (D2) and the third direction (D3) may be perpendicular to each other. For example, the first direction (D1) may be a horizontal direction (e.g., a row direction or X direction) of the display panel (110), the second direction (D2) may be a vertical direction (e.g., a column direction or Y direction) of the display panel (110), and the third direction (D3) may be a thickness direction (e.g., a height direction or Z direction) of the display panel (110).

[0053] In one embodiment, the display panel (110) may be formed in a rectangular shape on a plane. For example, the display panel (110) may include two first sides extending in a first direction (D1) and two second sides extending in a second direction (D2) intersecting the first direction (D1). In FIGS. 1 and 2 , the display panel (110) is illustrated in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel (110) is not limited thereto. For example, the display panel (110) may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or may have a shape in which the lengths of the first side and the second side are substantially the same.

[0054] In one embodiment, the display panel (110) may include, but is not limited to, an angled corner where the first side and the second side meet. For example, the display panel (110) may also include a rounded corner where the first side and the second side meet.

[0055] The planar shape of the display panel (110) is not limited to the rectangular shape illustrated, and may be applied in other shapes. For example, the display panel (110) may have a planar square shape, a non-square polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes.

[0056] In one embodiment, the display panel (110) may be substantially flat on a plane defined by the first direction (D1) and the second direction (D2), and may have a uniform thickness in the third direction (D3). In another embodiment, the display panel (110) may be provided in a three-dimensional shape having a curved surface, etc.

[0057] The display panel (110) may be provided as a panel having rigid characteristics so as not to be substantially deformed, or may be provided as a panel having flexible characteristics so as to be deformed in a form such as by folding, bending, or rolling at least in one portion. The display panel (110) may be provided to the display device (100) in an unbent state, or may be provided to the display device (100) in a bent state in some sections.

[0058] A display panel (110) may include a substrate (SUB) and pixels (PX) arranged on the substrate (SUB). The pixels (PX) may be arranged in a display area (DA) on the substrate (SUB).

[0059] The substrate (SUB) is a base member for manufacturing or providing a display panel (110) and may constitute a base surface of the display panel (110). The substrate (SUB) may include a display area (DA) and a non-display area (NDA) located around the display area (DA).

[0060] The display area (DA) may have various shapes depending on the embodiments. For example, the display area (DA) may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes. In one embodiment, the display area (DA) may have a shape that matches the shape of the display panel (110), but is not limited thereto.

[0061] The display area (DA) may include pixel areas in which pixels (PX) are provided and / or arranged. For example, each pixel (PX) may be arranged in a respective pixel area located in the display area (DA). In one embodiment, the display device (100) may be a light-emitting display device, and each pixel (PX) may include a light-emitting element located in each light-emitting area and a pixel circuit connected to the light-emitting element. In describing the embodiments, the term “connection” may include the meaning of an electrical connection and / or a physical connection. In addition, unless “direct connection” and “indirect connection” are specifically defined, the term “connection” may include both the meaning of a “direct connection” and an “indirect connection.”

[0062] Each pixel area may include a light-emitting area where the light-emitting element of the corresponding pixel is located and the pixel emits light, and a pixel circuit area where circuit elements constituting the pixel circuit of the corresponding pixel are located. The light-emitting area and the pixel circuit area of ​​each pixel (PX) may overlap each other, but are not limited thereto.

[0063] Pixels (PX) can be arranged in a display area (DA). The arrangement of pixels (PX) can vary depending on the embodiments.

[0064] The non-display area (NDA) may include a pad area (PA) on which pads (PD) are arranged, and may optionally further include a driving circuit area located at least on one side of the display area (DA). At least one driving unit, pads (PD), and / or wiring, etc. may be arranged in the non-display area (NDA).

[0065] At least one driving unit, or a portion of the driving unit, for driving pixels (PX) may be disposed in the driving circuit area. For example, circuit elements constituting the first driving unit (120) may be disposed in the driving circuit area on the substrate (SUB). In one embodiment, the circuit elements of the first driving unit (120) may be formed on the display panel (110) together with the pixels (PX).

[0066] Pads (PD) may be arranged in the pad area (PA). At least one circuit board (140) may be arranged and / or bonded on the pad area (PA). In one embodiment, a plurality of circuit boards (140) connected to different pads (PD) may be arranged on the pad area (PA). The pads (PD) may include signal pads and power pads for transmitting driving signals and power voltages required for driving the pixels (PX) and / or the first driving unit (120) to the inside of the display panel (110).

[0067] The first driving unit (120) and the second driving unit (130) can generate driving signals for controlling the operation timing and brightness of the pixels (PX) and supply the driving signals to the pixels (PX). For example, the first driving unit (120) can be a gate driving unit including a scan driving unit and can be connected to the pixels (PX) through respective gate lines. The first driving unit (120) can supply respective gate signals (for example, driving signals for controlling the operation timing of the pixels (PX)) to the pixels (PX). The second driving unit (130) can be a data driving unit including source driving circuits and can be connected to the pixels (PX) through respective data lines. The second driving unit (130) can supply respective data signals to the pixels (PX).

[0068] In one embodiment, at least one of the first driving unit (120) and the second driving unit (130) (or a portion of the at least one driving unit) may be built into the display panel (110). For example, the first driving unit (120) may be disposed on the substrate (SUB) of the display panel (110) and may be disposed and / or formed in the non-display area (NDA).

[0069] In FIG. 1, the first driving unit (120) is exemplified as being formed on one side of the display area (DA) (for example, the non-display area (NDA) on the right side of the display area (DA), but the embodiments are not limited thereto. For example, the first driving unit (120) may be positioned only on the other side of the display area (DA) (for example, the non-display area (NDA) on the left side of the display area (DA)) or on both sides of the display area (DA) (for example, the non-display areas (NDA) on the left and right sides of the display area (DA). Alternatively, a part of the first driving unit (120) may be positioned in the non-display area (NDA), and another part of the first driving unit (120) may be positioned in a non-emitting area (for example, an area between the emitting areas of the pixels (PX)) within the display area (DA).

[0070] In one embodiment, one of the first driving unit (120) and the second driving unit (130) (or a portion of the other driving unit) may be disposed or formed outside the display panel (110) and electrically connected to the display panel (110). For example, the second driving unit (130) may be implemented with a plurality of integrated circuit chips and may be disposed on circuit boards (140) electrically connected to the pixels (PX) of the display panel (110). Alternatively, the second driving unit (130) may be implemented with at least one integrated circuit chip and mounted on a non-display area (NDA) of the display panel (110).

[0071] The circuit board (140) may be connected to the display panel (110) via pads (PD). In one embodiment, the circuit board (140) may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but is not limited thereto. The circuit board (140) may be connected to a timing control unit and / or a power supply unit via another circuit board or a connector, etc.

[0072] Fig. 3 is an equivalent circuit diagram showing a pixel (PX) according to one embodiment. The pixel (PX) of Fig. 3 is presented as only one embodiment, and the structure and type of the pixel (PX) may be varied in various ways depending on the embodiments.

[0073] In addition to FIGS. 1 and 2, referring to FIG. 3, a pixel (PX) may include a light-emitting element (ED) and a pixel circuit (PC) connected (for example, electrically connected) to the light-emitting element (ED). The light-emitting element (ED) is a light source of the pixel (PX), and may be, for example, an organic light-emitting diode, but is not limited thereto. The pixel circuit (PC) may control the light-emitting timing and brightness of the light-emitting element (ED).

[0074] The pixel circuit (PC) may include pixel transistors (Tpx) and at least one pixel capacitor (Cpx). For example, the pixel circuit (PC) may include first to fifth transistors (T1 to T5), and first and second capacitors (C1, C2). The structure of the pixel circuit (PC) or the types of circuit elements constituting the pixel circuit (PC) may vary depending on embodiments. Although FIG. 3 illustrates an embodiment in which all pixel transistors (Tpx) are N-type transistors, the types of pixel transistors (Tpx) are not limited thereto. For example, at least one pixel transistor (Tpx) may be formed as a P-type transistor.

[0075] The pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to driving signals supplied from the first driving unit (120) and the second driving unit (130). For example, the pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to each of the gate signals (GS) supplied from the first driving unit (120) through each of the gate lines (GL) and the data signal (DATA) supplied from the second driving unit (130) through the data line (DL).

[0076] The first transistor (T1) may be a driving transistor of a pixel (PX), in which the magnitude of a drain-source current (e.g., a driving current (Id)) is determined according to a gate-source voltage. The second, third, fourth, and fifth transistors (T2, T3, T4, T5) may be switching transistors that are turned on or off according to their respective gate-source voltages. Depending on the type (e.g., a P-type or N-type transistor) and / or operating conditions of each of the first to fifth transistors (T1 to T5), the first electrode of each of the first to fifth transistors (T1 to T5) may be a drain electrode (or a drain region) or a source electrode (or a source region), and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode may be a source electrode.

[0077] A pixel (PX) may be connected to a first gate line (GWL) that transmits a first gate signal (GW) (e.g., a scan signal), a second gate line (GIL) that transmits a second gate signal (GIN), a third gate line (GRL) that transmits a third gate signal (GR), an emission control line (ECL) that transmits an emission control signal (EM), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel (PX) may be connected to a first power line (VDL) that transmits a first pixel voltage (ELVDD) (also referred to as a “first pixel power voltage”), and a second power line (VSL) that transmits a second pixel voltage (ELVSS) (also referred to as a “second pixel power voltage”). In one embodiment, the pixel (PX) may be further connected to an initialization power line (VIL) that carries an initialization voltage (VINT) (also referred to as a "third pixel power voltage") and a reference power line (VRL) that carries a reference voltage (VREF) (also referred to as a "fourth pixel power voltage").

[0078] In one embodiment, the first to fifth transistors (T1 to T5) may be positioned in respective pixel regions and may be oxide transistors (also referred to as “oxide semiconductor transistors”) including an oxide semiconductor (e.g., an oxide semiconductor material). For example, an active layer including a channel region of each of the first to fifth transistors (T1 to T5) may be formed of an oxide semiconductor. However, the embodiments are not limited thereto. For example, at least one pixel transistor (Tpx) may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polysilicon).

[0079] Oxide semiconductors have high carrier mobility and low leakage current, and thus, even if the driving time of the oxide transistor is long, a large voltage drop may not occur. For example, in the case of a pixel (PX) including an oxide transistor, since the brightness and / or color of the image does not change significantly due to the voltage drop even when driven at a low frequency, the pixel (PX) can be driven at a low frequency. In the case of a display device (100) in which the first to fifth transistors (T1 to T5) include an oxide semiconductor, the leakage current of the pixel (PX) can be reduced or prevented and power consumption can be reduced.

[0080] Oxide semiconductors are sensitive to light, and thus their current and other characteristics may vary depending on external light. In one embodiment, a light-blocking pattern or a lower electrode (e.g., a bottom gate electrode) may be disposed below the active layer included in at least one pixel transistor (Tpx) to block external light. Accordingly, the operating characteristics of the pixel transistor (Tpx) may be stabilized.

[0081] A first transistor (T1) (also referred to as a “first pixel transistor”) may include a gate electrode connected to a first node (N1), a first electrode (e.g., a drain electrode) connected to a second node (N2), and a second electrode (e.g., a source electrode) connected to a third node (N3). The first electrode of the first transistor (T1) may be connected to a first power line (VDL) via a fifth transistor (T5), and the second electrode may be connected to a light-emitting element (ED). The first transistor (T1) may function as a driving transistor of the pixel (PX) and may control the size (e.g., the amount of current) of a driving current (Id) flowing to the light-emitting element (ED) in response to a data signal (DATA) transmitted to the first node (N1).

[0082] In one embodiment, the first transistor (T1) may further include a bottom gate electrode (BG) (for example, a back-gate electrode of the first transistor (T1)) connected to a third node (N3). By connecting the bottom gate electrode (BG) of the first transistor (T1) to the third node (N3), the first transistor (T1) is formed into a double-gate structured transistor (for example, a double-gate transistor having a source-sync structure), the operating characteristics of the first transistor (T1) can be improved.

[0083] A second transistor (T2) (also referred to as a “second pixel transistor”) may include a gate electrode connected to a first gate line (GWL), a first electrode connected to a data line (DL), and a second electrode connected to a first node (N1). The second transistor (T2) may be turned on by a first gate signal (GW) transmitted to the first gate line (GWL) (for example, a first gate signal (GW) of a gate-on voltage) to connect the data line (DL) and the first node (N1). Accordingly, a data signal (DATA) transmitted to the data line (DL) may be transmitted to the first node (N1).

[0084] A third transistor (T3) (also referred to as a “third pixel transistor”) may include a gate electrode connected to a third gate line (GRL), a first electrode connected to a reference power line (VRL), and a second electrode connected to a first node (N1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit a reference voltage (VREF) transmitted to the reference power line (VRL) to the first node (N1).

[0085] A fourth transistor (T4) (also referred to as a “fourth pixel transistor”) may include a gate electrode connected to a second gate line (GIL), a first electrode connected to a third node (N3), and a second electrode connected to an initialization power line (VIL). The fourth transistor (T4) may be turned on by a second gate signal (GIN) transmitted to the second gate line (GIL) and may transmit an initialization voltage (VINT) transmitted to the initialization power line (VIL) to the third node (N3).

[0086] A fifth transistor (T5) (also referred to as a “fifth pixel transistor”) may include a gate electrode connected to a light emission control line (ECL), a first electrode connected to a first power supply line (VDL), and a second electrode connected to a second node (or the first electrode of the first transistor (T1)). The fifth transistor (T5) may be turned on by a light emission control signal (EM) transmitted to the light emission control line (ECL) (for example, a light emission control signal (EM) of a gate-on voltage), thereby controlling a light emission timing of the pixel (PX).

[0087] The first capacitor (C1) may be connected between the first node (N1) and the third node (N3). For example, the first capacitor (C1) may be connected between the gate electrode and the second electrode of the first transistor (T1). The first capacitor (C1) serves as a storage capacitor of the pixel (PX) and may store a voltage corresponding to the threshold voltage of the first transistor (T1) and a data signal (DATA) (e.g., a data voltage).

[0088] A second capacitor (C2) may be connected between the first power line (VDL) and the third node (N3). In one embodiment, the capacitance of the second capacitor (C2) may be smaller than the capacitance of the first capacitor (C1).

[0089] The light emitting element (ED) may be connected between the third node (N3) and the second power line (VSL). For example, the light emitting element (ED) may include a first electrode (e.g., an anode electrode) connected to the third node (N3), a second electrode (e.g., a cathode electrode) facing the first electrode and connected to the second power line (VSL), and a light emitting layer disposed between the first electrode and the second electrode. In one embodiment, the first electrode of the light emitting element (ED) may be an individual electrode individually provided to each pixel (PX), and the second electrode of the light emitting element (ED) may be a common electrode shared by a plurality of pixels (PX). The light emitting element (ED) may emit light with a brightness corresponding to the driving current (Id) during a period in which the driving current (Id) is supplied from the pixel circuit (PC).

[0090] FIG. 4 is an equivalent circuit diagram showing a pixel (PX) according to one embodiment. For example, FIG. 4 shows an additional embodiment related to switching transistors among the pixel transistors (Tpx) of FIG. 3.

[0091] In addition to FIGS. 1 to 3, referring to FIG. 4, at least one of the switching transistors provided in the pixel (PX) may include a bottom gate electrode (BG) (or back-gate electrode) facing a gate electrode (e.g., a top gate electrode) with an active layer therebetween. For example, at least one of the second, third, fourth, and fifth transistors (T2, T3, T4, T5) may include a bottom gate electrode (BG).

[0092] In Fig. 4, an embodiment is illustrated in which bottom gate electrodes (BG) are provided to each of the pixel transistors (Tpx), and reference numerals are given only to the bottom gate electrode (BG) provided to one pixel transistor (Tpx) (e.g., the first transistor (T1)). However, the embodiments are not limited thereto. For example, at least one pixel transistor (Tpx) may not include a bottom gate electrode (BG), and / or may not be formed as a double gate transistor such as a gate-sync or source-sync structure.

[0093] In one embodiment, the second, third, fourth, and fifth transistors (T2, T3, T4, T5) may include respective bottom gate electrodes (BG) connected to their respective gate electrodes. For example, each of the second, third, fourth, and fifth transistors (T2, T3, T4, T5) may be formed as a double-gate transistor with a gate-sink structure.

[0094] By providing bottom gate electrodes (BG) to the second, third, fourth and fifth transistors (T2, T3, T4, T5), respectively, current fluctuations of the second, third, fourth and fifth transistors (T2, T3, T4, T5) due to light can be prevented or reduced. In addition, when the bottom gate electrodes (BG) of each of the second, third, fourth and fifth transistors (T2, T3, T4, T5) are connected to the gate electrodes of each of the second, third, fourth and fifth transistors (T2, T3, T4, T5), the operating characteristics (e.g., switching characteristics) of each of the second, third, fourth and fifth transistors (T2, T3, T4, T5) can be improved and / or stabilized. For example, by forming at least one switching transistor with a double gate structure of a gate-sink structure, the off characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be secured, leakage current can be reduced, and voltage stability can be improved. For example, by forming a small-sized switching transistor formed with an oxide transistor having a short channel length with a double gate structure such as a gate-sink structure, the operating characteristics of the switching transistor can be improved.

[0095] Fig. 5 is a plan view showing a pixel transistor (Tpx) and a dummy gate electrode (DG) according to one embodiment. Fig. 5 shows a schematic plan view of one pixel transistor (Tpx) representing pixel transistors (Tpx), and the shape and / or size of each pixel transistor (Tpx) may vary depending on the embodiments.

[0096] In addition to FIGS. 1 to 4, referring to FIG. 5, the pixel transistor (Tpx) may include an active layer (ACT) and a gate electrode (GE) disposed on a portion of the active layer (ACT). In one embodiment, the gate electrode (GE) may be a top gate electrode disposed on top of the active layer (ACT), and a gate insulating layer may be disposed between the active layer (ACT) and the gate electrode (GE).

[0097] In one embodiment, the pixel transistor (Tpx) may further include a source electrode (SE) and a drain electrode (DE) disposed on different portions of the active layer (ACT) and connected to different portions of the active layer (ACT) (e.g., portions including a source region and a drain region, respectively) through respective contact holes (CNT). In FIG. 5, only one contact hole (CNT) is referenced.

[0098] In one embodiment, at least one of the pixel transistors (Tpx) provided in the pixel (PX) may not include a separate source electrode (SE) and / or drain electrode (DE). For example, a source region and / or a drain region included in an active layer (ACT) of the at least one pixel transistor (Tpx) may be connected (e.g., directly connected) to other circuit elements, wiring, and / or conductive patterns.

[0099] In one embodiment, at least one pixel transistor (Tpx) may further include a bottom gate electrode (BG), as in the embodiment of FIG. 3 or FIG. 4. For example, at least one pixel transistor (Tpx) may further include a bottom gate electrode (BG) disposed below the active layer (ACT) and facing the gate electrode (GE) with the active layer (ACT) interposed therebetween.

[0100] At least one dummy gate electrode (DG) may be disposed on the active layer (ACT) of at least one pixel transistor (Tpx) and separated and / or spaced from the gate electrode (GE). For example, two dummy gate electrodes (DG) may be disposed on different portions of the active layer (ACT) and spaced from the gate electrode (GE) on either side of the gate electrode (GE) of at least one pixel transistor (Tpx) including the first transistor (T1).

[0101] Fig. 6 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 6 shows a portion of a display area (DA) of the display panel (110).

[0102] FIG. 6 shows a first transistor (T1) and a second transistor (T2) disposed in one pixel area (PXA) as examples of circuit elements that can be provided or disposed in a panel circuit layer (PCL) of a display panel (110). In addition, FIGS. 5 and 6 show a light-emitting display panel including a light-emitting element (ED) (for example, an organic light-emitting diode) as an example of a display panel (110) to which embodiments can be applied. However, the type and / or structure of the display panel (110) is not limited thereto. For example, the display panel (110) may include a light-emitting element of a different type and / or structure, or may be a display panel of a different type and / or structure other than a light-emitting display panel.

[0103] In addition to FIGS. 1 to 5, referring to FIG. 6, the display panel (110) may include a substrate (SUB) (also referred to as a “base member” or “base layer”), a panel circuit layer (PCL), a light emitting element layer (LEL), and an encapsulation layer (ENL). The panel circuit layer (PCL), the light emitting element layer (LEL), and the encapsulation layer (ENL) may be arranged or provided on the substrate (SUB) to overlap each other. In one embodiment, the panel circuit layer (PCL), the light emitting element layer (LEL), and the encapsulation layer (ENL) may be arranged or formed sequentially on the substrate (SUB) along a third direction (D3).

[0104] In one embodiment, the display panel (110) may further include additional elements disposed above and / or below the encapsulation layer (ENL). For example, the display panel (110) may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and / or the protective layer may be disposed above the encapsulation layer (ENL) or between the light emitting element layer (LEL) and the encapsulation layer (ENL).

[0105] The substrate (SUB) is a base member for forming the display panel (110), and may be a substrate (or film) having rigid or flexible characteristics. In one embodiment, the substrate (SUB) may be a substrate having rigid characteristics including an insulating material such as glass, and may not be bent. In another embodiment, the substrate (SUB) may be a flexible substrate including polyimide or another insulating material, and may be deformable by bending, folding, rolling, etc., and may or may not be bent. The type and / or material of the substrate (SUB) may vary depending on the embodiments.

[0106] The substrate (SUB) may include at least a display area (DA). In one embodiment, the display area (DA) may include pixel areas (PXA) corresponding to each pixel (PX). For example, the display area (DA) may define respective pixel areas (PXA) in which each pixel (PX) is arranged.

[0107] In one embodiment, a barrier layer (BRL) may be provided on the substrate (SUB). For example, the display panel (110) may further include a barrier layer (BRL) disposed between the substrate (SUB) and the panel circuit layer (PCL). In another embodiment, the display panel (110) may not include a barrier layer (BRL), in which case the panel circuit layer (PCL) may be disposed (for example, directly disposed) on the substrate (SUB).

[0108] The barrier layer (BRL) may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The barrier layer (BRL) may protect the pixels (PX) from moisture permeating through the substrate (SUB) that is vulnerable to moisture permeation. The material of the barrier layer (BRL) may vary depending on the embodiments.

[0109] A panel circuit layer (PCL) may be arranged on one surface of a substrate (SUB) provided with a barrier layer (BRL). The panel circuit layer (PCL) may include circuit elements including pixel transistors (Tpx) and pixel capacitors (Cpx), and wires (e.g., signal lines and power lines).

[0110] The panel circuit layer (PCL) may further include insulating layers disposed on the substrate (SUB). For example, the panel circuit layer (PCL) may include a buffer layer (BFL) (also referred to as a “first insulating layer”), a gate insulating layer (GI) (also referred to as a “second insulating layer”), an interlayer insulating layer (ILD) (also referred to as a “third insulating layer”), and a passivation layer (PSV) (also referred to as a “fourth insulating layer”) sequentially disposed on the substrate (SUB) along a third direction (D3). In one embodiment, the buffer layer (BFL), the interlayer insulating layer (ILD), and the passivation layer (PSV) may be formed over the entire display area (DA), and the gate insulating layer (GI) may be formed as insulating patterns locally disposed on a portion of each of the active layers (ACT) of the pixel transistors (Tpx).

[0111] In one embodiment, the passivation layer (PSV) may have a multilayer structure including an inorganic film (e.g., an inorganic insulating layer) and an organic film (e.g., an organic insulating layer). For example, the passivation layer (PSV) may include an inorganic film (IOL) and an organic film (ORL) sequentially disposed on an interlayer insulating layer (ILD).

[0112] In one embodiment, the display panel (110) may further include additional conductive layers and / or passivation layers. For example, the display panel (110) may further include at least one fourth conductive layer provided on the passivation layer (PSV), and at least one insulating layer covering the fourth conductive layer. In an embodiment in which the display panel (110) further includes a fourth conductive layer, the fourth conductive layer may be provided with at least one wire and / or bridge pattern (for example, a bridge pattern connected between the first source electrode (SE1) of the first transistor (T1) and the first electrode (ET1) of the light emitting element (ED).

[0113] In one embodiment, each of the buffer layer (BFL), the gate insulating layer (GI), the interlayer insulating layer (ILD), and the inorganic layer (IOL) can include at least one inorganic insulating layer comprising an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating material).

[0114] The organic layer (ORL) may include at least one organic insulating layer comprising an organic insulating material (e.g., an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or another organic insulating material). A surface (e.g., an upper surface) of the organic layer (ORL) may be substantially flat.

[0115] Pixel transistors (Tpx) may be included in a pixel circuit (PC) of each pixel (PX) and may be located in a display area (DA). For example, a first transistor (T1) and a second transistor (T2) provided (for example, included) to each pixel (PX) may be placed in each pixel area (PXA) where the corresponding pixel (PX) is located. In describing embodiments, when a specific element is “provided” to another element, it may mean that the specific element is included or placed inside the other element. In addition, at least one other pixel transistor (Tpx) and / or at least one pixel capacitor (Cpx) may be further placed in each pixel area (PXA).

[0116] In one embodiment, at least one pixel transistor (Tpx) may include a bottom gate electrode (BG). For example, a first transistor (T1) may include a first bottom gate electrode (BG1), and a second transistor (T2) may include a second bottom gate electrode (BG2). In one embodiment, the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) may be provided in the same layer (e.g., the first conductive layer (CDL1)) within the panel circuit layer (PCL).

[0117] A first transistor (T1) may include a first bottom gate electrode (BG1) disposed on a substrate (SUB), a first active layer (ACT1) (also referred to as a “first active pattern”) disposed on the first bottom gate electrode (BG1), and a first gate electrode (GE1) disposed on the first active layer (ACT1). A buffer layer (BFL) may be disposed between the first bottom gate electrode (BG1) and the first active layer (ACT1). A first gate insulating layer (GI1) may be disposed between the first active layer (ACT1) and the first gate electrode (GE1).

[0118] In one embodiment, the first transistor (T1) may further include a first source electrode (SE1) and a first drain electrode (DE1) connected to different portions of the first active layer (ACT1). Alternatively, the first transistor (T1) may not include separate source electrodes and / or drain electrodes, and the first source region (SR1) and / or the first drain region (DR1) of the first active layer (ACT1) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the source electrode and / or the drain electrode of the first transistor (T1).

[0119] A first bottom gate electrode (BG1) may be provided on a first conductive layer (CDL1) on a substrate (SUB). For example, the first conductive layer (CDL1) includes the first bottom gate electrode (BG1) and may optionally further include additional conductive patterns. In one embodiment, the first conductive layer (CDL1) may be disposed between the substrate (SUB) and a buffer layer (BFL). For example, the first conductive layer (CDL1) may be disposed on a barrier layer (BRL) and covered by the buffer layer (BFL).

[0120] The first bottom gate electrode (BG1) may overlap the first active layer (ACT1). For example, the first bottom gate electrode (BG1) may be disposed under the first active layer (ACT1) so as to overlap at least the first channel region (CH1). The first bottom gate electrode (BG1) and the first active layer (ACT1) may be spaced apart from each other with a buffer layer (BFL) therebetween. The first bottom gate electrode (BG1) may face the first gate electrode (GE1) with the first active layer (ACT1) therebetween. In one embodiment, the first bottom gate electrode (BG1) may be electrically connected to the first source electrode (SE1) and may be utilized as a back-gate electrode for adjusting the characteristics of the first transistor (T1).

[0121] A first active layer (ACT1) may be provided on a semiconductor layer (SCL) on a substrate (SUB). For example, the semiconductor layer (SCL) includes the first active layer (ACT1) and may optionally further include additional semiconductor patterns. In one embodiment, the semiconductor layer (SCL) may be disposed on a buffer layer (BFL) and may be covered by a gate insulating layer (GI) and an interlayer insulating layer (ILD).

[0122] The first active layer (ACT1) may include a first portion (ACT11) located at the center, and a second portion (ACT12) and a third portion (ACT13) spaced apart from each other with the first portion (ACT11) interposed therebetween. For example, the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1) may be located on both sides of the first portion (ACT11).

[0123] At least a portion of the first active layer (ACT1) including the first portion (ACT11) may overlap the first bottom gate electrode (BG1). The first portion (ACT11) of the first active layer (ACT1) may include a first channel region (CH1). In one embodiment, the entire first portion (ACT11) of the first active layer (ACT1) may be the first channel region (CH1). The first channel region (CH1) may be a region that is not conductive and maintains semiconductor characteristics.

[0124] The first active layer (ACT1) may include a first source region (SR1) and a first drain region (DR1) located in a second portion (ACT12) and a third portion (ACT13), respectively. For example, the second portion (ACT12) of the first active layer (ACT1) may include the first source region (SR1), and the third portion (ACT13) of the first active layer (ACT1) may include the first drain region (DR1). In one embodiment, the entire second portion (ACT12) of the first active layer (ACT1) may be the first source region (SR1), and the entire third portion (ACT13) of the first active layer (ACT1) may be the first drain region (DR1). The first source region (SR1) may be located on one side of the first channel region (CH1), and the first drain region (DR1) may be located on the other side of the first channel region (CH1). The first source region (SR1) and the first drain region (DR1) may be spaced apart from each other with the first channel region (CH1) therebetween. The first source region (SR1) and the first drain region (DR1) are conductive regions and may have a higher carrier concentration (e.g., electron concentration) than the first channel region (CH1).

[0125] A first gate insulating layer (GI1) may be disposed on a portion of the first active layer (ACT1). For example, the first gate insulating layer (GI1) may be disposed between the first active layer (ACT1) and the first gate electrode (GE1), and between the first active layer (ACT1) and the first dummy gate electrodes (DG1).

[0126] In one embodiment, the first gate insulating layer (GI1) may have an etched shape that covers only a portion of the first active layer (ACT1) and exposes another portion of the first active layer (ACT1). For example, the first gate insulating layer (GI1) may include an insulating pattern that is disposed between the first active layer (ACT1) and the first gate electrode (GE1) and covers at least a first portion (ACT11) of the first active layer (ACT1). For example, the first gate insulating layer (GI1) may include an insulating pattern that is disposed under the first gate electrode (GE1) and covers a first portion (ACT11) of the first active layer (ACT1) and a portion of each of a second portion (ACT12) and a third portion (ACT13) immediately adjacent to the first portion (ACT11). The first gate insulating layer (GI1) is not provided on a different portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1), and thus can expose a different portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1). The first gate insulating layer (GI1) may further include at least one insulating pattern disposed between the first active layer (ACT1) and at least one first dummy gate electrode (DG1) disposed on the first active layer (ACT1). For example, the first gate insulating layer (GI1) may further include insulating patterns disposed under each of the first dummy gate electrodes (DG1) located on both sides of the first gate electrode (GE1).

[0127] In one embodiment, the insulating patterns disposed on the first active layer (ACT1) may be separated from each other. However, the embodiments are not limited thereto. For example, the first gate insulating layer (GI1) may be formed as a single insulating pattern that is connected to each other when viewed from a plan view, and may have an etched shape that includes an opening corresponding to a portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1).

[0128] As the first gate insulating layer (GI1) exposes a portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1), the first source region (SR1) and the first drain region (DR1) can be appropriately and / or easily made conductive during the manufacturing process of the display panel (110). For example, the first gate insulating layer (GI1) is formed by etching the gate insulating layer (GI) so that a portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1) is exposed, and the interlayer insulating layer (ILD) is formed in a state where a portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1) is exposed, thereby making the first source region (SR1) and the first drain region (DR1) can be appropriately and / or easily made conductive without performing a separate doping process.

[0129] A first gate electrode (GE1) and first dummy gate electrodes (DG1) may be disposed on a first gate insulating layer (GI1). The first gate electrode (GE1) and the first dummy gate electrodes (DG1) may be provided on a second conductive layer (CDL2) on a substrate (SUB). For example, the second conductive layer (CDL2) includes the first gate electrode (GE1) and the first dummy gate electrodes (DG1), and may optionally further include additional conductive patterns. In one embodiment, the second conductive layer (CDL2) may be disposed on the gate insulating layer (GI) and covered by an interlayer insulating layer (ILD).

[0130] The first gate electrode (GE1) may be disposed on a portion of the first active layer (ACT1) including the first portion (ACT11). For example, the first gate electrode (GE1) may be disposed on the first portion (ACT11) of the first active layer (ACT1) so as to overlap at least the first channel region (CH1).

[0131] In one embodiment, the first gate electrode (GE1) may also be disposed on a portion of each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1) so as to overlap a portion of each of the first source region (SR1) and the first drain region (DR1). For example, the first gate electrode (GE1) may overlap the first source region (SR1) and the first drain region (DR1) by a section corresponding to the length of △L1 (for example, by the length of △L1) for a portion of each of the first source region (SR1) and the first drain region (DR1) that contacts the first channel region (CH1). The section corresponding to the length of △L1 in each of the first source region (SR1) and the first drain region (DR1) may correspond to a section in which oxygen vacancies, which may mainly occur in a part of the first active layer (ACT1) (for example, the second part (ACT12) and the third part (ACT13)) during the manufacturing process of the display panel (110), are diffused to a part of the region overlapping the first gate electrode (GE1) and the first gate insulating layer (GI1), thereby expanding the first source region (SR1) and the first drain region (DR1).

[0132] Although FIG. 6 illustrates an embodiment in which the first channel region (CH1) overlaps the first source region (SR1) and the first drain region (DR1) by a section corresponding to the same length as each other, the embodiments are not limited thereto. In addition, due to process deviations, etc., the length and / or area of ​​the section in which the first channel region (CH1) and the first source region (SR1) overlap may be different from the length and / or area of ​​the section in which the first channel region (CH1) and the first drain region (DR1) overlap.

[0133] Accordingly, the first gate electrode (GE1) may cover at least the first channel region (CH1) and overlap a portion of the first source region (SR1) and the first drain region (DR1) by a section corresponding to a first length (for example, 2△L1, which is twice △L1) in the longitudinal direction of the first active layer (ACT1) (for example, by the first length). For example, each of the two ends of the first gate electrode (GE1) may overlap the first source region (SR1) or the first drain region (DR1) by an area corresponding to a section having a length corresponding to △L1 of the first active layer (ACT1).

[0134] At least one first dummy gate electrode (DG1) separated and / or spaced from the first gate electrode (GE1) may be disposed on at least one of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1). In one embodiment, the first dummy gate electrodes (DG1) may be disposed on each of the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1).

[0135] Since a plurality of first dummy gate electrodes (DG1) (for example, two first dummy gate electrodes (DG1)) spaced apart from the first gate electrode (GE1) are arranged on both sides of the first gate electrode (GE1), oxygen vacancies that mainly occur in a part of the first active layer (ACT1) that is not covered with the first gate insulating layer (GI1) during the manufacturing process of the display panel (110) can be diffused in both directions within the first active layer (ACT1). For example, in a patterning process of the first gate insulating layer (GI1), oxygen vacancies may occur in the oxide semiconductor forming the first active layer (ACT1) by an etching gas or the like, centered on a part of the first active layer (ACT1) exposed in the region between the first gate electrode (GE1) and the first dummy gate electrodes (DG1). Oxygen vacancies can diffuse into the region below the first gate electrode (GE1) of the first active layer (ACT1), as well as into the region below each of the first dummy gate electrodes (DG1) of the first active layer (ACT1). For example, by forming the first dummy gate electrodes (DG1), the diffusion direction of oxygen vacancies generated in the first active layer (ACT1) can be distributed. Additionally, by arranging the first dummy gate electrodes (DG1) spaced apart from the first gate electrode (GE1) on both sides of the first gate electrode (GE1), hydrogen that is intensively introduced into a portion of the first active layer (ACT1) that is not covered with the first gate insulating layer (GI1) during the manufacturing process of the display panel (110) can also diffuse in both directions within the first active layer (ACT1).

[0136] As oxygen vacancies diffuse in both directions within the first active layer (ACT1), the amount of diffusion of oxygen vacancies into a portion of the first active layer (ACT1) located under the first gate electrode (GE1) and / or the length of the region into which oxygen vacancies diffuse under the first gate electrode (GE1) can be reduced. Accordingly, the overlapping area between the first gate electrode (GE1) and the first source and drain regions (SR1, DR1) can be reduced.

[0137] When the overlapping area of ​​the first gate electrode (GE1) and the first source and drain regions (SR1, DR1) is reduced, the size of the parasitic capacitance formed in the first transistor (T1) (for example, the electrostatic capacitance formed between the first gate electrode (GE1) and the first source and drain regions (SR1, DR1)) can be reduced. In one embodiment, the first transistor (T1) may be a driving transistor that controls the driving current (Id) flowing to the light emitting element (ED) in response to the voltage applied to the first gate electrode (GE1). By reducing or minimizing the size of the parasitic capacitance formed in the first transistor (T1), characteristic fluctuations and / or characteristic deviations of the first transistor (T1) can be prevented, reduced, or minimized. As a result, image stains due to brightness deviations of the pixels (PX), etc., can be prevented, reduced, or minimized, and the picture quality of the display device (100) can be improved.

[0138] In one embodiment, each of the first dummy gate electrodes (DG1) may have a length (Ld1) equal to or less than a first length corresponding to 2△L1 in the longitudinal direction of the first active layer (ACT1). Accordingly, a portion of the first active layer (ACT1) overlapping each of the first dummy gate electrodes (DG1) may be conductive by oxygen vacancies and / or hydrogen introduced from both directions. Accordingly, the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1), including the region overlapping each of the first dummy gate electrodes (DG1), may be regions conductive to the first source and drain regions (SR1, DR1). For example, the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1) may exhibit electrical characteristics substantially like a conductor.

[0139] A semiconductor layer (SCL) including a first active layer (ACT1), a gate insulating layer (GI) including a first gate insulating layer (GI1), and a second conductive layer (CDL2) including a first gate electrode (GE1) and first dummy gate electrodes (DG1) may be covered by an interlayer insulating layer (ILD). A third conductive layer (CDL3) may be disposed on the interlayer insulating layer (ILD).

[0140] A first source electrode (SE1) and a first drain electrode (DE1) may be provided on a third conductive layer (CDL3). For example, the third conductive layer (CDL3) includes a first source electrode (SE1) and a first drain electrode (DE1), and may optionally further include additional conductive patterns. The first source electrode (SE1) and the first drain electrode (DE1) are disposed on an interlayer insulating layer (ILD), and may be electrically connected to a first source region (SR1) and a first drain region (DR1), respectively.

[0141] In the embodiment of FIG. 6, the first transistor (T1) of each pixel (PX) may be connected to the light-emitting element (ED) of the corresponding pixel (PX). For example, the first source electrode (SE1) of each pixel (PX) may be directly connected to the first electrode (ET1) of the light-emitting element (ED) through at least one contact hole or via hole penetrating the passivation layer (PSV).

[0142] However, the embodiments are not limited thereto. For example, the panel circuit layer (PCL) may further include a fourth conductive layer disposed on a passivation layer (PSV) and an insulating layer covering the fourth conductive layer, and the first transistor (T1) may be connected to the light emitting element (ED) through a bridge pattern provided on the fourth conductive layer.

[0143] The second transistor (T2) may include a second bottom gate electrode (BG2) disposed on a substrate (SUB), a second active layer (ACT2) (also referred to as a “second active pattern”) disposed on the second bottom gate electrode (BG2), and a second gate electrode (GE2) disposed on the second active layer (ACT2). A buffer layer (BFL) may be disposed between the second bottom gate electrode (BG2) and the second active layer (ACT2). A second gate insulating layer (GI2) may be disposed between the second active layer (ACT2) and the second gate electrode (GE2).

[0144] In one embodiment, the second transistor (T2) may further include a second source electrode (SE2) and a second drain electrode (DE2) connected to different portions of the second active layer (ACT2). Alternatively, the second transistor (T2) may not include separate source electrodes and / or drain electrodes, and the second drain region (DR2) and / or the second source region (SR2) of the second active layer (ACT2) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the source electrode and / or the drain electrode of the second transistor (T2).

[0145] The second bottom gate electrode (BG2) may be provided on the first conductive layer (CDL1) on the substrate (SUB). For example, the second bottom gate electrode (BG2) may be provided on the first conductive layer (CDL1) together with the first bottom gate electrode (BG1). In this case, the first conductive layer (CDL1) may include the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2).

[0146] The second bottom gate electrode (BG2) may overlap the second active layer (ACT2). For example, the second bottom gate electrode (BG2) may be disposed under the second active layer (ACT2) so as to overlap at least the second channel region (CH2). The second bottom gate electrode (BG2) and the second active layer (ACT2) may be spaced apart from each other with a buffer layer (BFL) therebetween. The second bottom gate electrode (BG2) may face the second gate electrode (GE2) with the second active layer (ACT2) therebetween. In one embodiment, the second bottom gate electrode (BG2) may be connected to the second gate electrode (GE2) of the second transistor (T2) and may be utilized as a back-gate electrode for adjusting the characteristics of the second transistor (T2).

[0147] The second active layer (ACT2) may be provided on the semiconductor layer (SCL) on the substrate (SUB). In one embodiment, the first active layer (ACT1) and the second active layer (ACT2) may be provided and / or arranged on the same layer on the substrate (SUB). For example, the semiconductor layer (SCL) may include the first active layer (ACT1) and the second active layer (ACT2).

[0148] The second active layer (ACT2) may include a first portion (ACT21) located at the center, and a second portion (ACT22) and a third portion (ACT23) spaced apart from each other with the first portion (ACT21) interposed therebetween. For example, the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2) may be located on both sides of the first portion (ACT21) of the second active layer (ACT2).

[0149] At least a portion of the second active layer (ACT2) including the first portion (ACT21) may overlap the second bottom gate electrode (BG2). The first portion (ACT21) of the second active layer (ACT2) may include a second channel region (CH2). In one embodiment, the entire first portion (ACT21) of the second active layer (ACT2) may be the second channel region (CH2). The second channel region (CH2) may be a region that is not conductive and maintains semiconductor characteristics.

[0150] The second active layer (ACT2) may include a second source region (SR2) and a second drain region (DR2) located in a second portion (ACT22) and a third portion (ACT23), respectively. For example, the second portion (ACT22) of the second active layer (ACT2) may include the second source region (SR2), and the third portion (ACT23) of the second active layer (ACT2) may include the second drain region (DR2). In one embodiment, the entire second portion (ACT22) of the second active layer (ACT2) may be the second source region (SR2), and the entire third portion (ACT23) of the second active layer (ACT2) may be the second drain region (DR2). The second source region (SR2) may be located on one side of the second channel region (CH2), and the second drain region (DR2) may be located on the other side of the second channel region (CH2). The second source region (SR2) and the second drain region (DR2) may be spaced apart from each other with the second channel region (CH2) therebetween. The second source region (SR2) and the second drain region (DR2) are conductive regions and may have a higher carrier concentration (e.g., electron concentration) than the second channel region (CH2).

[0151] A second gate insulating layer (GI2) may be disposed on a portion of the second active layer (ACT2). For example, the second gate insulating layer (GI2) may be disposed between the second active layer (ACT2) and the second gate electrode (GE2), and between the second active layer (ACT2) and the second dummy gate electrodes (DG2).

[0152] In one embodiment, the second gate insulating layer (GI2) may have an etched shape so as to cover only a portion of the second active layer (ACT2) and expose another portion of the second active layer (ACT2). For example, the second gate insulating layer (GI2) may include an insulating pattern that is disposed between the second active layer (ACT2) and the second gate electrode (GE2) and covers at least a first portion (ACT21) of the second active layer (ACT2). For example, the second gate insulating layer (GI2) may include an insulating pattern that is disposed under the second gate electrode (GE2) and covers a first portion (ACT21) of the second active layer (ACT2) and a portion of a second portion (ACT22) and a third portion (ACT23) immediately adjacent to the first portion (ACT21). The second gate insulating layer (GI2) is not provided on a different portion of each of the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2), and thus may expose a different portion of each of the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2). The second gate insulating layer (GI2) may further include at least one insulating pattern disposed between the second active layer (ACT2) and at least one second dummy gate electrode (DG2) disposed on the second active layer (ACT2). For example, the second gate insulating layer (GI2) may further include insulating patterns disposed under each of the second dummy gate electrodes (DG2) located on both sides of the second gate electrode (GE2). In one embodiment, the insulating patterns disposed on the second active layer (ACT2) may be separated from each other, but embodiments are not limited thereto.

[0153] As the second gate insulating layer (GI2) exposes a portion of each of the second part (ACT22) and the third part (ACT23) of the second active layer (ACT2), the second source region (SR2) and the second drain region (DR2) can be appropriately and / or easily made conductive during the manufacturing process of the display panel (110). For example, the gate insulating layer (GI) is etched to form the second gate insulating layer (GI2) so that a portion of each of the second part (ACT22) and the third part (ACT23) of the second active layer (ACT2) is exposed, and the interlayer insulating layer (ILD) is formed in a state where a portion of each of the second part (ACT22) and the third part (ACT23) of the second active layer (ACT2) is exposed, thereby making the second source region (SR2) and the second drain region (DR2) can be appropriately and / or easily made conductive without performing a separate doping process.

[0154] A second gate electrode (GE2) and second dummy gate electrodes (DG2) may be disposed on a second gate insulating layer (GI2). The second gate electrode (GE2) and the second dummy gate electrodes (DG2) may be provided on a second conductive layer (CDL2) on a substrate (SUB). In this case, the second conductive layer (CDL2) may include a first gate electrode (GE1), first dummy gate electrodes (DG1), a second gate electrode (GE2), and second dummy gate electrodes (DG2).

[0155] The second gate electrode (GE2) may be disposed on a portion of the second active layer (ACT2) including the first portion (ACT21). For example, the second gate electrode (GE2) may be disposed on the first portion (ACT21) of the second active layer (ACT2) so as to overlap at least the second channel region (CH2).

[0156] In one embodiment, the second gate electrode (GE2) may also be disposed on a portion of each of the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2) so as to overlap a portion of each of the second source region (SR2) and the second drain region (DR2). For example, the second gate electrode (GE2) may overlap the second source region (SR2) and the second drain region (DR2) by a section corresponding to the length of △L2 (for example, by the length of △L2) for a portion of each of the second source region (SR2) and the second drain region (DR2) that contacts the second channel region (CH2). The section corresponding to the length of △L2 in each of the second source region (SR2) and the second drain region (DR2) may correspond to a section in which oxygen vacancies, which may mainly occur in a part of the second active layer (ACT2) (for example, the second part (ACT22) and the third part (ACT23)) during the manufacturing process of the display panel (110), are diffused to a part of the region overlapping the second gate electrode (GE2) and the second gate insulating layer (GI2), thereby expanding the second source region (SR2) and the second drain region (DR2).

[0157] Although FIG. 6 illustrates an embodiment in which the second channel region (CH2) overlaps the second source region (SR2) and the second drain region (DR2) by a section having the same length as each other, the embodiments are not limited thereto. In addition, due to process deviations, etc., the length and / or area of ​​the section in which the second channel region (CH2) and the second source region (SR2) overlap may be different from the length and / or area of ​​the section in which the second channel region (CH2) and the second drain region (DR2) overlap.

[0158] Accordingly, the second gate electrode (GE2) may cover at least the second channel region (CH2) and overlap a portion of the second source region (SR2) and the second drain region (DR2) by a section corresponding to a second length (for example, 2△L2, which is twice △L2) in the longitudinal direction of the second active layer (ACT2) (for example, by the second length). For example, each of the two ends of the second gate electrode (GE2) may overlap the second source region (SR2) and the second drain region (DR2) by an area corresponding to a section having a length corresponding to △L2 of the second active layer (ACT2). In one embodiment, the first length and the second length (or △L1 and △L2) may be substantially the same, but the embodiments are not limited thereto.

[0159] At least one second dummy gate electrode (DG2) may be disposed on at least one of the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2), and may be separated and / or spaced apart from the second gate electrode (GE2). In one embodiment, the second dummy gate electrodes (DG2) may be disposed on each of the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2).

[0160] Since a plurality of second dummy gate electrodes (DG2) (for example, two second dummy gate electrodes (DG2)) spaced apart from the second gate electrode (GE2) are arranged on both sides of the second gate electrode (GE2), oxygen vacancies that mainly occur on a part of the second active layer (ACT2) that is not covered with the second gate insulating layer (GI2) during the manufacturing process of the display panel (110) can be diffused in both directions within the second active layer (ACT2). For example, oxygen vacancies may occur in the oxide semiconductor forming the second active layer (ACT2) during a patterning process of the second gate insulating layer (GI2). The oxygen vacancies may not only diffuse into the region below the second gate electrode (GE2) of the second active layer (ACT2), but also diffuse into the region below each of the second dummy gate electrodes (DG2) of the second active layer (ACT2). For example, by forming the second dummy gate electrodes (DG2), the diffusion direction of oxygen vacancies generated in the second active layer (ACT2) can be dispersed. Additionally, by positioning the second dummy gate electrodes (DG2) spaced apart from the second gate electrode (GE2) on both sides of the second gate electrode (GE2), hydrogen that is intensively introduced into a portion of the second active layer (ACT2) that is not covered with the second gate insulating layer (GI2) during the manufacturing process of the display panel (110) can also diffuse in both directions within the second active layer (ACT2).

[0161] As oxygen vacancies diffuse in both directions within the second active layer (ACT2), the amount of oxygen vacancies diffused into a portion of the second active layer (ACT2) located under the second gate electrode (GE2) and / or the length of the region into which oxygen vacancies diffuse under the second gate electrode (GE2) can be reduced. Accordingly, the overlapping area between the second gate electrode (GE2) and the second source and drain regions (SR2, DR2) can be reduced.

[0162] When the overlapping area of ​​the second gate electrode (GE2) and the second source and drain regions (SR2, DR2) is reduced, the size of the parasitic capacitance formed in the second transistor (T2) (for example, the electrostatic capacitance formed between the second gate electrode (GE2) and the second source and drain regions (SR2, DR2)) can be reduced. In one embodiment, the second transistor (T2) can be electrically connected to the first gate electrode (GE1). For example, the second source region (SR2) and / or the second source electrode (SE2) of the second transistor (T2) can be electrically connected to the first gate electrode (GE1). By reducing or minimizing the size of the parasitic capacitance formed in the second transistor (T2), voltage fluctuation of the first node (N1) to which the first gate electrode (GE1) is connected can be prevented, reduced, or minimized. By this, image staining due to luminance deviation of pixels (PX), etc. can be prevented, reduced or minimized, and the picture quality of the display device (100) can be improved. In one embodiment, the second transistor (T2) may be a switching transistor connected to the first driver (120) through a gate line (GL) (for example, the first gate line (GWL)). By reducing or minimizing the size of the parasitic capacitance formed in the second transistor (T2), the load formed at the output terminal of the first driver (120) can be reduced. Accordingly, the output characteristics of the first driver (120) can be improved. In one embodiment, at least one dummy gate electrode may be arranged in at least one other pixel transistor (Tpx) connected to the first node (N1), such as the third transistor (T3). Accordingly, voltage fluctuation of the first node (N1) can be prevented, reduced or minimized, and the load formed at the output terminal of the first driver (120) can be reduced.

[0163] In one embodiment, each of the second dummy gate electrodes (DG2) may have a length (Ld2) equal to or less than a second length corresponding to 2△L2 in the longitudinal direction of the second active layer (ACT2). Accordingly, a portion of the second active layer (ACT2) overlapping each of the second dummy gate electrodes (DG2) may be conductive by oxygen vacancies and / or hydrogen introduced from both directions. Accordingly, the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2), including the region overlapping each of the second dummy gate electrodes (DG2), may be regions that are conductive to the second source and drain regions (SR2, DR2). For example, the second portion (ACT22) and the third portion (ACT23) of the second active layer (ACT2) may exhibit electrical characteristics substantially like a conductor.

[0164] The second source electrode (SE2) and the second drain electrode (DE2) may be provided on the third conductive layer (CDL3). In this case, the third conductive layer (CDL3) may include a first source electrode (SE1), a first drain electrode (DE1), a second source electrode (SE2), and a second drain electrode (DE2). For example, the second source electrode (SE2) and the second drain electrode (DE2) may be disposed on an interlayer insulating layer (ILD) and may be electrically connected to the second source region (SR2) and the second drain region (DR2), respectively.

[0165] Pixel transistors (Tpx) including a first transistor (T1) and a second transistor (T2) may be covered by a passivation layer (PSV).

[0166] Each of the electrodes, conductive patterns and / or wires provided on the conductive layers of the panel circuit layer (PCL) (for example, included in the conductive layers) may include at least one conductive material, and may each have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns and / or wires provided on each of the first conductive layer (CDL1), the second conductive layer (CDL2) and the third conductive layer (CDL3) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials, and may each have a single-layer or multi-layer structure. In one embodiment, electrodes, conductive patterns and / or wires disposed on the same conductive layer can be formed simultaneously using the same conductive material.

[0167] In one embodiment, the active layers provided on the semiconductor layer (SCL), for example, the first active layer (ACT1) and the second active layer (ACT2) included in the semiconductor layer (SCL), may include oxide semiconductors. For example, the active layers provided on the semiconductor layer (SCL) may include at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). For example, each of the first active layer (ACT1) and the second active layer (ACT2) may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), and indium-tin-gallium-zinc oxide (ITGZO), or another oxide semiconductor. The oxide semiconductor used in forming the oxide transistors including the first transistor (T1) and the second transistor (T2) is not limited to the materials exemplified above, and may be variously changed according to embodiments.

[0168] In one embodiment, the active layers provided on the same semiconductor layer (SCL) may include the same oxide semiconductor. For example, the first active layer (ACT1) and the second active layer (ACT2) may be formed simultaneously using the same oxide semiconductor.

[0169] The light emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) and can be located in the display area (DA). For example, the light emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) in the display area (DA).

[0170] The light emitting element layer (LEL) may include light emitting elements (ED) of the pixels (PX). For example, the light emitting element layer (LEL) may include a pixel defining layer (PDL) (also referred to as a “bank”) that defines a light emitting area of ​​each of the pixels (PX) and a light emitting element (ED) positioned in each light emitting area. In one embodiment, the light emitting element layer (LEL) may further include a spacer (SPC) disposed on a portion of the pixel defining layer (PDL).

[0171] Each light emitting element (ED) may include a first electrode (ET1) connected to at least one pixel transistor (Tpx) (for example, a first transistor (T1)) included in a corresponding pixel (PX), and an emission layer (EML) and a second electrode (ET2) sequentially arranged on the first electrode (ET1). In one embodiment, the light emitting element (ED) may further include a first intermediate layer (for example, a hole layer including a hole transport layer) interposed between the first electrode (ET1) and the emission layer (EML), and a second intermediate layer (for example, an electron layer including an electron transport layer) interposed between the emission layer (EML) and the second electrode (ET2).

[0172] The first electrode (ET1) of the light-emitting element (ED) may be positioned on the panel circuit layer (PCL) corresponding to each light-emitting region. The first electrode (ET1) may include a conductive material. In one embodiment, the first electrode (ET1) may include a metal material having a high reflectivity. For example, the first electrode (ET1) may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or a multi-layer structure including indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.).

[0173] An emission layer (EML) of a light-emitting element (ED) may include a polymer material or a low-molecular material. Light emitted from the emission layer (EML) may contribute to image display. In one embodiment, the emission layer (EML) may be provided for each pixel (PX), and the emission layer (EML) of each pixel (PX) may emit visible light of a color corresponding to the pixel (PX). In another embodiment, the emission layer (EML) may be a common layer shared by pixels (PX) of different colors, and wavelength conversion layers and / or color filters corresponding to the color (or wavelength band) of light to be emitted from each pixel (PX) may be arranged in emission areas of at least some of the pixels (PX).

[0174] The second electrode (ET2) of the light emitting element (ED) may include a conductive material. In one embodiment, the second electrode (ET2) may be a common film formed over the entire display area (DA) in a form that covers the light emitting layer (EML) and the pixel defining layer (PDL). In one embodiment, the second electrode (ET2) may be made of a transparent conductive material (TCO: Transparent Conductive Material) such as ITO, IZO, ZnO, ITZO, etc. that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0175] The pixel defining layer (PDL) has an opening corresponding to each light-emitting area and can surround the light-emitting area. For example, the pixel defining layer (PDL) can be formed to cover an edge of a first electrode (ET1) of a light-emitting element (ED) and can include an opening that exposes the remaining portion of the first electrode (ET1). An area where the exposed first electrode (ET1) and the light-emitting layer (EML) overlap can be defined as the light-emitting area of ​​each pixel (PX).

[0176] In one embodiment, the pixel defining layer (PDL) may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer (PDL) may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB), or other organic insulating materials.

[0177] A spacer (SPC) may be disposed on a portion of a pixel defining layer (PDL). The spacer (SPC) may include at least one organic insulating layer including an organic insulating material. The spacer (SPC) may include the same material as the pixel defining layer (PDL) or a different material from the pixel defining layer (PDL). In one embodiment, the pixel defining layer (PDL) and the spacer (SPC) may be sequentially formed through respective mask processes. In another embodiment, the pixel defining layer (PDL) and the spacer (SPC) may be an integrated pattern formed simultaneously using a halftone mask.

[0178] An encapsulation layer (ENL) may be disposed on the light emitting element layer (LEL). The encapsulation layer (ENL) may cover the light emitting element layer (LEL) in the display area (DA) and extend to the non-display area (NDA) to be in contact with the panel circuit layer (PCL). For example, the encapsulation layer (ENL) may be disposed in the display area (DA) to cover the light emitting element layer (LEL), and an end of the encapsulation layer (ENL) may be located in a part of the non-display area (NDA) adjacent to the display area (DA). The encapsulation layer (ENL) may block the penetration of oxygen or moisture into the light emitting element layer (LEL) and mitigate electrical and / or physical impacts on the panel circuit layer (PCL) and the light emitting element layer (LEL).

[0179] In one embodiment, the encapsulation layer (ENL) may have a multilayer structure including a first encapsulation layer (ENL1), a second encapsulation layer (ENL2), and a third encapsulation layer (ENL3) sequentially arranged on the light emitting element layer (LEL). Each of the first encapsulation layer (ENL1) and the third encapsulation layer (ENL3) may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer (ENL2) may be an organic encapsulation layer including an organic material. The structure and / or material of the encapsulation layer (ENL) may vary depending on the embodiments.

[0180] Fig. 7 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 7 shows an embodiment that is different from the embodiment of Fig. 6 with respect to the lengths of the first and second dummy gate electrodes (DG1, DG2). In describing the embodiments below, redundant descriptions of configurations that are substantially the same or similar to at least one embodiment described above will be omitted.

[0181] In addition to FIGS. 1 to 6, referring to FIG. 7, at least one first dummy gate electrode (DG1) may have a length (Ld1') longer than a first length (for example, 2△L1) in the longitudinal direction of the first active layer (ACT1). Accordingly, the first active layer (ACT1) may include at least one first dummy channel region (DCH1) positioned in at least one of the second portion (ACT12) and the third portion (ACT13) and overlapping with at least one first dummy gate electrode (DG1).

[0182] For example, each of the first dummy gate electrodes (DG1) positioned on both sides of the first gate electrode (GE1) may have a length (Ld1') longer than a first length (for example, 2△L1) in the longitudinal direction of the first active layer (ACT1). Accordingly, a first dummy channel region (DCH1) may be formed below each of the first dummy gate electrodes (DG1). For example, the first dummy channel region (DCH1) may have a length corresponding to a value obtained by subtracting the first length (for example, 2△L1) from the length (Ld1') of each of the first dummy gate electrodes (DG1).

[0183] In embodiments, the second portion (ACT12) and the third portion (ACT13) of the first active layer (ACT1) may each refer to portions located on different sides of the first portion (ACT11). For example, the second portion (ACT12) of the first active layer (ACT1) may include at least a first source region (SR1). In addition, when a first dummy channel region (DCH1) is formed under a first dummy gate electrode (DG1) disposed on the second portion (ACT12) of the first active layer (ACT1), the second portion (ACT12) of the first active layer (ACT1) may include the first dummy channel region (DCH1) and conductive regions on both sides of the first dummy channel region (DCH1) (for example, the first source region (SR1) of the first transistor (T1), or the source and drain regions of the first dummy transistor (DT1). Similarly, the third portion (ACT13) of the first active layer (ACT1) may include at least a first drain region (DR1). In addition, when a first dummy channel region (DCH1) is formed under a first dummy gate electrode (DG1) disposed on the third portion (ACT13) of the first active layer (ACT1), the third portion (ACT13) of the first active layer (ACT1) may include the first dummy channel region (DCH1) and conductive regions on both sides of the first dummy channel region (DCH1) (for example, the first drain region (DR1) of the first transistor (T1), or the source and drain regions of the first dummy transistor (DT1)).

[0184] Each first dummy gate electrode (DG1) can cover each first dummy channel region (DCH1) and overlap with a portion of the first source region (SR1) or the first drain region (DR1) around the first dummy channel region (DCH1). For example, the first dummy gate electrode (DG1) disposed on the second portion (ACT12) of the first active layer (ACT1) can cover the first dummy channel region (DCH1) located in the second portion (ACT12) of the first active layer (ACT1) and overlap with a portion of the first source region (SR1) adjacent to the first dummy channel region (DCH1). A first dummy gate electrode (DG1) disposed on a third portion (ACT13) of a first active layer (ACT1) may cover a first dummy channel region (DCH1) located in the third portion (ACT13) of the first active layer (ACT1) and overlap a portion of a first drain region (DR1) adjacent to the first dummy channel region (DCH1).

[0185] In one embodiment, each first dummy channel region (DCH1) may have a short channel having a length that falls within a threshold voltage roll-off range of the first dummy transistor (DT1) including the first dummy channel region (DCH1) and each first dummy gate electrode (DG1). For example, each first dummy channel region (DCH1) may have a short channel, and thus, the first dummy transistor (DT1) may operate in the threshold voltage roll-off range. For example, the length (Ld1') of each of the first dummy gate electrodes (DG1) may be less than or equal to the sum of the subthreshold channel length (Subthreshold Channel Length) of the first dummy transistor (DT1) and the first length (for example, 2△L1). Accordingly, each first dummy channel region (DCH1) may have a length that is less than or equal to the subthreshold channel length of the first dummy transistor (DT1). In one embodiment, each first dummy gate electrode (DG1) may have a shorter length than the gate electrode (GE) of each of the pixel transistors (Tpx) provided to each pixel (PX). Accordingly, each first dummy channel region (DCH1) may have a shorter length than the length of the channel region of each of the pixel transistors (Tpx).

[0186] Each first dummy transistor (DT1) can substantially operate like a conductor due to the short-channel effect. For example, each first dummy transistor (DT1) can operate like a wire.

[0187] Similarly, at least one second dummy gate electrode (DG2) may have a length (Ld2') longer than a second length (for example, 2△L2) in the longitudinal direction of the second active layer (ACT2). Accordingly, the second active layer (ACT2) may include at least one second dummy channel region (DCH2) positioned in at least one of the second portion (ACT22) and the third portion (ACT23) and overlapping with at least one second dummy gate electrode (DG2).

[0188] For example, each of the second dummy gate electrodes (DG2) positioned on both sides of the second gate electrode (GE2) may have a length (Ld2') longer than the second length (for example, 2△L2) in the longitudinal direction of the second active layer (ACT2). Accordingly, a second dummy channel region (DCH1) may be formed under each of the second dummy gate electrodes (DG2). For example, the second dummy channel region (DCH2) may have a length corresponding to a value obtained by subtracting the second length (for example, 2△L2) from the length (Ld2') of each of the second dummy gate electrodes (DG2).

[0189] Each second dummy gate electrode (DG2) may cover each second dummy channel region (DCH2) and overlap with a portion of the second source region (SR2) or the second drain region (DR2) around the second dummy channel region (DCH2). For example, the second dummy gate electrode (DG2) disposed on the second portion (ACT22) of the second active layer (ACT2) may cover the second dummy channel region (DCH2) located in the second portion (ACT22) of the second active layer (ACT2) and overlap with a portion of the second source region (SR2) adjacent to the second dummy channel region (DCH2). A second dummy gate electrode (DG2) disposed on a third portion (ACT23) of a second active layer (ACT2) may cover a second dummy channel region (DCH2) located in the third portion (ACT23) of the second active layer (ACT2) and overlap a portion of a second drain region (DR2) adjacent to the second dummy channel region (DCH2).

[0190] In one embodiment, each of the second dummy channel regions (DCH2) may have a short channel having a length that falls within a threshold voltage roll-off range of the second dummy transistor (DT2) including the second dummy channel region (DCH2) and each of the second dummy gate electrodes (DG2). For example, each of the second dummy channel regions (DCH2) may have a short channel, and thus, the second dummy transistor (DT2) may operate in the threshold voltage roll-off range. For example, the length (Ld2') of each of the second dummy gate electrodes (DG2) may be less than or equal to the sum of the subthreshold voltage channel length of the second dummy transistor (DT2) and a second length (for example, 2△L2). Accordingly, each of the second dummy channel regions (DCH2) may have a length that is less than or equal to the subthreshold voltage channel length of the second dummy transistor (DT2). In one embodiment, each second dummy gate electrode (DG2) may have a shorter length than the gate electrode (GE) of each of the pixel transistors (Tpx) provided to each pixel (PX). Accordingly, each second dummy channel region (DCH2) may have a shorter length than the length of the channel region of each of the pixel transistors (Tpx) provided to each pixel (PX).

[0191] Each second dummy transistor (DT2) can substantially operate like a conductor due to the short channel effect. For example, each second dummy transistor (DT2) can operate like a wire.

[0192] FIG. 8 is a plan view showing a pixel transistor (Tpx) and a dummy gate electrode (DG) according to one embodiment. For example, FIG. 8 shows an additional embodiment of the embodiment of FIG. 5 with respect to the dummy gate electrode (DG).

[0193] Fig. 9 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 9 shows an additional embodiment to the embodiments of Figs. 6 and 7 with respect to first and second dummy gate electrodes (DG1, DG2).

[0194] In addition to FIGS. 1 to 7, referring to FIGS. 8 and 9, the display panel (110) may include a power line (PL) connected to each dummy gate electrode (DG) and to which the gate-on voltage of each pixel transistor (Tpx) is applied. In one embodiment, the power line (PL) may be provided on the third conductive layer (CDL3), but is not limited thereto. The position, shape, and / or cross-sectional structure of the power line (PL) may vary depending on the embodiments.

[0195] In one embodiment, the power line (PL) may be a first power line (VDL) to which a first pixel voltage (ELVDD) is applied, and a plurality of dummy gate electrodes (DG) formed in the pixel (PX) may be connected to the same first power line (VDL). For example, a plurality of dummy gate electrodes (DG) formed in the pixel (PX), including the first dummy gate electrodes (DG1) and the second dummy gate electrodes (DG2), may be commonly connected to the first power line (VDL) (or sub-wires constituting the first power line (VDL)). However, the embodiments are not limited thereto. For example, the power line (PL) connected to each dummy gate electrode (DG) may be variously changed according to the embodiments.

[0196] As each dummy gate electrode (DG) is connected to the power line (PL), a gate-on voltage can be applied to each dummy gate electrode (DG). Accordingly, the dummy transistors formed in the pixel (PX) (for example, a plurality of dummy transistors including the first dummy transistors (DT1) and the second dummy transistors (DT2)) can maintain a turn-on state while the display panel (110) is driven.

[0197] For example, even if each first dummy gate electrode (DG1) has a length (Ld1') longer than the first length corresponding to 2△L1, a gate-on voltage is applied to each first dummy gate electrode (DG1) during a period in which the display device (100) is driven, and thus each first dummy transistor (DT1) can maintain a turned-on state. For example, each first dummy transistor (DT1) can operate like a wire.

[0198] Similarly, even if each second dummy gate electrode (DG2) has a length (Ld2') longer than the second length corresponding to 2△L2, a gate-on voltage can be applied to each second dummy gate electrode (DG2) during the period in which the display device (100) is driven. Accordingly, each second dummy transistor (DT2) can maintain a turned-on state and operate like a wiring.

[0199] FIG. 10 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, FIG. 10 shows an embodiment that is different from the embodiments of FIGS. 6 to 9 with respect to the second dummy gate electrode (DG2). As an example, FIG. 10 shows a modified embodiment of the embodiment of FIG. 6 with respect to the second dummy gate electrode (DG2).

[0200] In addition to FIGS. 1 to 9, referring to FIG. 10, a second dummy gate electrode DG2 may be disposed on only one side of the second gate electrode GE2. For example, the pixel PX may include a single second dummy gate electrode DG2 disposed only on the second portion ACT22 of the second active layer ACT2, and no second dummy gate electrode DG2 may be disposed on the third portion ACT23 of the second active layer ACT2. The second portion ACT22 of the second active layer ACT2 may be a portion including a second source region SR2 that is electrically connected to the first gate electrode GE1.

[0201] By arranging the second dummy gate electrode (DG2) on the second portion (ACT22) of the second active layer (ACT2), the size of the parasitic capacitance formed between the second source region (SR2) and the second gate electrode (DG2) can be reduced. Accordingly, the voltage fluctuation of the first node (N1) to which the first gate electrode (GE1) is connected can be prevented, reduced, or minimized, thereby improving the image quality of the display device (100).

[0202] By not arranging the second dummy gate electrode (DG2) on the third portion (ACT23) of the second active layer (ACT2), the size of the second transistor (T2) (e.g., the length of the second active layer (ACT2)) can be reduced. Accordingly, the pixel area (PXA) can be utilized more efficiently.

[0203] In one embodiment, a single dummy gate electrode may be formed only in a portion connected to the first node (N1) of at least one other pixel transistor (Tpx), such as the third transistor (T3), connected to the first node (N1). Accordingly, the area occupied by the pixel transistors (Tpx) may be reduced while preventing, reducing, or minimizing voltage fluctuations of the first node (N1).

[0204] In FIGS. 6 to 10, embodiments are disclosed in which at least one dummy gate electrode (DG) is disposed on the active layer (ACT) of each of the first transistor (T1), which is a driving transistor of the pixel (PX), and at least one switching transistor (for example, the second transistor (T2)), but the embodiments are not limited thereto. In another embodiment, at least one first dummy gate electrode (DG1) (for example, two second dummy gate electrodes (DG2) located on both sides of the first gate electrode (GE1)) may be disposed only on the first active layer (ACT1) of the first transistor (T1), and no dummy gate electrode (DG) may be disposed on the active layers (ACT) of other pixel transistors (Tpx) (for example, switching transistors). For example, the dummy gate electrode (DG) may be selectively disposed only on some pixel transistors (Tpx) in consideration of the operating characteristics of each pixel transistor (Tpx) and the area of ​​the pixel area (PXA). Alternatively, at least one dummy gate electrode (DG) may be disposed on each of all pixel transistors (Tpx) to reduce changes and / or deviations in operating characteristics due to parasitic capacitance. For example, a dummy gate electrode (DG) may be selectively formed on each pixel transistor (Tpx) in consideration of the area of ​​the pixel area (PXA) and the operating characteristics of the pixel (PX) to be secured.

[0205] FIGS. 11 to 18 are cross-sectional views showing a method of manufacturing a display device (100) according to one embodiment. For example, FIGS. 11 to 18 sequentially show steps of forming pixel transistors (Tpx) on a substrate (SUB) among steps of manufacturing the display panel (110) of FIG. 6. In one embodiment, the driver transistors provided to the first driver (120) may be formed simultaneously with the pixel transistors (Tpx) in a manner substantially identical or similar to the pixel transistors (Tpx).

[0206] In addition to FIGS. 1 to 10, referring to FIG. 11, a substrate (SUB) including at least a display area (DA) can be provided. The display area (DA) can include a pixel area (PXA).

[0207] In one embodiment, a barrier layer (BRL) may be formed on a substrate (SUB). The barrier layer (BRL) may be formed through a film formation process (e.g., a deposition process) of an insulating film using at least one insulating material (e.g., an inorganic insulating material) as exemplified above. The material and / or method for forming the barrier layer (BRL) may vary depending on the embodiments.

[0208] In addition to FIGS. 1 to 11, referring to FIG. 12, a first conductive layer (CDL1) including bottom gate electrodes (BG) of pixel transistors (Tpx) may be formed on a substrate (SUB). For example, a first conductive layer (CDL1) including a first bottom gate electrode (BG1) and a second bottom gate electrode (BG2) may be formed on a barrier layer (BRL) on the substrate (SUB). The first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) may be formed in each pixel area (PXA).

[0209] The first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) can be formed through a film formation process (e.g., a deposition process) of a conductive film using at least one conductive material exemplified above and a patterning process (e.g., an etching process using a mask) of the conductive film. The forming material and / or method of the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) can be variously changed according to embodiments.

[0210] Thereafter, a buffer layer (BFL) covering the first conductive layer (CDL1) can be formed on the substrate (SUB). The buffer layer (BFL) can be formed through a film formation process of an insulating film using at least one insulating material (e.g., an inorganic insulating material) as exemplified above. The material and / or method for forming the buffer layer (BFL) can be varied in various ways depending on the embodiments.

[0211] In addition to FIGS. 1 to 12, referring to FIG. 13, a semiconductor layer (SCL) including active layers (ACT) of pixel transistors (Tpx) may be formed on a buffer layer (BFL). For example, a first active layer (ACT1) and a second active layer (ACT2) may be formed in each pixel area (PXA). The first active layer (ACT1) may be formed to overlap at least a portion of the first bottom gate electrode (BG1), and the second active layer (ACT2) may be formed to overlap at least a portion of the second bottom gate electrode (BG2).

[0212] In one embodiment, the active layers (ACT) provided on the same semiconductor layer (SCL) can be formed simultaneously using the same oxide semiconductor. For example, the first active layer (ACT1) and the second active layer (ACT2) can be formed simultaneously using the same oxide semiconductor. For example, the first active layer (ACT1) and the second active layer (ACT2), etc., can be formed in the pixel area (PXA) through the film formation process and patterning process of the oxide semiconductor layer using at least one oxide semiconductor as exemplified above.

[0213] In addition to FIGS. 1 to 13, referring to FIG. 14, a gate insulating layer (GI) covering a semiconductor layer (SCL) can be formed on a substrate (SUB). For example, a gate insulating layer (GI) covering active layers (e.g., a first active layer (ACT1) and a second active layer (ACT2)) provided on a semiconductor layer (SCL) can be formed on a substrate (SUB).

[0214] The gate insulating layer (GI) may be first formed over the entire surface of the substrate (SUB) on which the first and second active layers (ACT1, ACT2), etc., are provided. For example, after the gate insulating layer (GI) is formed on the substrate (SUB) on which the semiconductor layer (SCL) is formed through a process for forming an insulating film using at least one insulating material (e.g., an inorganic insulating material) as exemplified above, a subsequent process such as heat treatment (e.g., annealing) may be performed. The material and / or method for forming the gate insulating layer (GI) may vary depending on the embodiments.

[0215] In addition to FIGS. 1 to 14, referring to FIG. 15, a second conductive layer (CDL2) may be formed on a gate insulating layer (GI). The second conductive layer (CDL2) may include gate electrodes (GE) of pixel transistors (Tpx) including a first gate electrode (GE1) and a second gate electrode (GE2), and a dummy gate electrode (DG) disposed on an active layer (ACT) of at least one pixel transistor (Tpx). On the active layer (ACT) on which the dummy gate electrode (DG) is disposed, the gate electrode (GE) and at least one dummy gate electrode (DG) may be formed to overlap different portions of the active layer (ACT) and be separated from each other. For example, in each pixel area (PXA), gate electrodes (GE) including a first gate electrode (GE1) and a second gate electrode (GE2), at least one first dummy gate electrode (DG1) disposed on a first active layer (ACT1) and separated from the first gate electrode (GE1), and at least one second dummy gate electrode (DG2) disposed on a second active layer (ACT2) and separated from the second gate electrode (GE2) can be formed.

[0216] The gate electrodes (GE) and the dummy gate electrodes (DG) can be formed through a film formation process (e.g., a deposition process) of a conductive film using at least one of the conductive materials exemplified above and a patterning process (e.g., an etching process using a mask) of the conductive film. The materials and / or methods for forming the gate electrodes (GE) and the dummy gate electrodes (DG) can be variously changed depending on the embodiments.

[0217] In addition to FIGS. 1 to 15, referring to FIG. 16, a first gate insulating layer (GI1) and a second gate insulating layer (GI2) may be formed by etching the gate insulating layer (GI). For example, by etching the gate insulating layer (GI), insulating patterns may be formed under each of the gate electrodes (GE) including the first and second gate electrodes (GE1, GE2) and the dummy gate electrodes (DG) including the first and second dummy gate electrodes (DG1, DG2), and a portion of each of the active layers (ACT) may be exposed in a region that does not overlap with the gate electrodes (GE) and the dummy gate electrodes (DG).

[0218] In one embodiment, the gate insulating layer (GI) can be etched using a mask used for patterning the gate electrodes (GE) and the dummy gate electrodes (DG), or using the gate electrodes (GE) and the dummy gate electrodes (DG) as a mask. Accordingly, insulating patterns corresponding to the shape and size of each of the gate electrodes (GE) and the dummy gate electrodes (DG) can be formed under the gate electrodes (GE) and the dummy gate electrodes (DG).

[0219] In the process of forming a first gate insulating layer (GI1), a second gate insulating layer (GI2), etc. by etching the gate insulating layer (GI), the properties of the active layers (ACT) may be changed so that each portion of the active layers (ACT) has different properties. Accordingly, each of the active layers (ACT) may be divided into a plurality of regions (e.g., a channel region, a source region, and a drain region) having different properties.

[0220] For example, oxygen may be removed from the oxide semiconductor forming the first active layer (ACT1) by an etching gas or the like, and oxygen vacancies may occur, centered on a portion that does not overlap with the first gate electrode (GE1) and the first dummy gate electrodes (DG1). Accordingly, the first active layer (ACT1) may be divided into a plurality of regions (for example, a first channel region (CH1), a first drain region (DR1), and a first source region (SR1)) having different characteristics. In one embodiment, the oxygen vacancies may primarily occur in a portion of the first active layer (ACT1) that is not covered with the first gate insulating layer (GI1), and may spread to a portion of the region overlapping with the first gate electrode (GE1), the first dummy gate electrodes (DG1), and / or the first gate insulating layer (GI1). In one embodiment, when each of the first dummy gate electrodes (DG1) has a length (Ld1) less than or equal to a first length corresponding to 2△L1, oxygen vacancies may spread throughout the entire region overlapping the first dummy gate electrodes (DG1) of the first active layer (ACT1).

[0221] Similarly, oxygen vacancies may occur in the second active layer ACT2, centered on a portion that does not overlap with the second gate electrode GE2 and the second dummy gate electrodes DG2. Accordingly, the second active layer ACT2 may be divided into a plurality of regions (for example, a second channel region CH2, a second drain region DR2, and a second source region SR2) having different characteristics. In one embodiment, the oxygen vacancies may primarily occur in a portion of the second active layer ACT2 that is not covered with the second gate insulating layer GI2, and may spread to a portion of the region that overlaps with the second gate electrode GE2, the second dummy gate electrodes DG2, and / or the second active layer ACT2. In one embodiment, when each of the second dummy gate electrodes (DG2) has a length (Ld2) less than or equal to a second length corresponding to 2△L2, oxygen vacancies may spread throughout the entire region overlapping the second dummy gate electrodes (DG2) of the second active layer (ACT2).

[0222] In addition to FIGS. 1 to 16, referring to FIG. 17, an interlayer insulating layer (ILD) covering the active layers (ACT) (for example, the first and second active layers (ACT1, ACT2)) provided on the semiconductor layer (SCL), the insulating patterns (for example, the first and second gate insulating layers (GI1, GI2)) provided on the gate insulating layer (GI), the gate electrodes (GE) (for example, the first and second gate electrodes (GE1, GE2)) provided on the second conductive layer (CDL2), and the dummy gate electrodes (DG) (for example, the first and second dummy gate electrodes (DG1, DG2)) may be formed. The interlayer insulating layer (ILD) may be formed through a process for forming an insulating film using at least one insulating material (for example, an inorganic insulating material) as exemplified above. In one embodiment, a subsequent process such as a heat treatment may be performed after forming the interlayer insulating layer (ILD). The material and / or method of forming the interlayer insulating layer (ILD) may vary depending on the embodiments.

[0223] During the process of forming an interlayer dielectric (ILD), hydrogen may be introduced into the active layers (ACT) of the semiconductor layer (SCL). For example, the hydrogen may be introduced mainly into a portion of the active layers (ACT) that is not covered by each of the gate electrodes (GE) and / or the dummy gate electrodes (DG). Accordingly, the source region (SE) and drain region (DE) of each of the active layers (ACT) may be electrically conductive to have appropriate conductivity.

[0224] In addition to FIGS. 1 to 17, referring to FIG. 18, a third conductive layer (CDL3) including source electrodes (SE) and drain electrodes (DE) may be formed on the interlayer insulating layer (ILD). For example, a first drain electrode (DE1), a first source electrode (SE1), a second source electrode (SE2), and a second drain electrode (DE2) may be formed on the interlayer insulating layer (ILD). In one embodiment, when at least one of the first drain region (DR1), the first source region (SR1), the second source region (SR2), and the second drain region (DR2) replaces at least one of the first drain electrode (DE1), the first source electrode (SE1), the second source electrode (SE2), and the second drain electrode (DE2), at least one of the first drain electrode (DE1), the first source electrode (SE1), the second source electrode (SE2), and the second drain electrode (DE2) may not be formed.

[0225] The first source electrode (SE1) and the first drain electrode (DE1) may be formed to be connected to different portions of the first active layer (ACT1). For example, the first source electrode (SE1) may be formed to be connected to the first source region (SR1), and the first drain electrode (DE1) may be formed to be connected to the first drain region (DR1). The second source electrode (SE2) and the second drain electrode (DE2) may be formed to be connected to different portions of the second active layer (ACT2). For example, the second source electrode (SE2) may be formed to be connected to the second source region (SR2), and the second drain electrode (DE2) may be formed to be connected to the second drain region (DR2). To this end, prior to the formation of the first drain electrode (DE1), the first source electrode (SE1), the second source electrode (SE2), and the second drain electrode (DE2), a plurality of contact holes may be formed in the interlayer insulating layer (ILD).

[0226] Through the above-described process, a plurality of pixel transistors (Tpx) including a first transistor (T1) and a second transistor (T2) and dummy gate electrodes (DG) can be formed in the display area (DA). In one embodiment, elements provided on the same conductive layer or the same semiconductor layer (SCL) within the display panel (110) can be formed simultaneously.

[0227] After forming pixel transistors (Tpx), a process of forming a passivation layer (PSV) as illustrated in FIG. 6 may be performed. The passivation layer (PSV) may cover the pixel transistors (Tpx). Accordingly, a panel circuit layer (PCL) of a display panel (110) may be formed.

[0228] In one embodiment, when the display panel (110) includes a light emitting element layer (LEL) and an encapsulation layer (ENL) disposed on a panel circuit layer (PCL), the light emitting element layer (LEL) and the encapsulation layer (ENL) may be sequentially formed on the panel circuit layer (PCL). By the above-described process, the display panel (110) according to the embodiments and the display device (100) including the same may be manufactured.

[0229] Fig. 19 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 19 shows an embodiment that is different from the embodiment of Fig. 6 with respect to the bottom gate electrode (BG).

[0230] Although FIG. 19 illustrates a modified embodiment of the embodiment of FIG. 6, the embodiment of FIG. 19 may be applied to other embodiments as well. For example, the embodiment of FIG. 19 may be applied to at least one of the embodiments of FIGS. 7, 9, and 10.

[0231] In addition to FIGS. 1 to 18, referring to FIG. 19, each pixel transistor (Tpx) or each switching transistor provided in a pixel (PX) may or may not include a bottom gate electrode (BG). In one embodiment, at least one pixel transistor (Tpx) (e.g., a driving transistor) provided in a pixel (PX) may include a bottom gate electrode (BG), and at least one other pixel transistor (Tpx) (e.g., at least one switching transistor) provided in the pixel (PX) may not include a bottom gate electrode (BG). For example, a first transistor (T1) may include a first bottom gate electrode (BG1), and a second transistor (T2) may not include a bottom gate electrode (BG) (e.g., a second bottom gate electrode (BG2) of FIG. 6). In this way, the structure of the pixel (PX) with respect to the bottom gate electrode (BG) may vary depending on the embodiments.

[0232] Fig. 20 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 20 shows an embodiment that is different from the embodiment of Fig. 6 with respect to the bottom gate electrode (BG).

[0233] Although FIG. 20 illustrates a modified embodiment of the embodiment of FIG. 6, the embodiment of FIG. 20 may be applied to other embodiments as well. For example, the embodiment of FIG. 20 may be applied to at least one of the embodiments of FIGS. 7, 9, 10, and 19.

[0234] In addition to FIGS. 1 to 19, referring to FIG. 20, the bottom gate electrode (BG) provided to the pixel transistor (Tpx) may not overlap with at least one dummy gate electrode (DG) provided to the pixel transistor (Tpx). For example, the second bottom gate electrode (BG2) provided to the second transistor (T2) may not overlap with the second dummy gate electrodes (DG2) provided to the second transistor (T2). For example, the second bottom gate electrode (BG2) may be disposed under the second active layer (ACT2) so as to overlap with the second gate electrode (GE2), and may have a reduced width so as not to overlap with the second dummy gate electrodes (DG2). However, the embodiments are not limited thereto. For example, the second bottom gate electrode (BG2) may overlap with one of the second dummy gate electrodes (DG2) and may not overlap with another second dummy gate electrode (DG2).

[0235] Similarly, the first bottom gate electrode (BG1) provided to the first transistor (T1) may not overlap with at least one first dummy gate electrode (DG1) provided to the first transistor (T1). For example, the first bottom gate electrode (BG1) may be disposed under the first active layer (ACT1) so as to overlap with the first gate electrode (GE1), and may not overlap with the first dummy gate electrode (DG1) adjacent to the first drain electrode (DE1). In one embodiment, the first bottom gate electrode (BG1) may overlap with the first dummy gate electrode (DG1) adjacent to the first source electrode (SE1). However, the embodiments are not limited thereto. For example, the first bottom gate electrode (BG1) may extend to the lower portion of the first source electrode (SE1) bypassing the region where the first dummy gate electrode (DG1) adjacent to the first source electrode (SE1) is disposed.

[0236] In addition, the shape, size, and / or position of the bottom gate electrode (BG) provided to each pixel transistor (Tpx) may be varied according to embodiments.

[0237] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A first transistor comprising a first active layer including a first portion including a first channel region and a second portion and a third portion spaced apart from each other with the first portion interposed therebetween, and a first gate electrode disposed on the first portion of the first active layer; At least one first dummy gate electrode disposed on at least one of the second portion and the third portion of the first active layer and separated from the first gate electrode; and A display device comprising a first gate insulating layer disposed between the first gate electrode and each of the at least one first dummy gate electrode and the first active layer.

2. In paragraph 1, A display device, wherein the first gate insulating layer includes an insulating pattern disposed between the first active layer and the first gate electrode, and exposes a portion of each of the second portion and the third portion of the first active layer.

3. In paragraph 2, A display device, wherein the first gate insulating layer further includes at least one insulating pattern disposed between the at least one first dummy gate electrode and the first active layer.

4. In paragraph 1, The first active layer further includes a first source region located in the second portion and located on one side of the first channel region, and a first drain region located in the third portion and located on the other side of the first channel region, A display device, wherein the first gate electrode covers at least the first channel region and overlaps a portion of the first source region and the first drain region by a section corresponding to a first length in the longitudinal direction of the first active layer.

5. In paragraph 4, A display device, wherein the first dummy gate electrode has a length less than or equal to the first length in the longitudinal direction of the first active layer.

6. In paragraph 4, The first dummy gate electrode has a length longer than the first length in the longitudinal direction of the first active layer, A display device, wherein the first active layer further includes at least one dummy channel region positioned in at least one of the second portion and the third portion and overlapping the first dummy gate electrode.

7. In paragraph 6, A display device, wherein the first dummy gate electrode covers the dummy channel region and overlaps a portion of the first source region or the first drain region around the dummy channel region.

8. In paragraph 7, A display device, wherein the dummy channel region has a short channel having a length that falls within a threshold voltage roll-off range of a dummy transistor including the first dummy gate electrode and the dummy channel region.

9. In paragraph 7, A pixel including a plurality of pixel transistors including the first transistor, A display device, wherein the dummy channel region has a length shorter than the length of the channel region of each of the plurality of pixel transistors.

10. In paragraph 4, further comprising an interlayer insulating layer disposed on the substrate and covering the first active layer, the first gate insulating layer, the first gate electrode, and the at least one dummy gate electrode; A display device, wherein the first transistor further includes at least one of a first source electrode disposed on the interlayer insulating layer and electrically connected to the first source region, and a first drain electrode disposed on the interlayer insulating layer and electrically connected to the first drain region.

11. In paragraph 1, A display device further comprising a power line electrically connected to the first dummy gate electrode and to which a gate-on voltage of the first transistor is applied.

12. In paragraph 1, A pixel circuit including the first transistor and a pixel including a light-emitting element connected to the pixel circuit are included. A display device, wherein the first transistor is a driving transistor that controls a driving current flowing to the light-emitting element in response to a voltage applied to the first gate electrode.

13. In paragraph 12, A display device, wherein the at least one first dummy gate electrode comprises a plurality of first dummy gate electrodes positioned on both sides of the first gate electrode and arranged on top of each of the second portion and the third portion of the first active layer.

14. In paragraph 12, The pixel circuit further includes a second transistor electrically connected to the first gate electrode, The second transistor is, A second active layer disposed on the substrate, comprising a first portion including a second channel region, a second portion located on one side of the second channel region and including a second source region, and a third portion located on the other side of the second channel region and including a second drain region; and A display device comprising a second gate electrode disposed on the first portion of the second active layer.

15. In paragraph 14, The above pixel is, At least one second dummy gate electrode disposed on at least one of the second portion and the third portion of the second active layer and spaced apart from the second gate electrode; and A display device further comprising a second gate insulating layer including insulating patterns disposed between the second gate electrode and each of the at least one second dummy gate electrode and the second active layer.

16. In paragraph 15, The second gate insulating layer exposes a portion of each of the second portion and the third portion of the second active layer, A display device, wherein the second gate electrode covers at least the second channel region and overlaps a portion of each of the second source region and the second drain region around the second channel region.

17. In paragraph 15, A display device, wherein the at least one second dummy gate electrode comprises a plurality of second dummy gate electrodes positioned on both sides of the second gate electrode and arranged on top of each of the second portion and the third portion of the second active layer.

18. In paragraph 15, The second source region is electrically connected to the first gate electrode, A display device, wherein the pixel comprises a single second dummy gate electrode disposed only on the second portion of the second active layer.

19. In paragraph 14, A display device, wherein the first active layer and the second active layer include oxide semiconductors.

20. A step of forming an active layer including an oxide semiconductor on a substrate; A step of forming a gate insulating layer covering the active layer on the substrate; A step of forming a gate electrode and at least one dummy gate electrode overlapping and separated from different parts of the active layer on the gate insulating layer; A step of forming insulating patterns under each of the gate electrode and the at least one dummy gate electrode by etching the gate insulating layer, and exposing a portion of the active layer that does not overlap with the gate electrode and the at least one dummy gate electrode; and A method for manufacturing a display device, comprising the step of forming an interlayer insulating layer covering the active layer, the insulating patterns, the gate electrode, and the at least one dummy gate electrode.

Images