Display substrates and methods for manufacturing these substrates, and display devices.

Abstract

The invention relates to a display substrate and a method of constructing such substrate, and a display device. The display substrate consists of multiple first electrodes (31) and multiple pixel-determining structures (32) which are arranged on a substrate (10), wherein each pixel-determining structure (32) is arranged between adjacent first electrodes (31), and creates pixel holes (35) exposing the first electrodes (31); and each pixel-determining structure (32) consists of at least a first (101), second (102), third (103) and fourth (104) insulator. The orthogonal projection of the second insulator (102) on the substrate (10) overlaps at least partially the orthogonal projection of the first electrode (31) on the substrate (10); second cavities (106) are arranged in the surface of the second insulator (102); and the inner wall on the side of each second cavity (106) near the substrate (10) is arranged between the surface on the first electrode side (31) away from the substrate (10) and the surface on the first electrode side (31) near the substrate (10).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display that has been developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize active addressing of pixels, but also realize the preparation of pixel driving circuits and other structures on silicon-based substrates, which is conducive to reducing the system volume and achieving lightweight. Silicon-based OLED is prepared using the mature complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) integrated circuit process. It has the advantages of small size, high resolution (Pixels Per Inch, PPI), high refresh rate, etc., and is widely used in the field of virtual reality (VR) or augmented reality (AR) near-eye display.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display substrate, including a base substrate, a plurality of first electrodes arranged on the base substrate, and a plurality of pixel definition structures, wherein the pixel definition structure is arranged between adjacent first electrodes and forms a pixel opening exposing the first electrode; in a direction perpendicular to the base substrate, the pixel definition structure includes at least a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the base substrate do not overlap with the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the second insulating layer on the base substrate at least partially overlaps with the orthographic projection of the first electrode on the base substrate; a second recessed portion concave toward the base substrate is provided on a surface of the second insulating layer away from the base substrate, and an inner wall of the second recessed portion close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate.

[0006] In an exemplary embodiment, a second depth of the second recess is 0.01 μm to 0.06 μm, and the second depth is a maximum distance between an inner wall of the second recess close to the base substrate and a surface of the second insulating layer away from the base substrate.

[0007] In an exemplary embodiment, a surface of the first insulating layer away from the base substrate is flush with a surface of the first electrode away from the base substrate, or a surface of the first insulating layer away from the base substrate is lower than a surface of the first electrode away from the base substrate.

[0008] In an exemplary embodiment, the first insulating layer has a first width, the second insulating layer has a second width, the second width is greater than the first width, and the first width and the second width are dimensions in a direction parallel to the substrate.

[0009] In an exemplary embodiment, a difference between the second width and the first width is greater than or equal to 0.1 μm.

[0010] In an exemplary embodiment, a material of the third insulating layer is different from a material of the fourth insulating layer, and a material of the second insulating layer is the same as a material of the fourth insulating layer.

[0011] In an exemplary embodiment, the third insulating layer has a third width, the fourth insulating layer has a fourth width, the fourth width is smaller than the second width, the fourth width is smaller than the first width, the third width is smaller than the fourth width, and the third width and the fourth width are dimensions in a direction parallel to the substrate.

[0012] In an exemplary embodiment, a difference between the fourth width and the second width is greater than or equal to 0.3 μm, and a difference between the fourth width and the third width is 0.1 μm to 0.4 μm.

[0013] In an exemplary embodiment, the fourth insulating layer has a protrusion relative to the side wall of the third insulating layer, and the protrusion and the side wall of the third insulating layer form a first recess that is recessed away from the pixel opening, and a first depth of the first recess is greater than a second depth of the second recess, and the first depth is the maximum distance between the side wall of the fourth insulating layer close to the pixel opening and the side wall of the third insulating layer close to the pixel opening.

[0014] In an exemplary embodiment, the first depth of the first recess is 0.05 μm to 0.2 μm.

[0015] In an exemplary embodiment, a first height of the first recess is greater than a second depth of the second recess, and the first height of the first recess is a maximum distance between a surface of the first recess close to the substrate and a surface of the first recess away from the substrate.

[0016] In an exemplary embodiment, a surface of the fourth insulating layer on a side away from the base substrate is provided with a smooth third recessed portion that is recessed toward the base substrate.

[0017] In an exemplary embodiment, a curvature of the third indentation is smaller than a curvature of the first indentation or a curvature of the second indentation.

[0018] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer disposed on a side of the first electrode and the pixel definition structure away from the base substrate, the organic light-emitting layer including a plurality of film layers, at least one of which is disconnected at an edge of the fourth insulating layer, and a distortion region is provided at the disconnected portion of the film layer of the organic light-emitting layer.

[0019] In an exemplary embodiment, the distorted region may include at least one crack, and an orthographic projection of the distorted region on the base substrate does not overlap with an orthographic projection of the pixel opening on the base substrate.

[0020] In an exemplary embodiment, the display substrate further comprises a second electrode disposed on a side of the organic light-emitting layer away from the base substrate, the second electrode having a puncture tip disposed in a crack of the distortion region, and an orthographic projection of the puncture tip on the base substrate does not overlap with an orthographic projection of the first electrode on the base substrate;

[0021] The orthographic projection of the endpoint of the puncture tip on the substrate is within the range of the orthographic projection of the first insulating layer on the substrate. The endpoint of the puncture tip is the boundary point on the puncture tip closest to the substrate.

[0022] In an exemplary embodiment, the organic light-emitting layer includes a stacked first device, a charge generating layer, and a second device, the first device and the charge generating layer have a first device thickness, the second device has a second device thickness, the first device thickness is less than the second device thickness, and the first device thickness and the second device thickness are dimensions perpendicular to the direction of the substrate.

[0023] In an exemplary embodiment, the first device thickness is less than ½*the second device thickness.

[0024] In an exemplary embodiment, the third insulating layer has a third thickness D3, which is a dimension perpendicular to the substrate; the third thickness is less than the first device thickness, and the third thickness is greater than 1 / 2*the first device thickness.

[0025] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display device including the aforementioned display substrate.

[0026] As a third aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a method for preparing a display substrate, the preparation method comprising: forming a plurality of first electrodes and a plurality of pixel definition structures on a base substrate, the pixel definition structures being arranged between adjacent first electrodes and forming pixel openings exposing the first electrodes; in a direction perpendicular to the base substrate, the pixel definition structures comprising at least a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the base substrate not overlapping with the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the second insulating layer on the base substrate at least partially overlapping with the orthographic projection of the first electrode on the base substrate; a second recess which is concave toward the base substrate is provided on a surface of the second insulating layer away from the base substrate, and an inner wall of the second recess close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate.

[0027] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0028] Summary of the Figures

[0029] The accompanying drawings are intended to facilitate understanding of the technical solutions of this application and constitute part of the specification. Together with the embodiments of this application, they are used to explain the technical solutions of this application and do not constitute a limitation of the technical solutions of this application. The shapes and sizes of the components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of this disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0032] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] FIG4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG5 is an enlarged view of a pixel definition structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG6 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first conductive layer pattern;

[0036] FIG7A is a first schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0037] FIG7B is a second schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0038] FIG7C is a third schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0039] FIG7D is a fourth schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0040] FIG7E is a fifth schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0041] FIG7F is a sixth schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0042] FIG7G is a seventh schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0043] FIG7H is a schematic diagram eight of an exemplary embodiment of the present disclosure after forming a pixel definition structure pattern;

[0044] FIG8 is a schematic diagram of an exemplary embodiment of the present disclosure after forming an organic light-emitting layer pattern;

[0045] FIG9 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second conductive layer pattern;

[0046] FIG10 is a schematic structural diagram of an organic light-emitting layer according to an exemplary embodiment of the present disclosure;

[0047] FIG. 11 is a schematic structural diagram of another organic light-emitting layer according to an exemplary embodiment of the present disclosure.

[0048] Explanation of the accompanying drawings: 10-base substrate; 20-driving circuit layer; 30-light-emitting structure layer; 31-first electrode; 32-pixel definition structure; 33-organic light-emitting layer; 34-second electrode; 35-pixel opening; 40-first encapsulation layer; 50-color filter structure layer; 60-second encapsulation layer; 70-cover layer; 101-first insulating layer; 102-second insulating layer; 103-third insulating layer; 104-fourth insulating layer; 105-first recess; 106-second recess; 107-distortion region; 108-puncture tip; 109-third recess; 111-first photoresist pattern; 112-second photoresist pattern; 33-1-first device; 33-2 charge generation layer; 33-3-second device.

[0049] Details

[0050] The embodiments herein can be implemented in a variety of different forms. A person skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0051] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0052] The ordinal numbers such as "first", "second", and "third" in this article are set to avoid confusion of constituent elements, rather than to limit the quantity.

[0053] In this document, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely to facilitate the description of the embodiments and simplify the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of the present disclosure. The positional relationships of the constituent elements may be appropriately changed according to the orientation of the constituent elements being described. Therefore, the present invention is not limited to the words and phrases described herein and may be appropriately replaced according to the circumstances.

[0054] In this document, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0055] In this article, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (or drain electrode terminal, drain region, or drain electrode) and a source electrode (or source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this article, the channel region refers to the region through which current primarily flows.

[0056] In this article, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source electrode" and "drain electrode" can sometimes be reversed. Therefore, in this article, "source electrode" and "drain electrode" can be reversed.

[0057] As used herein, "electrically connected" includes components connected together via an element having some electrical function. This "element having some electrical function" is not particularly limited as long as it enables the transfer of electrical signals between the connected components. Examples of this "element having some electrical function" include electrodes or wiring, switching elements such as transistors, and other functional components such as resistors, inductors, and capacitors.

[0058] In this article, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0059] In this document, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film." Similarly, "insulating film" can sometimes be replaced with "insulating layer."

[0060] The term "about" as used herein refers to a numerical value that is not strictly limited to a certain limit and is within a range of process and measurement errors.

[0061] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), multiple light emitting signal lines (E1 to Eo), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, a clock signal and a scan start signal suitable for the specifications of the scan signal driver to the scan signal driver, and a clock signal and an emission stop signal suitable for the specifications of the light emitting signal driver to the light emitting signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver can sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal. m can be a natural number. The light signal driver can generate emission signals to be provided to the light signal lines E1, E2, E3, ..., and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light signal driver can sequentially provide emission signals having off-level pulses to the light signal lines E1 to Eo. For example, the light signal driver can be configured as a shift register and can generate light signals by sequentially transmitting light stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal. o can be a natural number. The pixel array can include a plurality of sub-pixels Pxij. Each subpixel Pxij can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, where i and j can be natural numbers. Subpixel Pxij can refer to a subpixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line. In an exemplary embodiment, a pixel array can be provided on a display substrate.

[0062] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0063] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in this disclosure. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally, vertically, or in a square pattern, which is not limited in this disclosure.

[0064] FIG3 is a schematic diagram of the cross-sectional structure of a display substrate, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , the display substrate of a silicon-based OLED display device may include: a base substrate 10, a driving circuit layer 20 arranged on the base substrate 10, a light-emitting structure layer 30 arranged on the side of the driving circuit layer 20 away from the base substrate 10, a first encapsulation layer 40 arranged on the side of the light-emitting structure layer 30 away from the base substrate 10, a color filter structure layer 50 arranged on the side of the first encapsulation layer 40 away from the base substrate 10, a second encapsulation layer 60 arranged on the side of the color filter structure layer 50 away from the base substrate 10, and a cover layer 70 arranged on the side of the second encapsulation layer 60 away from the base substrate 10. In some possible implementations, the display substrate may include other film layers, which are not limited in this disclosure.

[0065] In an exemplary embodiment, the substrate 10 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 20 may be prepared on the substrate 10 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 20 may include a plurality of circuit units, at least one of which may include a pixel driving circuit, which is respectively connected to a scanning signal line and a data signal line. The at least one pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 only takes the pixel driving circuit including one transistor as an example. The transistor may include a control electrode, a first electrode, and a second electrode. The control electrode, the first electrode, and the second electrode may be respectively connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0066] In an exemplary embodiment, the light-emitting structure layer 30 may include multiple light-emitting devices. The light-emitting devices of the light-emitting structure layer 30 may be organic light-emitting diodes (OLEDs) or quantum dot light-emitting diodes (QLEDs). The present disclosure does not limit the type of light-emitting devices. The light-emitting devices may include at least a first electrode, an organic light-emitting layer, and a second electrode. The first electrode may be connected to the second electrode of the transistor via a connecting electrode, the organic light-emitting layer may be connected to the first electrode, the second electrode may be connected to the organic light-emitting layer, and the second electrode may be connected to a second power line. The organic light-emitting layer emits light when driven by the first and second electrodes. The first electrode may be disposed on a side of the driving circuit layer 20 away from the base substrate 10, and the organic light-emitting layer and the second electrode may be stacked in sequence on the side of the first electrode away from the base substrate 10.

[0067] In an exemplary embodiment, the light emitting structure layer 30 may further include a pixel definition layer. A pixel opening is provided on the pixel definition layer of each sub-pixel. The pixel opening exposes the first electrode, so that the organic light emitting layer is connected to the first electrode through the pixel opening.

[0068] In an exemplary embodiment, since the organic light-emitting layer emits light in the pixel opening area set in the pixel definition layer, the sub-pixel may include a pixel light-emitting area and a pixel spacing area, the pixel light-emitting area is the light-emitting area, and the area outside the pixel opening is the pixel spacing area, and the pixel spacing area is located on the periphery of the light-emitting area.

[0069] In an exemplary embodiment, the first encapsulation layer 40 and the second encapsulation layer 60 can adopt a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the organic light-emitting layer. The cover layer 70 can be made of glass or a flexible plastic such as colorless polyimide.

[0070] In an exemplary embodiment, the color film structure layer 50 may include a black matrix (BM) and a color filter (CF), the color filters being respectively arranged in the red sub-pixel, the green sub-pixel and the blue sub-pixel to filter the white light emitted by the light-emitting device into red (R) light, green (G) light and blue (B) light, and the black matrix may be located between adjacent color filters.

[0071] In an exemplary embodiment, the organic light-emitting layer is configured to emit white light and can be prepared by evaporation or inkjet printing. The organic light-emitting layers of all sub-pixels can be a common layer connected together.

[0072] The resolution and brightness requirements for silicon-based OLED screens are increasing, exceeding 5000 nits and 3000 PPI, respectively. Sub-pixel pitches are approaching 1μm, exposing issues such as lateral leakage in some layers of the organic light-emitting layer and lateral current crosstalk between adjacent sub-pixels. Currently, various solutions have been proposed to address this lateral current crosstalk, such as adjusting pixel pitch and using highly conductive organic film materials. However, research has found that these solutions not only have limited effectiveness in cutting lateral leakage, but also affect the voltage of the light-emitting device, reducing luminous efficiency and resulting in significant brightness loss.

[0073] An embodiment of the present disclosure provides a display substrate, comprising a base substrate, a plurality of first electrodes arranged on the base substrate, and a plurality of pixel definition structures, wherein the pixel definition structures are arranged between adjacent first electrodes and form pixel openings exposing the first electrodes; in a direction perpendicular to the base substrate, the pixel definition structure comprises at least a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the base substrate do not overlap with the orthographic projections of the first electrode on the base substrate, and the orthographic projection of the second insulating layer on the base substrate at least partially overlaps with the orthographic projection of the first electrode on the base substrate; a surface of the second insulating layer away from the base substrate is provided with a second recess concave toward the base substrate, and an inner wall of the second recess close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate.

[0074] The display substrate provided in this embodiment can partition the organic light-emitting layer through the pixel definition structure to cut off lateral leakage, while preventing the second electrode from being broken, thereby improving the display effect.

[0075] In an exemplary embodiment, a second depth of the second recess is 0.01 μm to 0.06 μm, and the second depth is a maximum distance between an inner wall of the second recess close to the base substrate and a surface of the second insulating layer away from the base substrate.

[0076] In an exemplary embodiment, a surface of the first insulating layer away from the base substrate is flush with a surface of the first electrode away from the base substrate, and the surface of the first insulating layer away from the base substrate is lower than a surface of the first electrode away from the base substrate.

[0077] In an exemplary embodiment, a material of the third insulating layer is different from a material of the fourth insulating layer, and a material of the second insulating layer is the same as a material of the fourth insulating layer.

[0078] In an exemplary embodiment, the fourth insulating layer has a protrusion relative to the side wall of the third insulating layer, and the protrusion and the side wall of the third insulating layer form a first recess that is recessed away from the pixel opening, and a first depth of the first recess is greater than a second depth of the second recess, and the first depth is the maximum distance between the side wall of the fourth insulating layer close to the pixel opening and the side wall of the third insulating layer close to the pixel opening.

[0079] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer disposed on a side of the first electrode and the pixel definition structure away from the base substrate, the organic light-emitting layer including a plurality of film layers, at least one of which is disconnected at an edge of the fourth insulating layer, and the film layers of the organic light-emitting layer form a distortion region at the disconnection location.

[0080] Figure 4 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, and Figure 5 is an enlarged view of the pixel definition structure in Figure 4. As shown in Figures 4 and 5, the display substrate according to this exemplary embodiment may include a base substrate 10, a plurality of first electrodes 31 and a plurality of pixel definition structures 32 disposed on the base substrate 10, an organic light-emitting layer 33 disposed on a side of the first electrodes 31 and the pixel definition structures 32 away from the base substrate 10, and a second electrode 34 disposed on a side of the organic light-emitting layer 33 away from the base substrate 10.

[0081] In an exemplary embodiment, the pixel definition structure 32 is disposed between adjacent first electrodes 31 and forms a pixel opening 35 exposing the first electrode 31 . The pixel definition structure 32 may include a plurality of inorganic layers stacked on the base substrate 10 .

[0082] In an exemplary embodiment, the multiple inorganic layers of the pixel defining structure 32 may include at least a first insulating layer 101 disposed on the base substrate 10, a second insulating layer 102 disposed on a side of the first insulating layer 101 away from the base substrate 10, a third insulating layer 103 disposed on a side of the second insulating layer 102 away from the base substrate 10, and a fourth insulating layer 104 disposed on a side of the third insulating layer 103 away from the base substrate 10.

[0083] In an exemplary embodiment, the first insulating layer 101 is disposed between adjacent first electrodes 31 , the side surface of the first insulating layer 101 may be aligned with the side surface of the first electrode 31 , and the orthographic projection of the first insulating layer 101 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0084] In an exemplary embodiment, the surface of the first insulating layer 101 away from the base substrate 10 is substantially flush with the surface of the first electrode 31 away from the base substrate 10 , and the surface of the first insulating layer 101 away from the base substrate 10 is lower than the surface of the first electrode 31 away from the base substrate 10 .

[0085] In an exemplary embodiment, the first insulating layer 101 has a first width L1 , which is a dimension of the first insulating layer 101 in a direction parallel to the base substrate 10 .

[0086] In an exemplary embodiment, the first width L1 may be approximately 1.0 μm to 1.2 μm. For example, the first width L1 may be approximately 1.1 μm.

[0087] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the base substrate 10 , and the second insulating layer 102 has a second width L2 , which is the dimension of the second insulating layer 102 in a direction parallel to the base substrate 10 .

[0088] In an exemplary embodiment, the second width L2 of the second insulating layer 102 is greater than the first width L1 of the first insulating layer 101 , ie, L2 > L1 .

[0089] In an exemplary embodiment, the difference between the second width L2 and the first width L1 is greater than or equal to 0.1 μm. The second width L2 may be approximately 1.2 μm to 1.6 μm. For example, the second width L2 may be approximately 1.4 μm.

[0090] In an exemplary embodiment, the width of the overlapped region between the second insulating layer 102 and the first electrode 31 is greater than or equal to 0.1 μm, so that the second insulating layer 102 can effectively cover the edge of the first electrode 31. In other words, the pixel definition structure 32 does not expose the edge of the first electrode 31, which is achieved by forming the second insulating layer 102 wider than the first insulating layer 101.

[0091] In an exemplary embodiment, the difference between the second width L2 and the first width L1 may be approximately 0.3 μm, so that the second insulating layer 102 effectively covers a single side of the first electrode 31 by approximately 0.15 μm.

[0092] In an exemplary embodiment, the orthographic projection of the third insulating layer 103 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 , and the orthographic projection of the fourth insulating layer 104 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0093] In an exemplary embodiment, the material of the third insulating layer 103 can be different from the material of the fourth insulating layer 104, and the material of the second insulating layer 102 can be the same as the material of the fourth insulating layer 104. In this way, a recessed structure can be produced due to the difference in etching rates of the two materials. For example, the materials of the second insulating layer 102 and the fourth insulating layer 104 can both be silicon oxide (SiO X ), the material of the third insulating layer 103 can be silicon nitride (SiN X ).

[0094] In an exemplary embodiment, the third insulating layer 103 has a third width L3 , and the fourth insulating layer 104 has a fourth width L4 . The fourth width L4 may be greater than the third width L3 . The third width L3 and the fourth width L4 are dimensions parallel to the base substrate 10 .

[0095] In example embodiments, the third width L3 may be the minimum width of the third insulating layer 103 , and the fourth width L4 may be the maximum width of the fourth insulating layer 104 . Alternatively, the third width L3 may be the average width of the third insulating layer 103 , and the fourth width L4 may be the average width of the fourth insulating layer 104 .

[0096] In an exemplary embodiment, a difference between the fourth width L4 and the third width L3 may be approximately 0.1 μm to 0.4 μm.

[0097] In an exemplary embodiment, the third width L3 may be approximately 0.3 μm to 0.5 μm. In an exemplary embodiment, the third width L3 may be approximately 0.4 μm. The fourth width L4 may be approximately 0.5 μm to 0.7 μm. For example, the fourth width L4 may be approximately 0.6 μm.

[0098] In an exemplary embodiment, the fourth width L4 may be less than the first width L1, i.e., L4 < L1.

[0099] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, i.e., L4 < L2. The difference between the fourth width L4 and the second width L2 is greater than or equal to 0.3 μm.

[0100] In an exemplary embodiment, the fourth insulating layer 104 has a protrusion with respect to the sidewall of the third insulating layer 103, and the protrusion and the sidewall of the third insulating layer 103 form a first indentation 105 that is recessed away from the pixel opening 35. The first indentation 105 may be a curved surface shape with a curvature.

[0101] In an exemplary embodiment, the first indentation 105 may have a first depth ΔL. The first depth ΔL may be the maximum distance between the sidewall of the fourth insulating layer 104 on the side closer to the pixel opening 35 and the sidewall of the third insulating layer 103 on the side closer to the pixel opening 35. The first depth ΔL may be a dimension in the direction parallel to the substrate 10.

[0102] In an exemplary embodiment, the first depth ΔL of the first indentation 105 may be half of the difference between the fourth width L4 and the third width L3, where ΔL = (L4 - L3) / 2.

[0103] In an exemplary embodiment, the first depth ΔL of the first indentation 105 may be approximately 0.05 μm to 0.2 μm;

[0104] In an exemplary embodiment, the difference between the second width L2 and the fourth width L4 may be approximately 0.8 μm, such that the orthographic projection of the first indentation 105 on the substrate 10 and the orthographic projection of the pixel opening 35 on the substrate 10 do not overlap.

[0105] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, and the third width L3 may be less than the fourth width L4, i.e., L3 < L4 < L2.

[0106] In an exemplary embodiment, a second recess 106 is provided on the surface of the second insulating layer 102 facing away from the base substrate 10, and is recessed toward the base substrate 10. The inner wall of the second recess 106, which is located on the side of the second insulating layer 102 facing away from the base substrate 10, is located between the surface of the first electrode 31 facing away from the base substrate 10 and the surface of the first electrode 31 facing the base substrate 10. The second recess 106 may have a curved shape with a curvature. The second recess 106 may have a second depth ΔD, which may be the maximum distance between the inner wall of the second recess 106 facing away from the base substrate 10 and the surface of the second insulating layer 102 facing away from the base substrate 10. The second depth ΔD may be the dimension of the second recess in a direction perpendicular to the base substrate 10.

[0107] In an exemplary embodiment, the second depth ΔD of the second recess 106 may be approximately 0.01 μm to 0.06 μm; and the cross-sectional dimension of the second recess 106 gradually increases in a direction away from the base substrate 10 .

[0108] In an exemplary embodiment, the first depth ΔL of the first indentation 105 is greater than the second depth ΔD of the second indentation 106 .

[0109] In an exemplary embodiment, the first height ΔH of the first recess 105 is greater than the second depth ΔD of the second recess 106 . The first height ΔH of the first recess 105 is the maximum distance between the surface of the first recess 105 close to the base substrate 10 and the surface of the first recess 105 away from the base substrate 10 .

[0110] In an exemplary embodiment, a surface of the fourth insulating layer 104 facing away from the base substrate 10 is provided with a smooth third recess 109 that is recessed toward the base substrate 10. The third recess 109 may be a curved surface with a curvature. The curvature of the third recess 109 is smaller than that of the first recess 105 or the second recess 106.

[0111] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer 33 disposed on a side of the first electrode 31 and pixel definition structure 32 away from the base substrate 10. The organic light-emitting layer 33 includes multiple layers, at least one of which is disconnected at the edge of the fourth insulating layer 104. A distortion region 107 is defined at the disconnected portion of the organic light-emitting layer 33, as indicated by the dashed box. In an exemplary embodiment, the distortion region 107 may include at least one crack, with the organic light-emitting layer 33 on either side of the crack forming a step difference due to the disconnection.

[0112] In an exemplary embodiment, an orthographic projection of the distortion region 107 on the base substrate 10 does not overlap with an orthographic projection of the pixel opening 35 on the base substrate 10 .

[0113] In an exemplary embodiment, the display substrate further includes a second electrode 34 disposed on a side of the organic light-emitting layer 33 away from the base substrate 10. The second electrode 34 is provided with a puncture tip 108. The puncture tip 108 is disposed in a crack of the distortion region 107. The orthographic projection of the puncture tip 108 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10.

[0114] The orthographic projection of the endpoint of the puncture tip 108 on the base substrate 10 is within the range of the orthographic projection of the first insulating layer 101 on the base substrate 10 . The endpoint of the puncture tip 108 is the boundary point on the puncture tip 108 closest to the base substrate 10 .

[0115] In an exemplary embodiment, the first insulating layer 101 of the pixel definition structure 32 has a first thickness D1, the second insulating layer 102 has a second thickness D2, the third insulating layer 103 has a third thickness D3, and the fourth insulating layer 104 has a fourth thickness D4. The first thickness D1, the second thickness D2, the third thickness D3, and the fourth thickness D4 are dimensions perpendicular to the substrate 10. The first thickness D1 may be approximately 900 angstroms to 1100 angstroms, for example, approximately 1000 angstroms. The second thickness D2 may be approximately 300 angstroms to 500 angstroms, for example, approximately 400 angstroms. The third thickness D3 may be approximately 500 angstroms to 700 angstroms, for example, approximately 600 angstroms. The fourth thickness D4 may be approximately 100 angstroms to 300 angstroms, for example, approximately 200 angstroms.

[0116] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged on the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0117] In an exemplary embodiment, taking three sub-pixels of a display substrate as an example, a process of preparing the display substrate may include the following operations.

[0118] A. Forming a First Conductive Layer Pattern. In an exemplary embodiment, forming the first conductive layer pattern may include depositing a first conductive film on the base substrate 10 and patterning the first conductive film through a patterning process to form a first conductive layer pattern, wherein the first conductive layer pattern includes at least a first electrode 31 located in each sub-pixel, as shown in FIG6 .

[0119] In an exemplary embodiment, the first electrode 31 may be made of a metal material or a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the aforementioned metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the first electrode 31 may be a single-layer structure or a multi-layer composite structure. In an exemplary embodiment, the multi-layer composite structure may include a Ti layer, an Al layer, a titanium nitride (TiN) layer, and an ITO layer sequentially arranged in a direction away from the base substrate 10, which can meet the conventional requirements of high reflectivity, low roughness, and work function matching for light-emitting devices.

[0120] In an exemplary embodiment, the first electrode 31 has a first electrode thickness, which may be approximately 900 angstroms to 1100 angstroms, and the first electrode thickness is a dimension perpendicular to the base substrate 10. For example, the first thickness D1 may be approximately 1000 angstroms.

[0121] B. Forming a pixel definition structure pattern. In an exemplary embodiment, the pixel definition structure pattern includes at least a pixel definition structure 32 located in each sub-pixel, the pixel definition structure 32 being disposed between adjacent first electrodes 31 and forming a pixel opening that exposes the first electrode 31. Forming the pixel definition structure pattern may include:

[0122] B1. Forming a First Insulation Layer Pattern. In an exemplary embodiment, forming the first insulation layer pattern may include: first depositing a first insulation film on the substrate having the aforementioned pattern formed thereon, as shown in FIG7A . Subsequently, etching the first insulation film through a full-surface etch-back process to form a first insulation layer 101, as shown in FIG7B .

[0123] In an exemplary embodiment, the first insulating layer 101 is disposed between adjacent first electrodes 31 , the orthographic projection of the first insulating layer 101 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 , and the side surface of the first insulating layer 101 can be aligned with the side surface of the first electrode 31 .

[0124] In an exemplary embodiment, through a full-surface etching process, the surface of the first insulating layer 101 away from the base substrate 10 is substantially flush with the surface of the first electrode 31 away from the base substrate 10, and the surface of the first insulating layer 101 away from the base substrate 10 is lower than the surface of the first electrode 31 away from the base substrate 10.

[0125] In an exemplary embodiment, the first insulating layer 101 may be a planarization layer. The side surfaces of the first insulating layer 101 may be aligned with the side surfaces of the first electrode 31, forming a flat region of a predetermined width where the first insulating layer 101 and the first electrode contact each other. The first insulating layer 101 has a first width L1, which is a dimension parallel to the substrate 10. In an exemplary embodiment, the first width L1 may be approximately 1.0 μm to 1.2 μm. For example, the first width L1 may be approximately 1.1 μm.

[0126] In an exemplary embodiment, the first insulating layer 101 may have a first thickness D1. The first thickness D1 may be approximately 900 angstroms to 1100 angstroms. For example, the first thickness D1 may be approximately 1000 angstroms.

[0127] In an exemplary embodiment, the material of the first insulating layer 101 is an inorganic material, for example, the material of the first insulating layer 101 is silicon oxide (SiO X ).

[0128] B2. Forming Second, Third, and Fourth Insulating Film Patterns. In an exemplary embodiment, forming the second, third, and fourth insulating film patterns may include sequentially depositing the second, third, and fourth insulating films on the substrate having the aforementioned patterns formed thereon, as shown in FIG7C .

[0129] In an exemplary embodiment, the second insulating layer 102 in the pixel definition structure 32 has a second thickness D2, which is the dimension of the second insulating layer 102 in a direction perpendicular to the base substrate 10. Second thickness D2 may be approximately 300 to 500 angstroms. For example, second thickness D2 may be approximately 400 angstroms. In an exemplary embodiment, the third insulating layer 103 has a third thickness D3, which is the dimension of the third insulating layer 103 in a direction perpendicular to the base substrate 10. Third thickness D3 may be approximately 500 to 700 angstroms. For example, third thickness D3 may be approximately 600 angstroms. In an exemplary embodiment, the fourth insulating layer 104 has a fourth thickness D4, which is the dimension of the fourth insulating layer 104 in a direction perpendicular to the base substrate 10. Fourth thickness D4 may be approximately 100 to 300 angstroms. For example, fourth thickness D4 may be approximately 200 angstroms.

[0130] In an exemplary embodiment, the second insulating film, the third insulating film, and the fourth insulating film are all made of inorganic materials. The material of the third insulating film may be different from that of the fourth insulating film, and the material of the second insulating film may be the same as that of the fourth insulating film. For example, the second insulating film and the fourth insulating film are both made of silicon oxide (SiO X ), the material of the third insulating film is silicon nitride (SiN X ).

[0131] B3. First, a photoresist is coated on the fourth insulating film, and a first photoresist pattern 111 is formed by exposure and development, as shown in FIG7D.

[0132] In an exemplary embodiment, the first photoresist pattern 111 has a second width L2. The second width L2 is a dimension of the second photoresist pattern 112 in a direction parallel to the base substrate 10. The second width L2 may be greater than the first width L1. In an exemplary embodiment, the second width L2 may be approximately 1.2 μm to 1.6 μm. For example, the second width L2 may be approximately 1.4 μm.

[0133] Subsequently, the second insulating film, the third insulating film and the fourth insulating film that are not coated with the photoresist are etched to form a first transition pattern, as shown in FIG7E .

[0134] In example embodiments, the first transition pattern may include a stacked second insulating layer 102 , a third insulating layer 103 , and a fourth insulating layer 104 , the second insulating layer 102 , the third insulating layer 103 , and the fourth insulating layer 104 having substantially the same second width L2 .

[0135] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the base substrate 10 includes the orthographic projection of the first insulating layer 101 on the base substrate 10 , and the orthographic projection of the second insulating layer 102 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0136] In an exemplary embodiment, an orthographic projection of the second insulating layer 102 on the base substrate 10 at least partially overlaps an orthographic projection of the first electrode 31 on the base substrate 10 , and at least partially exposes the first electrode 31 .

[0137] In an exemplary embodiment, the difference between the second width L2 of the second insulating layer 102 and the first width L1 of the first insulating layer 101 is greater than or equal to 0.1 μm. The width of the overlapping region between the second insulating layer 102 and the first electrode 31 can be greater than 0.1 μm, allowing the second insulating layer 102 to effectively cover the edge of the first electrode 31. In other words, the pixel definition structure 32 does not expose the edge of the first electrode 31, which is achieved by forming the second insulating layer 102 wider than the first insulating layer 101.

[0138] In an exemplary embodiment, the difference between the second width L2 and the first width L1 may be approximately 0.3 μm, so that the second insulating layer 102 effectively covers a single side of the first electrode 31 by approximately 0.15 μm.

[0139] B4. First, a photoresist shrinking method is used to reduce the width of the photoresist pattern to form a second photoresist pattern 112, as shown in FIG. 7F.

[0140] In an exemplary embodiment, the second photoresist pattern 113 has a fourth width L4, which is a dimension of the third photoresist pattern 113 in a direction parallel to the base substrate 10. The fourth width L4 may be approximately 0.5 μm to 0.7 μm, for example, approximately 0.6 μm.

[0141] Subsequently, the exposed third insulating layer 103 and fourth insulating layer 104 are etched to form a second transition pattern, as shown in FIG7G .

[0142] In an exemplary embodiment, the second transition pattern may include a stacked third insulating layer 103 and a fourth insulating layer 104, and the third insulating layer 103 and the fourth insulating layer 104 have substantially the same fourth width L4.

[0143] In an exemplary embodiment, the orthographic projection of the third insulating layer 103 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10, and the orthographic projection of the fourth insulating layer 104 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10.

[0144] In an exemplary embodiment, the fourth width L4 may be less than the first width L1, i.e., L4 < L1.

[0145] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, i.e., L4 < L2. The difference between the fourth width L4 and the second width L2 may be greater than or equal to 0.3 μm.

[0146] Subsequently, by changing the ratio of the etching gas, the side surface of the third insulating layer 103 is etched so that the fourth insulating layer 104 has a protrusion with respect to the side wall of the third insulating layer 103, and the protrusion and the side wall of the third insulating layer 103 form a first indentation 105. In this etching process, the etching gas will etch the surface of the second insulating layer 102 on the side away from the substrate 10, and a second indentation 106 is formed on the surface of the second insulating layer 102. In this etching process, the etching gas will etch the surface of the fourth insulating layer 104 on the side away from the substrate 10 to form a third indentation 109. After removing the remaining photoresist, a pixel defining structure pattern is formed, as shown in FIG. 7H.

[0147] In an exemplary embodiment, the pixel defining structure 32 may include a second insulating layer 102, a third insulating layer 103, and a fourth insulating layer 104 sequentially disposed on the first insulating layer 101. The orthographic projection of the first insulating layer 101 on the substrate is within the range of the orthographic projection of the second insulating layer 102 on the substrate, the orthographic projection of the fourth insulating layer 104 on the substrate is within the range of the orthographic projection of the first insulating layer 101 on the substrate, and the orthographic projection of the third insulating layer 103 on the substrate is within the range of the orthographic projection of the fourth insulating layer 104 on the substrate.

[0148] In an exemplary embodiment, the first insulating layer 101 has a first width L1, the second insulating layer 102 has a second width L2, the third insulating layer 103 has a third width L3, and the fourth insulating layer 104 has a fourth width L4. In the exemplary embodiment, the first width L1 may be less than the second width L2, the fourth width L4 may be less than the first width L1, and the third width L3 may be less than the fourth width L4, that is, L3 < L4 < L1 < L2. The first width L1, the second width L2, the third width L3, and the fourth width L4 are dimensions in a direction parallel to the substrate 10.

[0149] In an exemplary embodiment, the third width L3 may be the minimum width of the third insulating layer 103, and the fourth width L4 may be the maximum width of the fourth insulating layer 104. Alternatively, the third width L3 may be the average width of the third insulating layer 103, and the fourth width L4 may be the average width of the fourth insulating layer 104.

[0150] In an exemplary embodiment, the difference between the fourth width L4 and the third width L3 may be approximately 0.1 μm to 0.4 μm. <​​​​​​​​​​​​​​​​​

[0157] In an exemplary embodiment, a second recess 106 is provided on the surface of the second insulating layer 102 facing away from the substrate 10, and is recessed toward the substrate 10. The inner wall of the second recess 106, which is located on the side of the second insulating layer 102 facing away from the substrate 10, is located between the surface of the first electrode 31 facing away from the substrate 10 and the surface of the first electrode 31 facing the substrate 10. The second recess 106 may have a curved surface shape. The second recess 106 may have a second depth ΔD, which may be the maximum distance between the inner wall of the second recess 106 facing the substrate 10 and the surface of the second insulating layer 102 facing away from the substrate 10. The second depth ΔD may be the dimension of the second recess in a direction perpendicular to the substrate 10.

[0158] In an exemplary embodiment, the second depth ΔD of the second recess 106 may be approximately 0.01 μm to 0.06 μm; and the cross-sectional dimension of the second recess 106 gradually increases in a direction away from the base substrate 10 .

[0159] In an exemplary embodiment, the first depth ΔL of the first indentation 105 is greater than the second depth ΔD of the second indentation 106 .

[0160] In an exemplary embodiment, a first height ΔH of the first recess 105 is greater than a second depth ΔD of the second recess 106 . The first height ΔH of the first recess 105 is the maximum distance between a surface of the first recess 105 close to the base substrate 10 and a surface of the first recess 105 away from the base substrate 10 .

[0161] In an exemplary embodiment, a surface of the fourth insulating layer 104 facing away from the base substrate 10 is provided with a smooth third recess 109 that is recessed toward the base substrate 10. The third recess 109 may be a curved surface with a curvature. The curvature of the third recess 109 is smaller than that of the first recess 105 or the second recess 106.

[0162] C. Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming the organic light-emitting layer pattern may include forming the organic light-emitting layer pattern by evaporation or the like, wherein the organic light-emitting layer 33 of each sub-pixel is connected to the first electrode 31 of the sub-pixel through the pixel opening 35 , as shown in FIG8 .

[0163] In an exemplary embodiment, the organic light-emitting layer 33 may include multiple film layers, at least one of which is disconnected at the edge of the fourth insulating layer 104. In an exemplary embodiment, a distortion region 107 is provided at the disconnected portion of the organic light-emitting layer 33. As shown in the dashed box, the organic light-emitting layer 33 is broken in the distortion region 107. In an exemplary embodiment, the distortion region 107 may include at least one crack, with the organic light-emitting layer 33 on both sides of the crack forming a step difference due to the disconnection.

[0164] In an exemplary embodiment, an orthographic projection of the distortion region 107 on the base substrate 10 does not overlap with an orthographic projection of the pixel opening 35 on the base substrate 10 .

[0165] D. Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include forming a second electrode 34 by evaporation or deposition, and the second electrode 34 is disposed on a side of the organic light-emitting layer 33 away from the base substrate 10 and is a full-surface structure, as shown in FIG9 .

[0166] In the exemplary embodiment, since the organic light emitting layer 33 is formed with the distorted region 107 , the second electrode 34 is provided with a puncture tip 108 , and the puncture tip 108 is disposed in a crack of the distorted region 107 .

[0167] The orthographic projection of the endpoint of the puncture tip 108 on the base substrate 10 is within the range of the orthographic projection of the first insulating layer 101 on the base substrate 10 . The endpoint of the puncture tip 108 is the boundary point on the puncture tip 108 closest to the base substrate 10 .

[0168] In an exemplary embodiment, the orthographic projection of the puncture tip 108 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0169] In an exemplary embodiment, the second electrode 34 may be made of a metal material or a transparent conductive material. The metal material may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or alloys thereof. The transparent conductive material may include indium zinc oxide (IZO). In an exemplary embodiment, the second electrode 34 may have a single-layer structure or a multi-layer composite structure, such as Mg / Ag.

[0170] In an exemplary embodiment, an optical coupling layer pattern can be formed after the second conductive layer pattern is formed. The optical coupling layer is arranged on the second electrode 34. The refractive index of the optical coupling layer can be greater than the refractive index of the second electrode 34, which is conducive to light extraction and increases the light extraction efficiency. The material of the optical coupling layer can be organic material, or inorganic material, or organic material and inorganic material, and can be a single layer, a multi-layer or a composite layer, which is not limited in the present disclosure.

[0171] At this point, the display substrate is prepared. The display substrate may include a base substrate 10 , a first electrode 31 , a pixel definition structure 32 , an organic light-emitting layer 33 and a second electrode 34 . The organic light-emitting layer 33 emits light under the drive of the first electrode 31 and the second electrode 34 .

[0172] Subsequent preparation may include processes such as forming a first encapsulation layer 40 , a color filter structure layer 50 , a second encapsulation layer 60 and a cover layer 70 , which will not be described in detail here.

[0173] The display substrate provided by the present disclosure is provided with a pixel definition structure including multiple insulating layers, and a second recess is formed on the second insulating layer in the pixel definition structure, and the inner wall of the second recess close to the side of the base substrate is located between the upper surface and the lower surface of the first electrode, which can ensure that while the pixel definition structure isolates the organic light-emitting layer, the second electrode is prevented from being broken, thereby ensuring the continuity of the second electrode. The pixel definition structure proposed in the present disclosure forms a first recess on the side wall of the pixel definition structure, so that the organic light-emitting layer is disconnected at the edge of the pixel definition structure, which can effectively block the lateral current in the organic light-emitting layer. The pixel definition structure proposed in the present disclosure forms a distortion area in the organic light-emitting layer, and the orthographic projection of the distortion area on the base substrate does not overlap with the orthographic projection of the pixel opening on the base substrate, that is, the distortion area is located outside the pixel opening and away from the effective light-emitting area, thereby improving the light-emitting efficiency and reducing the brightness loss. The pixel definition structure proposed in the present disclosure ensures that the orthographic projection of the puncture tip of the second electrode on the substrate does not overlap with the orthographic projection of the first electrode on the substrate, that is, the puncture tip is located outside the area where the first electrode is located, which can effectively avoid a short circuit between the second electrode and the first electrode. By arranging the puncture tip within the area where the flat first insulating layer is located, the continuity of the second electrode can be further ensured, and no virtual connection or disconnection occurs.

[0174] The organic light-emitting layer is disconnected at the edge of the pixel definition structure, which can effectively avoid the crosstalk caused by the carrier transfer of the charge generation layer, greatly reduce the risk of longitudinal leakage of the organic light-emitting device, improve the luminous efficiency and enhance the display effect.

[0175] Figure 10 is a schematic diagram of the structure of an organic light-emitting layer according to an exemplary embodiment of the present disclosure. As shown in Figure 10, the organic light-emitting layer 33 may include a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer disposed between a first electrode and a second electrode.

[0176] FIG. 11 is a schematic structural view of another organic light-emitting layer according to an exemplary embodiment of the present disclosure. As shown in FIG. 11, the organic light-emitting layer 33 may include a first device 33-1, a charge generation layer 33-2, and a second device 33-3 disposed between the first electrode and the second electrode. Both the first device 33-1 and the second device 33-3 include a stacked hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0177] In an exemplary embodiment, in a direction perpendicular to the substrate 10, the first device 33-1 and the charge generation layer 33-2 have a first device thickness T1, and the second stacked device 33-3 has a second thickness T2. The first device thickness T1 may be less than the second device thickness T2, that is, T1 < T2.

[0178] In an exemplary embodiment, the first device thickness T1 may be less than half of the second device thickness T2, T1 < 1 / 2 * T2, to ensure that the inscribed structure effectively isolates the organic light-emitting layer 33 while preventing virtual connection or breakage of the second electrode 34.

[0179] In an exemplary embodiment, a third thickness D3 may be less than the first device thickness T1 and greater than half of the first device thickness T1, that is, 1 / 2 * T1 < D3 < T1, to ensure that at least one film layer in the organic light-emitting layer 33 is disconnected at a position corresponding to the pixel definition structure 32, especially to isolate the charge generation layer 33-2 in the organic light-emitting layer 33.

[0180] In an exemplary embodiment, the total thickness of the organic light-emitting layer 33 may be about 2900 Å to 3100 Å, where the first device thickness T1 may be about 900 Å, and the second device thickness T2 may be about 2100 Å.

[0181] It has been found through research that not only does the width of the inorganic layer in the pixel definition structure affect the efficiency and lifespan of the light-emitting device, but the thickness of the organic light-emitting layer is also a factor affecting the quality of the light-emitting device. By setting the thickness relationship between the third insulating layer and the organic light-emitting layer, the present disclosure not only further effectively blocks lateral leakage between pixels, but also reduces longitudinal leakage caused by distortion of the organic light-emitting layer.

[0182] The disclosed exemplary embodiments also provide a method for preparing a display substrate. In an exemplary embodiment, the preparation method includes: forming a plurality of first electrodes and a plurality of pixel definition structures on a base substrate; the pixel definition structures are arranged between adjacent first electrodes and form pixel openings exposing the first electrodes; in a direction perpendicular to the base substrate, the pixel definition structures include at least a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the base substrate do not overlap with the orthographic projections of the first electrodes on the base substrate, and the orthographic projections of the second insulating layer on the base substrate at least partially overlap with the orthographic projections of the first electrodes on the base substrate; a second indentation is provided on a surface of the second insulating layer away from the base substrate that is concave toward the base substrate, and an inner wall of the second indentation on a side close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate.

[0183] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0184] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising a base substrate, a plurality of first electrodes arranged on the base substrate, and a plurality of pixel definition structures, wherein the pixel definition structures are arranged between adjacent first electrodes and form pixel openings exposing the first electrodes; in a direction perpendicular to the base substrate, the pixel definition structures at least include a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the base substrate do not overlap with the orthographic projections of the first electrode on the base substrate, and the orthographic projections of the second insulating layer on the base substrate at least partially overlap with the orthographic projections of the first electrode on the base substrate; a second recessed portion concave toward the base substrate is arranged on a surface of the second insulating layer away from the base substrate, and an inner wall of the second recessed portion close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate.

2. The display substrate according to claim 1, wherein: The second depth of the second recess is 0.01 μm to 0.06 μm, and the second depth is the maximum distance between an inner wall of the second recess close to the base substrate and a surface of the second insulating layer away from the base substrate.

3. The display substrate according to claim 1, wherein: The surface of the first insulating layer away from the base substrate is flush with the surface of the first electrode away from the base substrate, or the surface of the first insulating layer away from the base substrate is lower than the surface of the first electrode away from the base substrate.

4. The display substrate according to claim 1, wherein: The first insulating layer has a first width, the second insulating layer has a second width, the second width is greater than the first width, and the first width and the second width are dimensions in a direction parallel to the substrate.

5. The display substrate according to claim 4, wherein: A difference between the second width and the first width is greater than or equal to 0.1 μm.

6. The display substrate according to claim 1, wherein: The material of the third insulating layer is different from that of the fourth insulating layer, and the material of the second insulating layer is the same as that of the fourth insulating layer.

7. The display substrate according to claim 4, wherein: The third insulating layer has a third width, the fourth insulating layer has a fourth width, the fourth width is smaller than the second width, the fourth width is smaller than the first width, the third width is smaller than the fourth width, and the third width and the fourth width are dimensions parallel to the direction of the substrate.

8. The display substrate according to claim 7, wherein: A difference between the fourth width and the second width is greater than or equal to 0.3 μm, and a difference between the fourth width and the third width is 0.1 μm to 0.4 μm.

9. The display substrate according to claim 2, wherein: The fourth insulating layer has a protrusion relative to the side wall of the third insulating layer, and the protrusion and the side wall of the third insulating layer form a first recess that is recessed in a direction away from the pixel opening. A first depth of the first recess is greater than a second depth of the second recess. The first depth is the maximum distance between the side wall of the fourth insulating layer close to the pixel opening and the side wall of the third insulating layer close to the pixel opening.

10. The display substrate according to claim 9, wherein: The first depth of the first recess is 0.05 μm to 0.2 μm.

11. The display substrate according to claim 9, wherein: The first height of the first recess is greater than the second depth of the second recess. The first height of the first recess is the maximum distance between a surface of the first recess close to the substrate and a surface of the first recess away from the substrate.

12. The display substrate according to claim 11, wherein: A smooth third recessed portion that is recessed toward the base substrate is disposed on a surface of the fourth insulating layer that is away from the base substrate.

13. The display substrate according to claim 12, wherein: A curvature of the third indentation is smaller than a curvature of the first indentation or a curvature of the second indentation.

14. The display substrate according to any one of claims 1 to 13, wherein: The display substrate also includes an organic light-emitting layer arranged on the side of the first electrode and the pixel definition structure away from the base substrate, the organic light-emitting layer includes multiple film layers, at least one film layer is disconnected at the edge of the fourth insulating layer, and a distortion region is set at the disconnected film layer of the organic light-emitting layer.

15. The display substrate according to claim 14, wherein: The distortion region may include at least one crack, and an orthographic projection of the distortion region on the substrate does not overlap with an orthographic projection of the pixel opening on the substrate.

16. The display substrate according to claim 15, wherein: The display substrate further comprises a second electrode disposed on a side of the organic light emitting layer away from the base substrate, the second electrode being provided with a puncture tip, the puncture tip being disposed in a crack of the distortion region, and an orthographic projection of the puncture tip on the base substrate not overlapping with an orthographic projection of the first electrode on the base substrate; The orthographic projection of the endpoint of the puncture tip on the substrate is located within the range of the orthographic projection of the first insulating layer on the substrate, and the endpoint of the puncture tip is the boundary point on the puncture tip that is closest to the substrate.

17. The display substrate according to claim 14, wherein: The organic light-emitting layer includes a first device, a charge generating layer, and a second device stacked together, the first device and the charge generating layer have a first device thickness, the second device has a second device thickness, the first device thickness is less than the second device thickness, and the first device thickness and the second device thickness are dimensions perpendicular to the substrate direction.

18. The display substrate according to claim 17, wherein: The thickness of the first device is less than 1 / 2*the thickness of the second device.

19. The display substrate according to claim 17, wherein: The third insulating layer has a third thickness D3, which is a dimension in a direction perpendicular to the substrate; the third thickness is less than the first device thickness, and the third thickness is greater than 1 / 2*the first device thickness.

20. A display device, wherein: The invention comprises the display substrate as claimed in any one of claims 1 to 19.

21. A method for preparing a display substrate, wherein: The preparation method comprises: A plurality of first electrodes and a plurality of pixel definition structures are formed on a base substrate, wherein the pixel definition structures are arranged between adjacent first electrodes and form pixel openings exposing the first electrodes; in a direction perpendicular to the base substrate, the pixel definition structures at least include a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer and the fourth insulating layer on the base substrate do not overlap with the orthographic projections of the first electrode on the base substrate, and the orthographic projections of the second insulating layer on the base substrate at least partially overlap with the orthographic projections of the first electrode on the base substrate; a second recessed portion concave toward the base substrate is arranged on a surface of the second insulating layer away from the base substrate, and an inner wall of the second recessed portion close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate.

Images