Display device

Abstract

The invention proposes a display device. This display device comprises: a substrate; a first conductive layer arranged on the substrate; an active layer arranged on the first conductive layer; a second conductive layer arranged on the active layer, consisting of a transparent conductive oxide (TCO) and excluding indium (In); a third conductive layer arranged on the second conductive layer; a transistor comprising a gate electrode arranged in the second conductive layer, and a drain and source electrode arranged in the active layer; and a light-emitting element comprising a first electrode arranged in the third conductive layer and connected to the source electrode.

Description

display device

[0001] The present invention relates to a display device.

[0002] Display devices are becoming increasingly important with the advancement of multimedia. In response, various display devices, such as liquid crystal display devices (LCDs) and organic light-emitting diode display devices (OLEDs), are being developed.

[0003] Among display devices, a self-luminous display device includes a self-luminous element, for example, an organic light-emitting element. The self-luminous element may include two opposing electrodes and a light-emitting layer interposed therebetween. When the self-luminous element is an organic light-emitting element, electrons and holes provided from the two electrodes recombine in the light-emitting layer to generate excitons, and the generated excitons may change from an excited state to a ground state, thereby emitting light.

[0004] Self-luminous display devices are attracting attention as next-generation display devices because they do not require a light source such as a backlight unit, so they can be configured as thin and lightweight devices with low power consumption, and they also have high-quality characteristics such as a wide viewing angle, high brightness and contrast, and fast response speed.

[0005] A self-luminous display device may include various circuit layers for driving a light-emitting layer. These circuit layers may be formed through multiple patterning processes using masks. Process efficiency can be improved as the number of masks and the number of layers constituting the circuit layer decreases. Consequently, the height difference between the light-emitting layer and the transistors driving it can be reduced.

[0006] The problem to be solved by the present invention is to provide a display device including a conductive layer with low reflectivity.

[0007] Another problem that the present invention seeks to solve is to provide a display device that reduces or minimizes the photothermal phenomenon.

[0008] Another problem that the present invention seeks to solve is to provide a display device with improved reliability.

[0009] Another problem that the present invention seeks to solve is to provide a display device with improved process efficiency of the display device.

[0010] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0011] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate, a first conductive layer disposed on the substrate, an active layer disposed on the first conductive layer, a second conductive layer disposed on the active layer, a third conductive layer disposed on the second conductive layer, a transistor including a gate electrode disposed on the second conductive layer, and a drain electrode and a source electrode disposed on the active layer, and a light-emitting element including a first electrode disposed on the third conductive layer and connected to the source electrode, wherein the second conductive layer includes a transparent conductive oxide (TCO) and does not include indium (In).

[0012] The second conductive layer may include aluminum-zinc-tin-oxide (AZTO).

[0013] The second conductive layer includes a first gate conductive layer and a second gate conductive layer disposed on the first gate conductive layer, and the second gate conductive layer can have a higher light transmittance than the first gate conductive layer.

[0014] The second gate conductive layer may include aluminum-zinc-tin-oxide (AZTO).

[0015] The second gate conductive layer may include 1 at% to 10 at% of aluminum relative to the remaining atoms excluding oxygen atoms.

[0016] The above second gate conductive layer may contain zinc in an amount of 60 at% to 90 at% relative to the remaining atoms excluding oxygen atoms.

[0017] The second gate conductive layer may include 10 at% to 30 at% of tin relative to the remaining atoms excluding oxygen atoms.

[0018] The second gate conductive layer may contain 0.5 at% to 5 at% of aluminum relative to the total atoms.

[0019] The second gate conductive layer may contain zinc in an amount of 20 at% to 40 at% relative to the total atoms.

[0020] The second gate conductive layer may contain 7 at% to 15 at% of tin relative to the total atoms.

[0021] The above second gate conductive layer may contain 50 at% to 60 at% of oxygen relative to the total atoms.

[0022] The first gate conductive layer may have a lower reflectivity than the second gate conductive layer.

[0023] The above first gate conductive layer may include titanium (Ti).

[0024] The thickness of the second gate conductive layer may be thicker than the thickness of the first gate conductive layer.

[0025] The thickness of the second gate conductive layer may be 2 to 30 times the thickness of the first gate conductive layer.

[0026] The thickness of the second gate conductive layer may be 400Å to 3000Å.

[0027] The thickness of the first gate conductive layer may be 100Å to 200Å.

[0028] The third conductive layer includes a transparent conductive oxide (TCO), and the transparent conductive oxide (TCO) of the second conductive layer and the transparent conductive oxide (TCO) of the third conductive layer may be different materials.

[0029] The second conductive layer may have a lower reflectivity than at least one of the first conductive layer and the third conductive layer.

[0030] According to another embodiment for solving the above problem, a display device includes a substrate, a first conductive layer disposed on the substrate, an active layer disposed on the first conductive layer, a second conductive layer disposed on the active layer, a transistor disposed on the first conductive layer, and a light-emitting element disposed on the second conductive layer and connected to the transistor, wherein the second conductive layer includes a first gate conductive layer including a first material, a second gate conductive layer disposed on the first gate conductive layer and including a second material, a third gate conductive layer disposed on the second gate conductive layer and including a third material, and a fourth gate conductive layer disposed on the third gate conductive layer and including aluminum-zinc-tin-oxide (AZTO), wherein the first to third materials include metals.

[0031] The first to third materials may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0032] The first material may include titanium (Ti).

[0033] The second material may include copper (Cu).

[0034] The third material may include titanium (Ti).

[0035] The thickness of the fourth gate conductive layer may be thicker than the thickness of the third gate conductive layer.

[0036] The thickness of the second gate conductive layer may be thicker than the thickness of the fourth gate conductive layer.

[0037] According to another embodiment for solving the above problem, a display device includes a substrate including a display area and a pad area disposed on one side of the display area, a first conductive layer disposed on the substrate, an active layer disposed on the first conductive layer, a second conductive layer disposed on the active layer, a transistor disposed on the first conductive layer in the display area, a light-emitting element disposed on the second conductive layer in the display area and connected to the transistor, and a wiring pad disposed on the substrate in the pad area, wherein the wiring pad includes a first pad electrode disposed on the first conductive layer and a second pad electrode disposed on the second conductive layer, and wherein the second conductive layer disposed in the display area includes a transparent conductive oxide and does not include indium (In).

[0038] The above second pad electrode may not include a transparent conductive oxide.

[0039] The second pad electrode may further include a driving component connected to the wiring pad, and the second pad electrode may include a sub-pad layer in direct contact with the driving component, and the sub-pad layer may include a metal.

[0040] According to one or more embodiments of the present invention, a display device may include a conductive layer having low reflectivity.

[0041] According to a display device according to one or more embodiments of the present invention, the photodegradation phenomenon can be reduced or minimized.

[0042] According to a display device according to one or more embodiments of the present invention, the reliability of the display device can be improved.

[0043] According to a display device according to one or more embodiments of the present invention, the process efficiency of the display device can be improved.

[0044] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0045] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0046] Figure 2 is a cross-sectional view taken along line X1-X1' of Figure 1.

[0047] Fig. 3 is a cross-sectional view showing a display device according to another embodiment.

[0048] FIG. 4 is a plan view showing a state in which a flexible film is attached to a wiring pad of a display device according to one embodiment.

[0049] FIG. 5 is a plan view showing a state in which a flexible film is not attached to a wiring pad of a display device according to one embodiment.

[0050] FIG. 6 is a drawing showing pixels and wirings of a display device according to one embodiment.

[0051] FIG. 7 is a plan view schematically illustrating a portion of a display area of ​​a display substrate according to one embodiment.

[0052] FIG. 8 is a plan view schematically illustrating a portion of a display area of ​​a display substrate according to another embodiment.

[0053] Fig. 9 is a cross-sectional view taken along line X2-X2' of Fig. 8.

[0054] Fig. 10 is an equivalent circuit diagram of a pixel according to one embodiment.

[0055] FIG. 11 is a cross-sectional view showing an example of a first transistor of a circuit layer according to one embodiment.

[0056] FIG. 12 is a cross-sectional view showing an example of a second transistor and a third transistor of a circuit layer according to one embodiment.

[0057] FIG. 13 is a cross-sectional view showing an example of a portion of a display area and a portion of a pad area of ​​a display device according to one embodiment.

[0058] Fig. 14 is a cross-sectional view showing an example of a lower conductive layer according to one embodiment.

[0059] Fig. 15 is a cross-sectional view showing an example of a gate conductive layer according to one embodiment.

[0060] Fig. 16 is a cross-sectional view showing an example of an anode conductive layer according to one embodiment.

[0061] Fig. 17 is a cross-sectional view showing an example of a gate conductive layer according to a conventional embodiment.

[0062] Fig. 18 is a photograph showing precipitated particles formed on a cross-section of a gate conductive layer according to a conventional embodiment.

[0063] FIG. 19 is a cross-sectional view showing an example of a portion of a display area and a portion of a pad area of ​​a display device according to another embodiment.

[0064] Fig. 20 is a cross-sectional view showing a wiring pad and a flexible film of a display device according to another embodiment.

[0065] FIGS. 21 to 23 are schematic perspective views showing a device including a display device according to one embodiment.

[0066] FIGS. 24 and 25 are schematic perspective views showing a transparent display device including a display device according to one embodiment.

[0067] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0068] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, references to "below," "left," and "right" include both cases where the other element or layer is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0069] Specific embodiments are described below with reference to the attached drawings.

[0070] Fig. 1 is a perspective view showing a display device according to one embodiment. Fig. 2 is a cross-sectional view taken along line X1-X1' of Fig. 1. Fig. 3 is a cross-sectional view showing a display device according to another embodiment.

[0071] Referring to FIGS. 1 to 3, the display device (10) can be applied to various electronic devices, such as tablet PCs, smart phones, car navigation units, cameras, center information displays (CIDs) provided in cars, wristwatch-type electronic devices, PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), small and medium-sized electronic devices such as game consoles, televisions, outdoor billboards, monitors, personal computers, and laptop computers, and medium and large-sized electronic devices such as laptop computers. These are presented only as examples, and can be employed in other electronic devices as long as they do not deviate from the concept of the present invention.

[0072] In one embodiment, the display device (10) may have a rectangular shape in plan view. The display device (10) may include two long sides extending in a first direction (DR1) and two short sides extending in a second direction (DR2) intersecting the first direction (DR1). An edge where the long side and the short side of the display device (10) meet may be a right angle, but is not limited thereto, and may also form a curved surface. In another embodiment, the long side may extend in the second direction (DR2), and the short side may extend in the first direction (DR1). The plan view of the display device (10) is not limited to the illustrated shape, and may be applied in a circular or other shape.

[0073] In the illustrated drawing, the first direction (DR1) and the second direction (DR2) are horizontal directions and intersect each other. For example, the first direction (DR1) and the second direction (DR2) may be orthogonal to each other. In addition, the third direction (DR3) intersects the first direction (DR1) and the second direction (DR2), and may be, for example, a vertical direction that is orthogonal to the first direction (DR1) and the second direction (DR2). Unless otherwise defined, in this specification, the direction indicated by the arrows of the first to third directions (DR1, DR2, DR3) may be referred to as one side, and the opposite direction may be referred to as the other side. In addition, in this specification, “upper”, “upper side”, “top”, “top”, and “top surface” refer to the direction in which the arrow in the drawing is directed among the third directions (DR3) based on the drawing, and “lower”, “lower side”, “lower”, “bottom”, and “lower side” refer to the opposite direction to the direction in which the arrow of the third direction (DR3) is directed based on the drawing.

[0074] The display device (10) may include a display area (DA) that displays an image and a non-display area (NDA) that does not display an image. In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0075] In one embodiment, as illustrated in FIG. 2, the display device (10) includes a display substrate (100), a color conversion substrate (200) facing the display substrate (100), and may further include a sealing portion (400) that connects the display substrate (100) and the color conversion substrate (200), and a filler (300) filled between the display substrate (100) and the color conversion substrate (200).

[0076] The display substrate (100) may include elements and circuits for displaying an image, for example, pixel circuits such as switching elements, a pixel defining film defining a light-emitting region and a non-light-emitting region in a display area (DA) to be described later, and a self-light emitting element. In one embodiment, the self-light emitting element may include at least one of an organic light emitting diode, a quantum dot light emitting diode, an inorganic-based micro light emitting diode (e.g., Micro LED), and an inorganic-based nano light emitting diode (e.g., nano LED). For the convenience of the following description, an example in which the self-light emitting element is an organic light emitting element will be described.

[0077] The color conversion substrate (200) may be positioned on the display substrate (100) and may face the display substrate (100). In one embodiment, the color conversion substrate (200) may include a color conversion pattern that converts the color of incident light. In one embodiment, the color conversion pattern may include at least one of a color filter and a wavelength conversion pattern.

[0078] A sealing portion (400) may be positioned between the display substrate (100) and the color conversion substrate (200) in the non-display area (NDA). The sealing portion (400) may be positioned along the edges of the display substrate (100) and the color conversion substrate (200) in the non-display area (NDA) to surround the display area (DA) on a plane. The display substrate (100) and the color conversion substrate (200) may be mutually coupled via the sealing portion (400).

[0079] In one embodiment, the sealing portion (400) may be made of an organic material. For example, the sealing portion (400) may be made of an epoxy resin, but is not limited thereto.

[0080] A filler (300) may be positioned in the space between the display substrate (100) and the color conversion substrate (200) surrounded by the sealing portion (400). The filler (300) may fill the space between the display substrate (100) and the color conversion substrate (200).

[0081] In one embodiment, the filler (300) may be formed of a material that can transmit light. In one embodiment, the filler (300) may be formed of an organic material. For example, the filler (300) may be formed of a silicone-based organic material, an epoxy-based organic material, or the like, but is not limited thereto. In another embodiment, the filler (300) may be omitted.

[0082] In another embodiment, as illustrated in FIG. 3, the display device (10_1) may not include a sealing portion (400). For example, the color conversion substrate (200_1) of the display device (10_1) may be a sealing substrate. The color conversion substrate (200_1) may include a protrusion disposed along the periphery of the color conversion substrate (200_1) and protruding toward the display substrate (100) in the third direction (DR3), and a recess surrounded by the protrusion. The internal space may be sealed by the display substrate (100), the color conversion substrate (200_1), and the protrusion. The filler (300) may be filled in the recess.

[0083] Fig. 4 is a plan view showing a state in which a flexible film is attached to a wiring pad of a display device according to one embodiment. Fig. 5 is a plan view showing a state in which a flexible film is not attached to a wiring pad of a display device according to one embodiment.

[0084] Referring to FIGS. 4 and 5, the display device (10) may include a display substrate (100), a connecting film (510), a display driver (520), a circuit board (530), a timing control unit (540), a power supply unit (550), and a gate driver unit (560).

[0085] The display substrate (100) may be formed in a rectangular shape on a plane. For example, the display substrate (100) may have a rectangular shape on a plane having a long side in a first direction (DR1) and a short side in a second direction (DR2). An edge where the long side in the first direction (DR1) and the short side in the second direction (DR2) meet may be formed at a right angle or may be formed to have a round shape with a predetermined curvature. The plane shape of the display substrate (100) is not limited to a rectangle, and may be formed in another polygonal, circular, or oval shape. For example, the display substrate (100) may be formed flat, but is not limited thereto. As another example, the display substrate (100) may be formed to be bent with a predetermined curvature.

[0086] The display substrate (100) may include a display area (DA) and a non-display area (NDA).

[0087] The display area (DA) is an area for displaying an image and may be defined as a central area of ​​the display substrate (100). In one embodiment, the display area (DA) may include a pixel (SP), a gate line (GL), a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), a horizontal voltage line (HVDL), a vertical voltage line (VVSL), and a second voltage line (VSL).

[0088] A pixel (SP) may be formed in each pixel area intersected by data lines (DLs) and gate lines (GLs). In one embodiment, the pixel (SP) may include first to third pixels (SP1, SP2, SP3). Each of the first to third pixels (SP1, SP2, SP3) may be connected to a gate line (GL) and a data line (DL). Each of the first to third pixels (SP1, SP2, SP3) may be defined as a minimum unit area that outputs light.

[0089] Each of the first to third pixels (SP1, SP2, SP3) may include an organic light emitting diode (OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, a micro LED, or an inorganic LED including an inorganic semiconductor.

[0090] A first pixel (SP1) can emit light of a first color or red light, a second pixel (SP2) can emit light of a second color or green light, and a third pixel (SP3) can emit light of a third color or blue light. The pixel circuit of the first pixel (SP1), the pixel circuit of the second pixel (SP2), and the pixel circuit of the third pixel (SP3) can be arranged in order in a direction opposite to the second direction (DR2), but the order of the pixel circuits is not limited thereto.

[0091] The gate line (GL) may include a first gate line (GL1) and a second gate line (GL2). The first gate lines (GL1) may extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). The first gate line (GL1) may receive a first gate signal from the gate driver (560) and supply the first gate signal to the first to third pixels (SP1, SP2, SP3).

[0092] The second gate lines (GL2) may extend in the first direction (DR1) and be spaced apart from each other in the second direction (DR2). The second gate line (GL2) may receive a second gate signal from the gate driver (560) and supply the second gate signal to the first to third pixels (SP1, SP2, SP3).

[0093] The data lines (DL) may extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1). The data lines (DL) may include first to third data lines (DL1, DL2, DL3). Each of the first to third data lines (DL1, DL2, DL3) may supply a data voltage to each of the first to third pixels (SP1, SP2, SP3).

[0094] The initialization voltage lines (VIL) may extend in the second direction (DR2) and be spaced apart from each other in the first direction (DR1). The initialization voltage lines (VIL) may supply the initialization voltage received from the display driver (520) to the pixel circuits of each of the first to third pixels (SP1, SP2, SP3). The initialization voltage lines (VIL) may receive sensing signals from the pixel circuits of each of the first to third pixels (SP1, SP2, SP3) and supply them to the display driver (520).

[0095] The first voltage lines (VDLs) may extend in the second direction (DR2) and be spaced apart from each other in the first direction (DR1). The first voltage lines (VDLs) may supply a driving voltage or a high-potential voltage received from a power supply unit (550) to the first to third pixels (SP1, SP2, SP3).

[0096] The horizontal voltage lines (HVDLs) can extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). The horizontal voltage lines (HVDLs) can be connected to the first voltage line (VDL). The horizontal voltage lines (HVDLs) can receive a driving voltage or a high-potential voltage from the first voltage line (VDL).

[0097] The vertical voltage lines (VVSL) may extend in the second direction (DR2) and be spaced apart from each other in the first direction (DR1). The vertical voltage lines (VVSL) may be connected to the second voltage lines (VSL). The vertical voltage lines (VVSL) may supply a low-potential voltage received from the power supply unit (550) to the second voltage lines (VSL).

[0098] The second voltage lines (VSL) can extend in the first direction (DR1) and be spaced apart from each other in the second direction (DR2). The second voltage lines (VSL) can supply a low voltage to the first to third pixels (SP1, SP2, SP3).

[0099] The connection relationship of the pixel (SP), gate line (GL), data line (DL), initialization voltage line (VIL), first voltage line (VDL), horizontal voltage line (HVDL), vertical voltage line (VVSL), and second voltage line (VSL) can be designed to vary depending on the number and arrangement of pixels (SP).

[0100] A non-display area (NDA) may be defined as an area remaining in the display substrate (100) excluding the display area (DA). For example, the non-display area (NDA) may include fan out lines connecting a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), and a vertical voltage line (VVSL) to a display driver (520), a gate driver (560), and a wiring pad (WPD) connected to a connection film (510).

[0101] The non-display area (NDA) may include a pad area (PDA), which is an area where a wiring pad (WPD) is placed. The pad area (PDA) may be positioned adjacent to one side of the display device (10). For example, the pad area (PDA) may be positioned adjacent to the lower side of the display device (10). In one embodiment, the pad area (PDA) may extend along the first direction (DR1).

[0102] The connecting film (510) can be connected to a wiring pad (WPD) positioned on the lower side of the non-display area (NDA) and a board pad (BPD) positioned on the upper side of the circuit board (530). For example, input terminals provided on one side and the other side of the connecting film (510), such as bumps (512) (see FIG. 20), can be attached to the wiring pad (WPD) and the board pad (BPD) by a film attachment process. For example, the connecting film (510) can be bent, such as a tape carrier package or a chip on film. The connecting film (510) can be bent to the lower side of the display substrate (100) to reduce the bezel area of ​​the display device (10).

[0103] The display driver (520) may be mounted on the connecting film (510). For example, the display driver (520) may be implemented as an integrated circuit (IC). The display driver (520) may receive digital video data and a data control signal from the timing control unit (540), and may convert the digital video data into an analog data voltage according to the data control signal and supply the converted digital video data to the data lines (DL) through the fan-out lines.

[0104] The circuit board (530) supports the timing control unit (540) and the power supply unit (550), and can supply signals and power to the display driver unit (520). For example, the circuit board (530) can supply a signal supplied from the timing control unit (540) and a power voltage supplied from the power supply unit (550) to the connection film (510) and the display driver unit (520) through the board pad (BPD) to display an image on each pixel. For this purpose, signal lines and power lines can be provided on the circuit board (530).

[0105] The timing control unit (540) is mounted on the circuit board (530) and can receive image data and a timing synchronization signal supplied from a display driving system or a graphic device through a user connector provided on the circuit board (530). The timing control unit (540) can align the image data to a pixel arrangement structure based on the timing synchronization signal to generate digital video data, and can supply the generated digital video data to the display driving unit (520). The timing control unit (540) can generate a data control signal and a gate control signal based on the timing synchronization signal. The timing control unit (540) can control the supply timing of the data voltage of the display driving unit (520) based on the data control signal, and can control the supply timing of the gate signal of the gate driving unit (560) based on the gate control signal.

[0106] The power supply unit (550) can be arranged on the circuit board (530) to supply power voltage to the connection film (510) and the display driver (520). For example, the power supply unit (550) can generate a driving voltage or a high-potential voltage and supply it to the first voltage line (VDL), generate a low-potential voltage and supply it to the vertical voltage line (VVSL), and generate an initialization voltage and supply it to the initialization voltage line (VIL).

[0107] The gate driver (560) may be positioned on at least one of the left and right sides of the non-display area (NDA). The gate driver (560) may generate a gate signal based on a gate control signal supplied from the timing controller (540). The gate control signal may include, but is not limited to, a start signal, a clock signal, and a power voltage. The gate driver (560) may supply the gate signal to the gate line (GL) according to a set order.

[0108] FIG. 6 is a drawing showing pixels and wirings of a display device according to one embodiment.

[0109] In addition to FIGS. 4 and 5, referring to FIG. 6, the pixel SP may include first to third pixels SP1, SP2, and SP3. The pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3 may be arranged in order in a direction opposite to the second direction DR2, but the order of the pixel circuits is not limited thereto.

[0110] Each of the first to third pixels (SP1, SP2, SP3) can be connected to a first voltage line (VDL), an initialization voltage line (VIL), a gate line (GL), and a data line (DL).

[0111] The first voltage line (VDL) can extend in the second direction (DR2). The first voltage line (VDL) can be arranged on the left side of the pixel circuits of the first to third pixels (SP1, SP2, SP3). The first voltage line (VDL) can supply a driving voltage or a high-potential voltage to each transistor of the first to third pixels (SP1, SP2, SP3).

[0112] The horizontal voltage line (HVDL) can be extended in the first direction (DR1). The horizontal voltage line (HVDL) is in the kth row (ROW k , k is a positive integer) may be arranged on the upper side of the first gate line (GL1). The horizontal voltage line (HVDL) may be connected to the first voltage line (VDL). The horizontal voltage line (HVDL) may receive a driving voltage or a high-potential voltage from the first voltage line (VDL).

[0113] An initialization voltage line (VIL) may extend in a second direction (DR2). The initialization voltage line (VIL) may be arranged on the left side of a vertical auxiliary line of the second gate line (GL2) branched in the second direction (DR2). The initialization voltage line (VIL) may be arranged between the auxiliary line of the second gate line (GL2) branched in the second direction (DR2) and the vertical voltage line (VVSL). The initialization voltage line (VIL) may supply an initialization voltage to each pixel circuit of the first to third pixels (SP1, SP2, SP3). The initialization voltage line (VIL) may receive a sensing signal from each pixel circuit of the first to third pixels (SP1, SP2, SP3) and supply the sensing signal to the display driver (520).

[0114] The vertical voltage line (VVSL) may extend in the second direction (DR2). The vertical voltage line (VVSL) may be positioned to the left of the initialization voltage line (VIL). The vertical voltage line (VVSL) may be connected between the power supply (550) and the second voltage line (VSL). The vertical voltage line (VVSL) may supply a low-potential voltage supplied from the power supply (550) to the second voltage line (VSL).

[0115] The second voltage line (VSL) can be extended in the first direction (DR1). The second voltage line (VSL) is in the k+1 row (ROW k+1 ) may be arranged on the upper side of the first gate line (GL1). The second voltage line (VSL) may supply a low-potential voltage received from the vertical voltage line (VVSL) to the light-emitting element layer (EML) (see FIG. 9) of the first to third pixels (SP1, SP2, SP3).

[0116] The first gate line (GL1) may extend in a first direction (DR1). The first gate line (GL1) may be arranged on an upper side of a pixel circuit of a first pixel (SP1). The first gate line (GL1) may branch so that a portion thereof extends in a direction opposite to the second direction (DR2). For example, the first gate line (GL1) may include a vertical auxiliary line that branches off from the right side of the first to third pixels (SP1, SP2, SP3) and extends in a direction opposite to the second direction (DR2). The auxiliary line of the first gate line (GL1) may be arranged on the right side of the pixel circuits of the first to third pixels (SP1, SP2, SP3). The first gate line (GL1) may supply a first gate signal received from the gate driver (560) to the pixel circuits of the first to third pixels (SP1, SP2, SP3) through the auxiliary line that extends in a direction opposite to the second direction (DR2).

[0117] The second gate line (GL2) may extend in the first direction (DR1). The second gate line (GL2) may be arranged on the lower side of the pixel circuit of the third pixel (SP3). The second gate line (GL2) may branch so that a portion thereof extends in the second direction (DR2). For example, the second gate line (GL2) may include a vertical auxiliary line that branches off from the left side of the first voltage line (VDL) and extends in the second direction (DR2). The auxiliary line of the second gate line (GL2) may be arranged on the left side of the first voltage line (VDL). The second gate line (GL2) may supply a second gate signal received from the gate driver (560) to the pixel circuits of the first to third pixels (SP1, SP2, and SP3) through the auxiliary line that extends in the second direction (DR2).

[0118] The data lines (DL) may extend in the second direction (DR2). The data lines (DL) may supply a data voltage to the pixels (SP). The data lines (DL) may include first to third data lines (DL1, DL2, DL3).

[0119] The second data line (DL2) may extend in the second direction (DR2). The second data line (DL2) may be arranged on the right side of the auxiliary line of the first gate line (GL1). The second data line (DL2) may supply a data voltage received from the display driver (520) to the pixel circuit of the second pixel (SP2).

[0120] The third data line (DL3) may extend in the second direction (DR2). The third data line (DL3) may be arranged to the right of the second data line (DL2). The third data line (DL3) may supply a data voltage received from the display driver (520) to the pixel circuit of the third pixel (SP3).

[0121] The first data line (DL1) may extend in the second direction (DR2). The first data line (DL1) may be arranged to the right of the third data line (DL3). The first data line (DL1) may supply a data voltage received from the display driver (520) to the pixel circuit of the first pixel (SP1).

[0122] In the drawing, the second data line (DL2), the third data line (DL3), and the first data line (DL1) are shown to be arranged in sequence in the first direction (DR1), but this is not limited thereto. The sequence of the first to third data lines (DL1, DL2, DL3) can be variously changed in the first direction (DR1).

[0123] Fig. 7 is a plan view schematically illustrating a portion of a display area of ​​a display substrate according to one embodiment. Fig. 8 is a plan view schematically illustrating a portion of a display area of ​​a display substrate according to another embodiment.

[0124] In addition to FIGS. 1 to 3, referring to FIGS. 7 and 8, a plurality of light-emitting areas (LA) and non-light-emitting areas (NLA) may be defined in the display area (DA) of the display substrate (100). The plurality of light-emitting areas (LA) may be areas in which light generated from a light-emitting element of the display substrate (100) is emitted to the outside of the display substrate (100), and the non-light-emitting area (NLA) may be an area in which light generated from a light-emitting element of the display substrate (100) is not emitted to the outside of the display substrate (100). In some embodiments, the plurality of light-emitting areas (LA) may include a first light-emitting area (LA1), a second light-emitting area (LA2), and a third light-emitting area (LA3).

[0125] In some embodiments, the emissive area (LA) and the non-emissive area (NLA) may be defined by a pixel defining layer (PDL) (see FIG. 9). For example, the emissive area (LA) may be an area overlapping an opening of the pixel defining layer (PDL) (see FIG. 9), and the non-emissive area (NLA) may be an area not overlapping an opening of the pixel defining layer (PDL) (see FIG. 9).

[0126] In one embodiment, the light emitted from the display substrate (100) to the color conversion substrate (200) in the plurality of light-emitting areas (LA) may be light of a third color. For example, the light of the third color may be blue light and may have a peak wavelength in a range of about 440 nm to about 480 nm. The peak wavelength may mean a wavelength at which the intensity is maximum within the wavelength range. However, the present invention is not limited thereto, and the light emitted from the display substrate (100) to the color conversion substrate (200) in the plurality of light-emitting areas (LA) may be light in the ultraviolet range.

[0127] When the first to third light-emitting areas (LA1, LA2, LA3) emit light of the same color, the first to third pixels (SP1, SP2, SP3) can express various colors by a color conversion pattern included in the color conversion substrate (200).

[0128] In another embodiment, the first to third light-emitting areas (LA1, LA2, LA3) may emit light of different colors. For example, the color of the light emitted from the first light-emitting area (LA1) may be red light, the color of the light emitted from the second light-emitting area (LA2) may be green light, and the color of the light emitted from the third light-emitting area (LA3) may be blue light.

[0129] The first light-emitting area (LA1), the second light-emitting area (LA2), and the third light-emitting area (LA3) can constitute a first pixel (SP1), a second pixel (SP2), and a third pixel (SP3), respectively. The first light-emitting area (LA1), the second light-emitting area (LA2), and the third light-emitting area (LA3) can be repeatedly arranged along the first direction (DR1) and the second direction (DR2) throughout the display area (DA). The first light-emitting area (LA1), the second light-emitting area (LA2), and the third light-emitting area (LA3) can constitute one unit color pixel.

[0130] In one embodiment, as illustrated in FIG. 7, the first to third light-emitting areas (LA1, LA2, LA3) may be arranged in a diagonal direction defined by opposite directions of the first direction (DR1) and the second direction (DR2). For example, within one unit color pixel, the first light-emitting area (LA1) may be arranged generally at the upper left on a plane, the second light-emitting area (LA2) may be arranged generally at the center on a plane, and the third light-emitting area (LA3) may be arranged generally at the lower right on a plane. However, the arrangement order of the first to third light-emitting areas (LA1, LA2, LA3) is not limited thereto.

[0131] In another embodiment, as illustrated in FIG. 8, the first to third light-emitting areas (LA1, LA2, LA3) may be arranged along the first direction (DR1). For example, within one unit color pixel, the first light-emitting area (LA1) may be arranged generally on the left side in a plane, the second light-emitting area (LA2) may be arranged generally in the center in a plane, and the third light-emitting area (LA3) may be arranged generally on the right side in a plane. However, the arrangement order of the first to third light-emitting areas (LA1, LA2, LA3) is not limited thereto.

[0132] In one embodiment, as illustrated in FIG. 7, the shape of the first light-emitting area (LA1) may be a polygon extending in the first direction (DR1) and the second direction (DR2). In the drawing, the shape of the first light-emitting area (LA1) is illustrated as a pentagon as an example. The shape of the second light-emitting area (LA2) may be a polygon extending in a diagonal direction defined by the first direction (DR1) and the second direction (DR2). In the drawing, the shape of the second light-emitting area (LA2) is illustrated as a polygon including steps at both ends as an example. The shape of the third light-emitting area (LA3) may be a polygon extending in the first direction (DR1) and the second direction (DR2). In the drawing, the shape of the third light-emitting area (LA3) is illustrated as a polygon including a portion protruding in the opposite direction of the first direction (DR1) and the second direction (DR2) as an example. The shapes of the first to third light-emitting areas (LA1, LA2, LA3) are not limited thereto.

[0133] In another embodiment, as illustrated in FIG. 8, the shapes of the first to third light-emitting areas (LA1, LA2, LA3) may be polygons extending in the second direction (DR2). In the drawing, the shapes of the first to third light-emitting areas (LA1, LA2, LA3) are illustrated as squares as an example. However, the shapes of the first to third light-emitting areas (LA1, LA2, LA3) are not limited thereto.

[0134] In one embodiment, as illustrated in FIG. 7, the widths and shapes of the first to third light-emitting areas LA1, LA2, and LA3 may be different from each other. For example, the first light-emitting area LA1 may have a similar width in the first direction DR1 and the second direction DR2. The second light-emitting area LA2 may have a wide width in a diagonal direction defined by the first direction DR1 and the second direction DR2, and a narrow width in a diagonal direction defined by a direction opposite to the first direction DR1 and the second direction DR2. Accordingly, the second light-emitting area LA2 may generally have a polygonal shape that is elongated in the diagonal direction defined by the first direction DR1 and the second direction DR2. The third light-emitting area LA3 may have a similar width in the first direction DR1 and the second direction DR2.

[0135] In another embodiment, as illustrated in FIG. 8, the widths and shapes of the first to third light-emitting areas (LA1, LA2, LA3) may be the same. For example, the widths of the first to third light-emitting areas (LA1, LA2, LA3) in the first direction (DR1) may be the same, and the widths of the first to third light-emitting areas (LA1, LA2, LA3) in the second direction (DR2) may be the same.

[0136] A non-luminous area (NLA) may be positioned around the light-emitting area (LA) of the display substrate (100) within the display area (DA). The non-luminous area (NLA) may be positioned not only around the light-emitting area (LA), but also between the first light-emitting area (LA1) and the second light-emitting area (LA2), between the second light-emitting area (LA2) and the third light-emitting area (LA3), and between the third light-emitting area (LA3) and the first light-emitting area (LA1).

[0137] Light emitted from the light-emitting area (LA) of the display substrate (100) can be transmitted through the light-transmitting area of ​​the color conversion substrate (200) and provided to the outside of the display device (10).

[0138] Fig. 9 is a cross-sectional view taken along line X2-X2' of Fig. 8.

[0139] In addition to FIGS. 7 and 8, referring to FIG. 9, the display device (10) may include a display substrate (100), a color conversion substrate (200) facing the display substrate (100), and a filler (300) for bonding them.

[0140] The display substrate (100) may include a first substrate (110), a circuit layer (CCL), a light emitting element layer (EML), and an encapsulation structure (170).

[0141] The first substrate (110) may include a transparent material. For example, the first substrate (110) may include a transparent insulating material such as glass, quartz, or the like. The first substrate (110) may be a rigid substrate. However, the first substrate (110) is not limited thereto, and may include a plastic such as polyimide, or may have flexible properties that allow it to be bent, folded, or rolled.

[0142] A circuit layer (CCL) (e.g., a thin film transistor layer) may be disposed on the first substrate (110). A description of the circuit layer (CCL) will be provided later with reference to FIG. 8, etc.

[0143] An emission layer (EML) may be disposed on a circuit layer (CCL). The emission layer (EML) may include a pixel electrode (PXE), a pixel defining layer (PDL), an emission layer (LEL), and a common electrode (CME).

[0144] The pixel electrode (PXE) may be a first electrode of a light-emitting diode, for example, an anode electrode. The pixel electrode (PXE) may have a laminated film structure in which a high work function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) is laminated with a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. The high work function material layer may be disposed above the reflective material layer and close to the light-emitting layer (LEL). The pixel electrode (PXE) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0145] The pixel electrode (PXE) may include a first pixel electrode (PXR), a second pixel electrode (PXG), and a third pixel electrode (PXB). The first pixel electrode (PXR) may be arranged to overlap the first light-emitting area (LA1). The second pixel electrode (PXG) may be arranged to overlap the second light-emitting area (LA2). The third pixel electrode (PXB) may be arranged to overlap the third light-emitting area (LA3).

[0146] A pixel defining layer (PDL) may be disposed along the boundary of a pixel (SP) on one surface of a first substrate (110). The pixel defining layer (PDL) is disposed on a pixel electrode (PXE) and may include an opening that exposes the pixel electrode (PXE). An emission area (LA) and a non-emission area (NLA) may be distinguished by the pixel defining layer (PDL) and the opening thereof.

[0147] The pixel defining layer (PDL) may include an organic insulating material such as polyacrylates, epoxy resin, phenolic resin, polyamides, polyimides, unsaturated polyesters, polyphenyleneethers, polyphenylenesulfides, or benzocyclobutene (BCB). The pixel defining layer (PDL) may also include an inorganic material.

[0148] The light-emitting layer (LEL) can be disposed on the pixel electrode (PXE) exposed by the pixel defining layer (PDL). The light-emitting layer (LEL) can be in contact not only with the pixel electrode (PXE) but also with the side and upper surfaces of the pixel defining layer (PDL). The light-emitting layer (LEL) can be connected without distinction between the light-emitting area (LA) and the pixel (SP). The light-emitting layer (LEL) can be disposed over the entire surface without distinction between the light-emitting area (LA) and the pixel (SP). Accordingly, the wavelength of light emitted by the light-emitting layer (LEL) can be the same for each light-emitting area (LA1, LA2, LA3). For example, when the light-emitting layer (LEL) of each light-emitting area (LA1, LA2, LA3) emits blue light or ultraviolet light, and the color conversion substrate (200) described below includes a wavelength conversion layer (WCL), a color for each pixel (SP) can be displayed.

[0149] In another embodiment, the light-emitting layers (LEL) may be spaced apart from each other in each light-emitting area (LA1, LA2, LA3) defined by a pixel defining layer (PDL). In this case, the wavelength of light emitted by each light-emitting layer (LEL) may be the same for each light-emitting area (LA1, LA2, LA3).

[0150] In one embodiment where the display device (10) is an organic light-emitting display device, the light-emitting layer (LEL) may include an organic layer including an organic material. The organic layer includes an organic light-emitting layer, and in some cases, may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer as an auxiliary layer that assists light emission. In another embodiment, when the display device (10) is a micro LED display device, a nano LED display device, or the like, the light-emitting layer (LEL) may include an inorganic material such as an inorganic semiconductor.

[0151] In some embodiments, the light-emitting layer (LEL) may have a tandem structure including a plurality of organic light-emitting layers that are overlapped in the thickness direction and a charge generation layer disposed therebetween. Each of the overlapping organic light-emitting layers may emit light of the same wavelength, but may also emit light of different wavelengths. At least some layers of the light-emitting layer (LEL) of each pixel (SP) may be separated from or connected to the same layer of an adjacent pixel (SP) by a pixel defining layer (PDL).

[0152] A common electrode (CME) may be disposed on the light-emitting layer (LEL). The common electrode (CME) may be connected without distinction between the light-emitting area (LA) and the pixel (SP). The common electrode (CME) may be a front electrode disposed across the entire surface without distinction between the light-emitting area (LA) and the pixel (SP). The common electrode (CME) may be a second electrode of the light-emitting diode, for example, a cathode electrode. The common electrode (CME) may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (for example, a mixture of Ag and Mg, etc.). The common electrode (CME) may further include a transparent metal oxide layer disposed on the material layer having a low work function.

[0153] A pixel electrode (PXE), an emission layer (LEL), and a common electrode (CME) can constitute a light-emitting element (e.g., an organic light-emitting element). Light emitted from the emission layer (LEL) can be emitted upward through the common electrode (CME).

[0154] The encapsulation structure (170) may be disposed on a common electrode (CME). The encapsulation structure (170) may include at least one thin film encapsulation layer. For example, the encapsulation structure (170) may include a first encapsulation inorganic film (171), an encapsulation organic film (172), and a second encapsulation inorganic film (173).

[0155] The first encapsulating inorganic film (171) can be placed on the light emitting element layer (EML). The first encapsulating inorganic film (171) can be made of silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ) may include, etc.

[0156] The encapsulating organic film (172) may be disposed on the first encapsulating inorganic film (171). The encapsulating organic film (172) may include an organic insulating material such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides rein, unsaturated polyesters resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB).

[0157] The second encapsulating inorganic film (173) may be disposed on the encapsulating organic film (172). The second encapsulating inorganic film (173) may include the same material as the first encapsulating inorganic film (171) described above. For example, the second encapsulating inorganic film (173) may be silicon nitride (SiN). x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ) may include, etc.

[0158] In some embodiments, some layers of the encapsulating structure (170) or the entire encapsulating structure (170) may be omitted. If the encapsulating structure (170) is omitted, the filler (300), the sealing member (400), and the color conversion substrate (200) may be directly disposed on the light emitting element layer (EML), and the filler (300), the sealing member (400), and the color conversion substrate (200) may directly perform the encapsulating function.

[0159] The color conversion substrate (200) may be placed on the encapsulation structure (170) to face the display substrate (100). The color conversion substrate (200) may include a second substrate (210), a light-blocking member (BM), a color filter layer (CFL), a first capping layer (220), a partition wall (PTL), a wavelength conversion layer (WCL), a light-transmitting layer (TPL), and a second capping layer (230).

[0160] The second substrate (210) may include a transparent material. The second substrate (210) may include a transparent insulating material such as glass, quartz, or the like. The second substrate (210) may be a rigid substrate. However, the second substrate (210) is not limited thereto, and the second substrate (210) may include a plastic such as polyimide, or may have flexible properties that allow it to be bent, folded, or rolled.

[0161] The second substrate (210) may be the same substrate as the first substrate (110), but may have different materials, thicknesses, transmittances, etc. For example, the second substrate (210) may have higher transmittances than the first substrate (110). The second substrate (210) may be thicker or thinner than the first substrate (110).

[0162] A light-blocking member (BM) may be disposed along the boundary of a pixel (SP) on one surface of a second substrate (210) facing the first substrate (110). The light-blocking member (BM) may overlap with a pixel defining layer (PDL) of the display substrate (100) and may be located in a non-emission area (NLA). The light-blocking member (BM) may include an opening that exposes one surface of the second substrate (210) overlapping with the emission area (LA). The light-blocking member (BM) may be formed in a grid shape in a plan view.

[0163] The light-shielding member (BM) may include an organic material. The light-shielding member (BM) can reduce color distortion caused by external light reflection by absorbing external light. In addition, the light-shielding member (BM) can play a role in reducing or preventing light emitted from the light-emitting layer (LEL) from penetrating into adjacent pixels (SP).

[0164] In one embodiment, the light-shielding member (BM) can absorb all visible light wavelengths. The light-shielding member (BM) may include a light-absorbing material. For example, the light-shielding member (BM) may be formed of a material used as a black matrix of the display device (10).

[0165] In another embodiment, the light-shielding member (BM) may absorb light of a specific wavelength among visible light wavelengths and transmit light of another specific wavelength. For example, the light-shielding member (BM) may include the same material as the color filter layer (CFL). Specifically, the light-shielding member (BM) may be formed of the same material as the blue color filter layer. In some embodiments, the light-shielding member (BM) may be formed integrally with the blue color filter layer. In addition, the light-shielding member (BM) may be omitted.

[0166] A color filter layer (CFL) may be disposed on one surface of a second substrate (210) on which a light-blocking member (BM) is disposed. The color filter layer (CFL) may be disposed on one surface of the second substrate (210) that is exposed through an opening of the light-blocking member (BM). Furthermore, a portion of the color filter layer (CFL) may also be disposed on an adjacent light-blocking member (BM).

[0167] The color filter layer (CFL) may include a first color filter layer (CFL1) arranged in a first pixel (SP1), a second color filter layer (CFL2) arranged in a second pixel (SP2), and a third color filter layer (CFL3) arranged in a third pixel (SP3). Each color filter layer (CFL) may include a colorant, such as a dye or pigment, that absorbs a wavelength other than a corresponding color wavelength. The first color filter layer (CFL1) may be a red color filter layer, the second color filter layer (CFL2) may be a green color filter, and the third color filter layer (CFL3) may be a blue color filter layer. Although the drawing exemplifies a case where adjacent color filter layers (CFLs) are arranged to be spaced apart from each other on the light-blocking member (BM), the adjacent color filter layers (CFLs) may at least partially overlap on the light-blocking member (BM).

[0168] The first capping layer (220) may be disposed on the color filter layer (CFL). The first capping layer (220) may reduce or prevent damage or contamination of the color filter layer (CFL) by impurities such as moisture or air from penetrating from the outside. In addition, the first capping layer (220) may reduce or prevent the colorant of the color filter layer (CFL) from diffusing into other components.

[0169] The first capping layer (220) can be in direct contact with one surface (bottom surface in FIG. 9) of the color filter layer (CFL). The first capping layer (220) can be made of an inorganic material. For example, the first capping layer (220) can be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, silicon oxynitride, etc.

[0170] A barrier rib (PTL) may be disposed on the first capping layer (220). The barrier rib (PTL) may be located in the non-luminous region (NLA). The barrier rib (PTL) may be disposed to overlap the light-shielding member (BM). The barrier rib (PTL) may include (or define) an opening that exposes the color filter layer (CFL). The barrier rib (PTL) may include, but is not limited to, a photosensitive organic material. The barrier rib (PTL) may further include a light-shielding material.

[0171] The wavelength conversion layer (WCL) and / or the light transmitting layer (TPL) may be positioned within the space exposed by the opening of the photoconductive layer (PTL). The wavelength conversion layer (WCL) and the light transmitting layer (TPL) may be formed by an inkjet process using the photoconductive layer (PTL) as a bank, but are not limited thereto.

[0172] In one embodiment where the light-emitting layer (LEL) of each pixel (SP) emits a third color, the wavelength conversion layer (WCL) may include a first wavelength conversion pattern (WCL1) disposed in a first pixel (SP1) and a second wavelength conversion pattern (WCL2) disposed in a second pixel (SP2). A light-transmitting layer (TPL) may be disposed in the third pixel (SP3).

[0173] The first wavelength conversion pattern (WCL1) may include a first base resin (BRS1) and a first wavelength conversion material (WCP1) disposed within the first base resin (BRS1). The second wavelength conversion pattern (WCL2) may include a second base resin (BRS2) and a second wavelength conversion material (WCP2) disposed within the second base resin (BRS2). The light transmitting layer (TPL) may include a third base resin (BRS3) and a scatterer (SCP) disposed within the third base resin (BRS3).

[0174] The first to third base resins (BRS1, BRS2, ​​BRS3) may include a light-transmitting organic material. For example, the first to third base resins (BRS1, BRS2, ​​BRS3) may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The first to third base resins (BRS1, BRS2, ​​BRS3) may all be made of the same material, but are not limited thereto.

[0175] The scattering material (SCP) may be a metal oxide particle or an organic particle. Examples of the metal oxide include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the organic particle material include acrylic resin or urethane resin.

[0176] The first wavelength conversion material (WCP1) may be a material that converts a third color into a first color, and the second wavelength conversion material (WCP2) may be a material that converts a third color into a second color. The first wavelength conversion material (WCP1) and the second wavelength conversion material (WCP2) may be quantum dots, quantum rods, phosphors, or the like. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof. The first wavelength conversion pattern (WCL1) and the second wavelength conversion pattern (WCL2) may further include a scatterer (SCP) that increases wavelength conversion efficiency.

[0177] The light transmitting layer (TPL) arranged in the third pixel (SP3) can transmit the third color light emitted from the light emitting layer (LEL) while maintaining the wavelength thereof. The scattering material (SCP) of the light transmitting layer (TPL) can serve to control the emission path of light emitted through the light transmitting layer (TPL). The light transmitting layer (TPL) may not include a wavelength conversion material.

[0178] The second capping layer (230) may be disposed on the wavelength conversion layer (WCL), the light-transmitting layer (TPL), and the phototransistor layer (PTL). The second capping layer (230) may be formed of an inorganic material. The second capping layer (230) may include a material selected from among the materials listed as the materials of the first capping layer (220). The second capping layer (230) and the first capping layer (220) may be formed of the same material, but are not limited thereto.

[0179] A filler (300) may be placed between the display substrate (100) and the color conversion substrate (200). The filler (300) may fill the space between the display substrate (100) and the color conversion substrate (200), and may also serve to adhere and bond them to each other. The filler (300) may be placed between the encapsulation structure (170) of the display substrate (100) and the second capping layer (230) of the color conversion substrate (200). The filler (300) may be made of a Si-based organic material, an epoxy-based organic material, or the like, but is not limited thereto.

[0180] Fig. 10 is an equivalent circuit diagram of a pixel according to one embodiment.

[0181] Referring to FIG. 10, each of the pixels (SP) can be connected to a first voltage line (VDL), a data line (DL), an initialization voltage line (VIL), a first gate line (GL1), a second gate line (GL2), and a vertical voltage line (VVSL).

[0182] Each of the pixels (SP) may include a pixel circuit and a light emitting element (ED). In one embodiment, as illustrated in the drawing, the pixel circuit of each pixel (SP) may have a 3T1C structure including three transistors and one capacitor. For example, the pixel circuit of each pixel (SP) may include first to third transistors (ST1, ST2, ST3) and a capacitor (C1). However, the present invention is not limited thereto, and the number of transistors and capacitors of each pixel circuit may be variously modified. Hereinafter, for convenience of explanation, the 3T1C structure will be described as an example, but the present invention is not limited thereto, and various other modified structures such as a 2T1C structure, a 7T1C structure, a 6T1C structure, and a 17T3C structure may be applied.

[0183] A first transistor (ST1) may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor (ST1) may be connected to a first node (N1), the drain electrode may be connected to a first voltage line (VDL), and the source electrode may be connected to a second node (N2). The first transistor (ST1) may control a drain-source current (or driving current) based on a data voltage applied to the gate electrode. The first transistor (ST1) may be a driving transistor that drives a light-emitting element (ED).

[0184] A light emitting element (ED) can receive a driving current and emit light. The amount of light emitted or the brightness of the light emitting element (ED) can be proportional to the magnitude of the driving current. The light emitting element (ED) can be an organic light emitting diode (OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, a micro LED, or an inorganic LED including an inorganic semiconductor.

[0185] A first electrode (e.g., a pixel electrode) of a light-emitting element (ED) may be connected to a second node (N2), and a second electrode of the light-emitting element (ED) may be connected to a vertical voltage line (VVSL). The first electrode of the light-emitting element (ED) may be connected to a source electrode of a first transistor (ST1), a drain electrode of a third transistor (ST3), and a first capacitor electrode of a capacitor (C1) via the second node (N2).

[0186] The second transistor (ST2) can be turned on by the first gate signal of the first gate line (GL1) to electrically connect the data line (DL) and the first node (N1), which is the gate electrode of the first transistor (ST1). The second transistor (ST2) can be turned on based on the first gate signal to supply a data voltage to the first node (N1). The gate electrode of the second transistor (ST2) can be connected to the first gate line (GL1), the drain electrode can be connected to the data line (DL), and the source electrode can be connected to the first node (N1). The source electrode of the second transistor (ST2) can be connected to the gate electrode of the first transistor (ST1) and the second capacitor electrode of the capacitor (C1) via the first node (N1). The second transistor (ST2) can be a switching transistor that controls current flowing to the first transistor (ST1) and the light-emitting element (ED).

[0187] The third transistor (ST3) can be turned on by the second gate signal of the second gate line (GL2) to electrically connect the initialization voltage line (VIL) and the second node (N2), which is the source electrode of the first transistor (ST1). The third transistor (ST3) can be turned on based on the second gate signal to supply the initialization voltage to the second node (N2). The third transistor (ST3) can be turned on based on the second gate signal to supply the sensing signal to the initialization voltage line (VIL). The gate electrode of the third transistor (ST3) can be connected to the second gate line (GL2), the drain electrode can be connected to the second node (N2), and the source electrode can be connected to the initialization voltage line (VIL). The drain electrode of the third transistor (ST3) may be connected to the source electrode of the first transistor (ST1), the first capacitor electrode of the capacitor (C1), and the first electrode of the light-emitting element (ED) via the second node (N2). The third transistor (ST3) may be a switching transistor that controls the current flowing to the first transistor (ST1) and the light-emitting element (ED).

[0188] Fig. 11 is a cross-sectional view showing an example of a first transistor of a circuit layer according to one embodiment. Fig. 12 is a cross-sectional view showing an example of a second transistor and a third transistor of a circuit layer according to one embodiment.

[0189] In addition to FIG. 10, referring to FIGS. 11 and 12, the display substrate (100) may include a first substrate (110), a circuit layer (CCL), and a light emitting element layer (EML).

[0190] The description of the first substrate (110) is omitted as it has been described above with reference to FIG. 9.

[0191] A circuit layer (CCL) may be disposed on a first substrate (110). The circuit layer (CCL) (e.g., a thin film transistor layer) may include a lower conductive layer (BML), a buffer film (BF), an active layer (ACTL), a gate insulating film (GI), a gate conductive layer (GML), a protective film (PV), and a via film (VIA). The circuit layer (CCL) may include first to third transistors (ST1, ST2, ST3) and a capacitor (C1).

[0192] A lower conductive layer (BML) may be disposed on a first substrate (110). The lower conductive layer (BML) may include a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0193] In one embodiment, the lower conductive layer (BML) may include an initialization voltage line (VIL), a data line (DL), a first voltage line (VDL), a vertical voltage line (VVSL), and a first capacitor electrode (CPE1) of a capacitor (C1).

[0194] The buffer film (BF) may be disposed on the lower conductive layer (BML). The buffer film (BF) may include an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. Alternatively, the buffer film (BF) may include a multi-film in which a plurality of layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated.

[0195] The active layer (ACTL) may be disposed on the buffer film (BF). The active layer (ACTL) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material.

[0196] In one embodiment, the active layer (ACTL) may include a first active region (ACT1), a first drain electrode (DE1), and a first source electrode (SE1) of a first transistor (ST1), a second active region (ACT2), a second drain electrode (DE2), and a second source electrode (SE2) of a second transistor (ST2), a third active region (ACT3), a third drain electrode (DE3), and a third source electrode (SE3) of a third transistor (ST3), and a second capacitor electrode (CPE2) of a capacitor (C1).

[0197] A gate insulating film (GI) may be disposed on the active layer (ACTL). The gate insulating film (GI) may include an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0198] A gate conductive layer (GML) may be disposed on a gate insulating film (GI). The gate conductive layer (GML) may include a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0199] In one embodiment, the gate conductive layer (GML) may include a first gate line (GL1), a second gate line (GL2), a first gate electrode (GE1) of a first transistor (ST1), a second gate electrode (GE2) of a second transistor (ST2), a third gate electrode (GE3) of a third transistor (ST3), and connection electrodes (CE1, CE2, CE3, CE4).

[0200] In the display device (10) according to the present embodiment, the gate conductive layer (GML) may have a lower reflectivity than at least one of the lower conductive layer (BML) and the anode conductive layer (AML). The gate conductive layer (GML) may further include a material for lowering the reflectivity. For example, the gate conductive layer (GML) may include aluminum-zinc-tin-oxide (AZTO).

[0201] First light (L1), such as light entering from the outside or light emitted from an adjacent pixel, may be reflected from the upper surface of the gate conductive layer (GML). Second light (L2) reflected from the upper surface of the gate conductive layer (GML) may be reflected again from the lower surface of the anode conductive layer (AML) and may be incident on the active layer (ACTL). This may cause light-induced degradation. Light-induced degradation refers to a phenomenon in which the characteristic curve between the drain-source current (Ids) and the gate voltage (Vg) of the original transistor shifts due to external light incident on the transistor, thereby changing the magnitude of the threshold voltage (Vth).

[0202] In the display device (10) according to the present embodiment, the gate conductive layer (GML) further includes a material for lowering reflectivity, thereby reducing reflected light such as the second light (L2). Accordingly, by reducing or minimizing the photodegradation phenomenon, the reliability of the display device (10) can be improved.

[0203] A passivation layer (PV) may be disposed on the gate conductive layer (GML). The passivation layer (PV) may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0204] A via film (VIA) may be disposed on a protective film (PV). The via film (VIA) may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0205] The circuit layer (CCL) may include first to third transistors (ST1, ST2, ST3) and a capacitor (C1).

[0206] The first transistor (ST1) may include a first active region (ACT1), a first gate electrode (GE1), a first drain electrode (DE1), and a first source electrode (SE1).

[0207] The first active region (ACT1) may be arranged on the active layer (ACTL). The first active region (ACT1) may overlap the first gate electrode (GE1) in the third direction (DR3). The first active region (ACT1) may be a region in which the active layer (ACTL) is not conductive in the region overlapping the first gate electrode (GE1).

[0208] A first gate electrode (GE1) may be disposed on a gate conductive layer (GML). As illustrated in FIG. 10, the first gate electrode (GE1) may be connected to a second source electrode (SE2) of a second transistor (ST2) and a second capacitor electrode (CPE2) of a capacitor (C1) via a first node (N1).

[0209] In the drawing, the first transistor (ST1) is illustrated as having a top gate structure in which the first gate electrode (GE1) is disposed on the upper portion of the first active region (ACT1), but is not limited thereto. For example, the first transistor (ST1) may have a bottom gate structure in which the first gate electrode (GE1) is disposed on the lower portion of the first active region (ACT1). As another example, the first transistor (ST1) may have a double gate structure in which the first gate electrode (GE1) is disposed on both the upper and lower portions of the first active region (ACT1).

[0210] The first drain electrode (DE1) and the first source electrode (SE1) can be formed by heat-treating the active layer (ACTL) to make it conductive. The first drain electrode (DE1) and the first source electrode (SE1) can be made conductive with a P-type semiconductor or an N-type semiconductor, but are not limited thereto.

[0211] The first drain electrode (DE1) can be electrically connected to the first voltage line (VDL), as illustrated in FIG. 10. For example, as illustrated in FIG. 11, the first drain electrode (DE1) can be connected to the first voltage line (VDL) via the first connection electrode (CE1). Accordingly, the first drain electrode (DE1) can receive a driving voltage from the first voltage line (VDL).

[0212] The first source electrode (SE1) can be connected to the light emitting element (ED) via the second node (N2), as illustrated in FIG. 10. For example, as illustrated in FIG. 11, the first source electrode (SE1) can be connected to the pixel electrode (PXE) via the second connection electrode (CE2). Accordingly, the first source electrode (SE1) can supply driving current to the light emitting element (ED).

[0213] The first source electrode (SE1) may be connected to the capacitor (C1) via the second node (N2), as illustrated in FIG. 10. For example, as illustrated in FIG. 11, the first source electrode (SE1) may be connected to the first capacitor electrode (CPE1) of the capacitor (C1) via the second connection electrode (CE2).

[0214] The second transistor (ST2) may include a second active region (ACT2), a second gate electrode (GE2), a second drain electrode (DE2), and a second source electrode (SE2).

[0215] The second active region (ACT2) may be arranged on the active layer (ACTL). The second active region (ACT2) may overlap the second gate electrode (GE2) in the third direction (DR3). The second active region (ACT2) may be a region in which the active layer (ACTL) is not conductive in the region overlapping the second gate electrode (GE2).

[0216] The second gate electrode (GE2) may be disposed on the gate conductive layer (GML). As illustrated in FIG. 10, the second gate electrode (GE2) may be connected to the first gate line (GL1). Accordingly, the second gate electrode (GE2) may receive a first gate signal from the first gate line (GL1).

[0217] In the drawing, the second transistor (ST2) is illustrated as having a top gate structure in which the second gate electrode (GE2) is disposed on the upper portion of the second active region (ACT2), but is not limited thereto. For example, the second transistor (ST2) may have a bottom gate structure in which the second gate electrode (GE2) is disposed on the lower portion of the second active region (ACT2). As another example, the second transistor (ST2) may have a double gate structure in which the second gate electrode (GE2) is disposed on both the upper and lower portions of the second active region (ACT2).

[0218] The second drain electrode (DE2) and the second source electrode (SE2) can be formed by heat-treating the active layer (ACTL) to make it conductive. The second drain electrode (DE2) and the second source electrode (SE2) can be made conductive with a P-type semiconductor or an N-type semiconductor, but are not limited thereto.

[0219] The second drain electrode (DE2) may be electrically connected to the data line (DL), as illustrated in FIG. 10. For example, as illustrated in FIG. 12, the second drain electrode (DE2) may be connected to the data line (DL) via the third connection electrode (CE3). Accordingly, the second drain electrode (DE2) may receive a data voltage from the data line (DL).

[0220] As illustrated in Fig. 10, the second source electrode (SE2) can be connected to the first gate electrode (GE1) of the first transistor (ST1) via the first node (N1). Accordingly, the second source electrode (SE2) can supply a data voltage to the first gate electrode (GE1) of the first transistor (ST1) via the first node (N1). The first transistor (ST1) can control the driving current based on the data voltage received from the second source electrode (SE2).

[0221] The second source electrode (SE2) may be connected to the capacitor (C1) via the first node (N1), as illustrated in Fig. 10. For example, although not illustrated in the drawing, the second source electrode (SE2) may be connected to the second capacitor electrode (CPE2) of the capacitor (C1) via a separate connection electrode disposed on the gate conductive layer (GML).

[0222] The third transistor (ST3) may include a third active region (ACT3), a third gate electrode (GE3), a third drain electrode (DE3), and a third source electrode (SE3).

[0223] The third active region (ACT3) may be arranged on the active layer (ACTL). The third active region (ACT3) may overlap the third gate electrode (GE3) in the third direction (DR3). The third active region (ACT3) may be a region in which the active layer (ACTL) is not conductive in the region overlapping the third gate electrode (GE3).

[0224] The third gate electrode (GE3) may be disposed on the gate conductive layer (GML). As illustrated in FIG. 10, the third gate electrode (GE3) may be connected to the second gate line (GL2). Accordingly, the third gate electrode (GE3) may receive a second gate signal from the second gate line (GL2).

[0225] In the drawing, the third transistor (ST3) is illustrated as having a top gate structure in which the third gate electrode (GE3) is disposed on the upper portion of the third active region (ACT3), but is not limited thereto. For example, the third transistor (ST3) may have a bottom gate structure in which the third gate electrode (GE3) is disposed on the lower portion of the third active region (ACT3). As another example, the third transistor (ST3) may have a double gate structure in which the third gate electrode (GE3) is disposed on both the upper and lower portions of the third active region (ACT3).

[0226] The third drain electrode (DE3) and the third source electrode (SE3) can be formed by heat-treating the active layer (ACTL) to make it conductive. The third drain electrode (DE3) and the third source electrode (SE3) can be made conductive with a P-type semiconductor or an N-type semiconductor, but are not limited thereto.

[0227] The third drain electrode (DE3) may be electrically connected to the first source electrode (SE1) of the first transistor (ST1), as illustrated in FIG. 10. For example, although not illustrated in the drawing, the third drain electrode (DE3) may be connected to the first source electrode (SE1) of the first transistor (ST1) via a separate connection electrode disposed on the gate conductive layer (GML).

[0228] The third drain electrode (DE3) may be connected to the capacitor (C1), as illustrated in FIG. 10. For example, although not illustrated in the drawing, the third drain electrode (DE3) may be connected to the first capacitor electrode (CPE1) of the capacitor (C1) via a separate connecting electrode disposed on the gate conductive layer (GML).

[0229] The third source electrode (SE3) can be connected to the initialization voltage line (VIL), as illustrated in FIG. 10. For example, as illustrated in FIG. 12, the third source electrode (SE3) can be connected to the initialization voltage line (VIL) via the fourth connection electrode (CE4). Accordingly, the third source electrode (SE3) can receive the initialization voltage from the initialization voltage line (VIL), and the third source electrode (SE3) can supply a sensing signal to the initialization voltage line (VIL).

[0230] The capacitor (C1) may include a first capacitor electrode (CPE1) and a second capacitor electrode (CPE2).

[0231] A first capacitor electrode (CPE1) may be disposed on a lower conductive layer (BML). The first capacitor electrode (CPE1) may be connected to a first source electrode (SE1) of a first transistor (ST1) via a second connection electrode (CE2). The first capacitor electrode (CPE1) may be connected to a third drain electrode (DE3) of a third transistor (ST3) via a separate connection electrode disposed on a gate conductive layer (GML).

[0232] The second capacitor electrode (CPE2) may be disposed on the active layer (ACTL). The second capacitor electrode (CPE2) may be connected to the first gate electrode (GE1) of the first transistor (ST1) through a separate connection electrode disposed on the gate conductive layer (GML). The second capacitor electrode (CPE2) may be connected to the second source electrode (SE2) of the second transistor (ST2) through a separate connection electrode disposed on the gate conductive layer (GML).

[0233] The light emitting device layer (EML) may include an anode conductive layer (AML) and a pixel defining layer (PDL).

[0234] The description of the pixel defining layer (PDL) is omitted as it has been described above with reference to Fig. 9.

[0235] The anode conductive layer (AML) may be disposed on the circuit layer (CCL). For example, the anode conductive layer (AML) may be disposed on a via film (VIA). In one embodiment, the anode conductive layer (AML) may include a pixel electrode (PXE).

[0236] The anode conductive layer (AML) may have a laminated film structure in which a high work function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) is laminated with a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. The high work function material layer may be disposed above the reflective material layer and close to the light emitting layer (LEL). The pixel electrode (PXE) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0237] The display device (10) according to the present embodiment can improve process efficiency by reducing or minimizing the number of layers of the circuit layer (CCL), thereby reducing the number of masks suitable for patterning each layer.

[0238] For example, by placing wires such as a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), and a vertical voltage line (VVSL) on a lower conductive layer (MTL), and placing wires such as a gate line (GL), a horizontal voltage line (HVDL), and a second voltage line (VSL) on a gate conductive layer (GML), the number of layers can be reduced or minimized by not adding a separate layer for wiring placement.

[0239] As another example, by placing the first capacitor electrode (CPE1) on the lower conductive layer (MTL) and the second capacitor electrode (CPE2) on the active layer (ACTL), the number of layers can be reduced or minimized by not adding a separate layer for placing the capacitor (C1).

[0240] As another example, the number of layers can be reduced or minimized by arranging the connection electrodes for connecting the lower conductive layer (MTL), the active layer (ACTL), and the gate conductive layer (GML) on the gate conductive layer (GML) without adding a separate layer for arranging the connection electrodes.

[0241] In the display device (10) according to the present embodiment, as the number of layers of the circuit layer (CCL) is reduced or minimized, the distance between the light emitting element layer (EML) and the active layer (ACTL) in the third direction (DR3) may become shorter. Accordingly, light introduced from the outside or light emitted from an adjacent pixel may easily enter the active layer (ACTL). In order to reduce or minimize the photodegradation phenomenon that may occur due to this, the gate conductive layer (GML) of the display device (10) according to the present embodiment may include a reflectivity reduction structure.

[0242] Hereinafter, the reflectivity reduction structure of the gate conductive layer (GML) will be described with reference to FIG. 13, etc.

[0243] Fig. 13 is a cross-sectional view showing an example of a portion of a display area and a portion of a pad area of ​​a display device according to one embodiment. Fig. 14 is a cross-sectional view showing an example of a lower conductive layer according to one embodiment. Fig. 15 is a cross-sectional view showing an example of a gate conductive layer according to one embodiment. Fig. 16 is a cross-sectional view showing an example of an anode conductive layer according to one embodiment.

[0244] In Fig. 13, a cross-section of a first transistor (ST1) and a capacitor (C1) is exemplarily shown in the display area (DA), and a cross-section of a wiring pad (WPD) is exemplarily shown in the pad area (PDA).

[0245] Referring to FIGS. 13 to 16, the display device (10) may include a display area (DA) and a pad area (PDA). The display area (DA) is an area for displaying an image and may be a generally central area of ​​the display substrate (100). The pad area (PDA) may be an area where a wiring pad (WPD) is placed. Descriptions regarding the display area (DA) and the pad area (PDA) have been described above with reference to FIG. 5, and therefore will be omitted.

[0246] As illustrated in FIGS. 13 and 14, the lower conductive layer (BML) may include a first lower conductive layer (BML1) and a second lower conductive layer (BML2).

[0247] The first lower conductive layer (BML1) may be disposed on the first substrate (110). The first lower conductive layer (BML1) may be a layer for improving bonding strength between the first substrate (110) and the lower conductive layer (BML). For example, the first lower conductive layer (BML1) may include one or an alloy thereof of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the first lower conductive layer (BML1) may include titanium (Ti), but is not limited thereto.

[0248] The second lower conductive layer (BML2) may be disposed on the first lower conductive layer (BML1). The second lower conductive layer (BML2) may include a material having excellent electrical conductivity. For example, the third lower conductive layer (BML3) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the second lower conductive layer (BML2) may include copper (Cu), but is not limited thereto.

[0249] As illustrated in FIGS. 13 and 15, the gate conductive layer (GML) may include a first gate conductive layer (GML1), a second gate conductive layer (GML2), a third gate conductive layer (GML3), and a fourth gate conductive layer (GML4).

[0250] The first gate conductive layer (GML1) may be disposed on the gate insulating film (GI). The first gate conductive layer (GML1) may be a layer for improving bonding strength between the gate insulating film (GI) and the gate conductive layer (GML). For example, the first gate conductive layer (GML1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Preferably, the first gate conductive layer (GML1) may include titanium (Ti), but is not limited thereto. In one embodiment, the thickness (TH1) of the first gate conductive layer (GML1) may be about 200 Å to 300 Å, but is not limited thereto.

[0251] The second gate conductive layer (GML2) may be disposed on the first gate conductive layer (GML1). The second gate conductive layer (GML2) may include a material having excellent electrical conductivity. For example, the second gate conductive layer (GML2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Preferably, the second gate conductive layer (BML2) may include copper (Cu), but is not limited thereto. In one embodiment, the thickness (TH2) of the second gate conductive layer (GML2) may be about 5000 Å to about 10000 Å, but is not limited thereto.

[0252] The third gate conductive layer (GML3) may be disposed on the second gate conductive layer (GML2). The third gate conductive layer (GML3) may include a material having a high absorption coefficient and a low reflectance. For example, the third gate conductive layer (GML3) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the third gate conductive layer (GML3) may include titanium (Ti), but is not limited thereto. In one embodiment, the thickness (TH3) of the third gate conductive layer (GML3) may be about 100 Å to 200 Å, but is not limited thereto.

[0253] The fourth gate conductive layer (GML4) may be disposed on the third gate conductive layer (GML3). The fourth gate conductive layer (GML4) may include a material having high light transmittance. The fourth gate conductive layer (GML4) may include a transparent conductive oxide (TCO). For example, the fourth gate conductive layer (GML4) may include aluminum-zinc-tin-oxide (AZTO).

[0254] In some embodiments, the fourth gate conductive layer (GML4) may include aluminum in an amount of about 1 at % to 10 at % relative to the remaining atoms excluding oxygen atoms. The fourth gate conductive layer (GML4) may include zinc in an amount of about 60 at % to 90 at % relative to the remaining atoms excluding oxygen atoms. The fourth gate conductive layer (GML4) may include tin in an amount of about 10 at % to 30 at % relative to the remaining atoms excluding oxygen atoms. Here, the respective proportions of aluminum, zinc, and tin included in the fourth gate conductive layer (GML4) refer to the proportions of the number of individual particles of aluminum, zinc, and tin atoms relative to the total number of particles of aluminum, zinc, and tin atoms, which are the remaining atoms excluding oxygen atoms.

[0255] In some embodiments, the fourth gate conductive layer (GML4) may include aluminum in an amount of about 0.5 at % to about 5 at % relative to the total number of atoms including oxygen atoms. The fourth gate conductive layer (GML4) may include zinc in an amount of about 20 at % to about 40 at % relative to the total number of atoms including oxygen atoms. The fourth gate conductive layer (GML4) may include tin in an amount of about 7 at % to about 15 at % relative to the total number of atoms including oxygen atoms. The fourth gate conductive layer (GML4) may include oxygen in an amount of about 50 at % to about 60 at % relative to the total number of atoms including oxygen atoms. Here, the respective proportions of aluminum, zinc, tin, and oxygen included in the fourth gate conductive layer (GML4) refer to the proportions of the number of individual particles of aluminum, zinc, tin, and oxygen atoms relative to the total number of particles of aluminum, zinc, tin, and oxygen atoms.

[0256] In some embodiments, the reflectivity of the third gate conductive layer (GML3) may be lower than the reflectivity of the fourth gate conductive layer (GML4). The light transmittance of the fourth gate conductive layer (GML4) may be higher than the light transmittance of the third gate conductive layer (GML3).

[0257] In the display device (10) according to the present embodiment, the reflectivity of the gate conductive layer (GML) can be reduced by adjusting the thickness (TH3) of the third gate conductive layer (GML3) and the thickness (TH4) of the fourth gate conductive layer (GML4).

[0258] For example, as illustrated in FIG. 15, the third light (L3) incident in advance on the gate conductive layer (GML) may pass through the fourth gate conductive layer (GML4) and be partially absorbed by the third gate conductive layer (GML3). Some of the third light (L3) that is not absorbed by the third gate conductive layer (GML3) may be reflected by the third gate conductive layer (GML3) and cause destructive interference with the fourth light (L4) incident in the subsequent direction, resulting in a reduction or disappearance of energy like the fifth light (L5). Accordingly, the reflectivity of the gate conductive layer (GML) may be reduced.

[0259] In some embodiments, the thickness (TH4) of the fourth gate conductive layer (GML4) may be thicker than the thickness (TH3) of the third gate conductive layer (GML3). For example, the thickness (TH4) of the fourth gate conductive layer (GML4) may be approximately 2 to 30 times the thickness (TH3) of the third gate conductive layer (GML3).

[0260] In some embodiments, the thickness (TH4) of the fourth gate conductive layer (GML4) may be approximately 400 Å to 3000 Å. When the thickness (TH4) of the fourth gate conductive layer (GML4) is less than 400 Å, the reflectivity reduction effect may not occur. When the thickness (TH4) of the fourth gate conductive layer (GML4) is greater than 3000 Å, the process efficiency may decrease and the reliability of the conductive layer may decrease due to heat applied during the conductive layer formation process. Preferably, the thickness (TH4) of the fourth gate conductive layer (GML4) may be approximately 400 Å to 1500 Å.

[0261] As illustrated in FIGS. 13 and 16, the anode conductive layer (AML) may include a first anode conductive layer (AML1), a second anode conductive layer (AML2), and a third anode conductive layer (AML3).

[0262] A first anode conductive layer (AML1) may be disposed on a via membrane (VIA). A second anode conductive layer (AML2) may be disposed on the first anode conductive layer (AML1). A third anode conductive layer (AML3) may be disposed on the second anode conductive layer (AML2).

[0263] The first anode conductive layer (AML1) and the third anode conductive layer (AML3) may include a material having a high work function and high light transmittance. For example, the first anode conductive layer (AML1) and the third anode conductive layer (AML3) may include at least one of indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3). Preferably, the first anode conductive layer (AML1) and the third anode conductive layer (AML3) may include indium-tin-oxide (ITO), but is not limited thereto.

[0264] The second anode conductive layer (AML2) may include a material having high reflectivity. For example, it may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof. Preferably, the second anode conductive layer (AML2) may include silver (Ag), but is not limited thereto.

[0265] In the display device (10) according to the present embodiment, since the third gate conductive layer (GML3) includes a material having low reflectivity and the fourth gate conductive layer (GML4) includes a material having high light-transmitting properties, the gate conductive layer (GML) can have a lower reflectivity than the lower conductive layer (BML) and the anode conductive layer (AML). Accordingly, it is possible to reduce or prevent light incident from the outside or from an adjacent pixel from being reflected from the gate conductive layer (GML) and the anode conductive layer (AML) to the active layer (ACTL). Accordingly, the photodegradation phenomenon can be reduced or minimized.

[0266] Meanwhile, the display device (10) may include a wiring pad (WPD) arranged in a pad area (PDA). In some embodiments, the wiring pad (WPD) may include a first pad electrode (PDE1) and a second pad electrode (PDE2).

[0267] The first pad electrode (PDE1) may be disposed on the lower conductive layer (BML). The first pad electrode (PDE1) may include the same material as the lower conductive layer (BML) of the display area (DA). For example, the first pad electrode (PDE1) may include a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0268] In some embodiments, the first pad electrode (PDE1) may include a first sub-pad (SPD1) and a second sub-pad (SPD2).

[0269] The first sub-pad (SPD1) may be disposed on the first lower conductive layer (BML1). The first sub-pad (SPD1) may include the same material as the first lower conductive layer (BML1) of the display area (DA). For example, the first sub-pad (SPD1) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the first sub-pad (SPD1) may include titanium (Ti), but is not limited thereto.

[0270] The second sub-pad (SPD2) may be disposed on the second lower conductive layer (BML2). The second sub-pad (SPD2) may include the same material as the second lower conductive layer (BML2) of the display area (DA). For example, the second sub-pad (SPD2) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the second sub-pad (SPD2) may include copper (Cu), but is not limited thereto.

[0271] The second pad electrode (PDE2) may be disposed on the gate conductive layer (GML). The second pad electrode (PDE2) may include the same material as the gate conductive layer (GML) of the display area (DA). For example, the second pad electrode (PDE2) may include a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In some embodiments, the second pad electrode (PDE2) may include aluminum-zinc-tin-oxide (AZTO).

[0272] In some embodiments, the second pad electrode (PDE2) may include a third sub-pad (SPD3), a fourth sub-pad (SPD4), a fifth sub-pad (SPD5), and a sixth sub-pad (SPD6).

[0273] The third sub-pad (SPD3) may be disposed on the first gate conductive layer (GML1). The third sub-pad (SPD3) may include the same material as the first gate conductive layer (GML1) of the display area (DA). For example, the third sub-pad (SPD3) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the third sub-pad (SPD3) may include titanium (Ti), but is not limited thereto.

[0274] The fourth sub-pad (SPD4) may be disposed on the second gate conductive layer (GML2). The fourth sub-pad (SPD4) may include the same material as the second gate conductive layer (GML2) of the display area (DA). For example, the fourth sub-pad (SPD4) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the fourth sub-pad (SPD4) may include copper (Cu), but is not limited thereto.

[0275] The fifth sub-pad (SPD5) may be disposed on the third gate conductive layer (GML3). The fifth sub-pad (SPD5) may include the same material as the third gate conductive layer (GML3) of the display area (DA). For example, the fifth sub-pad (SPD5) may include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Preferably, the fifth sub-pad (SPD5) may include titanium (Ti), but is not limited thereto.

[0276] The sixth sub-pad (SPD6) may be disposed on the fourth gate conductive layer (GML4). The sixth sub-pad (SPD6) may include the same material as the fourth gate conductive layer (GML4) of the display area (DA). For example, the sixth sub-pad (SPD6) may include a transparent conductive oxide (TCO). Preferably, the sixth sub-pad (SPD6) may include aluminum-zinc-tin-oxide (AZTO).

[0277] Fig. 17 is a cross-sectional view showing an example of a gate conductive layer according to a conventional embodiment. Fig. 18 is a photograph showing precipitated particles formed on a cross-section of a gate conductive layer according to a conventional embodiment.

[0278] In addition to FIGS. 13 to 16, referring to FIGS. 17 and 18, the gate conductive layer (GML) according to the present embodiment may not include indium. The gate conductive layer (GML) according to the conventional embodiment may include indium. For example, the fourth gate conductive layer (GML4) of the gate conductive layer (GML) according to the conventional embodiment may include indium tin oxide (ITO). The first to third gate conductive layers (GML1, GML2, GML3) of the gate conductive layer (GML) according to the present embodiment and the conventional embodiment may each include the same material for each layer.

[0279] As illustrated in FIGS. 17 and 18, in the case of the gate conductive layer (GML) according to the conventional embodiment, since the fourth gate conductive layer (GML) includes indium, precipitated particles (PRC) may be precipitated.

[0280] For example, when the third gate conductive layer (GML3) includes titanium, indium atoms of the fourth gate conductive layer (GML4) may be precipitated in the form of particles due to the difference in binding energy (e.g., Gibbs free energy) between titanium oxide and indium oxide. Since titanium oxide has a lower Gibbs free energy than indium oxide, titanium oxide may have a higher binding energy than indium oxide. Accordingly, due to the high temperature generated during the formation of the protective film (PV) or via film (VIA) located on the upper portion of the gate conductive layer (GML), oxygen atoms of the indium-tin-oxide of the fourth gate conductive layer (GML4) according to the conventional embodiment may move toward the titanium oxide. Accordingly, precipitated particles (PRC) may be precipitated on the fourth gate conductive layer (GML).

[0281] As illustrated in FIG. 18, in a display device (10) according to a conventional embodiment, when the second gate conductive layer (GML) includes copper, when indium atoms are precipitated, the indium atoms and copper atoms may combine to form an indium-copper alloy as precipitated particles (PRC).

[0282] The gate conductive layer (GML) according to the present embodiment does not contain indium, thereby preventing the formation of precipitated particles (PRC) containing indium metal or an indium-copper alloy. Accordingly, the reliability of the gate conductive layer (GML) can be improved.

[0283] Hereinafter, the first and second comparative examples and the first embodiment will be described by comparison with reference to Table 1 below. The first and second comparative examples may be gate conductive layers (GML) according to the conventional embodiment described above, and the first embodiment may be gate conductive layers (GML) according to the present embodiment described above.

[0284] Reflectance according to the wavelength of light of the gate conductive layer structure (1 / 2 / 3 / 4 layers) 450 nm 550 nm 650 nm 1st comparative example Ti / Cu / ITO 35.4% 22.3% 62.7% 2nd comparative example Ti / Cu / Ti / ITO 9.7% 23.8% 34% 1st embodiment Ti / Cu / Ti / AZTO 6.32% 4.50% 9.43%

[0285] Referring to Table 1 above, the gate conductive layer (GML) according to the first comparative example may include a stacked structure of Ti / Cu / ITO, the gate conductive layer (GML) according to the second comparative example may include a stacked structure of Ti / Cu / Ti / ITO, and the gate conductive layer (GML) according to the first embodiment may include a stacked structure of Ti / Cu / Ti / AZTO. In the stacked structure of Ti / Cu / ITO, the stacked structure of Ti / Cu / Ti / ITO, and the stacked structure of Ti / Cu / Ti / AZTO, the order listed from left to right may be the order from the lower layer to the upper layer of the gate conductive layer (GML). Since the gate conductive layer (GML) according to the first comparative example does not include a Ti layer, the reflectance reduction effect may hardly occur regardless of the wavelength of light.

[0286] Since the gate conductive layer (GML) according to the second comparative example includes a Ti layer, the reflectivity of the gate conductive layer (GML) according to the second comparative example for light having a wavelength of 450 nm and 650 nm may be lower than the reflectivity of the gate conductive layer (GML) according to the first comparative example for light having a wavelength of 450 nm and 650 nm. However, the reflectivity of the gate conductive layer (GML) according to the second comparative example for light having a wavelength of 550 nm may actually increase compared to the reflectivity of the gate conductive layer (GML) according to the first comparative example for light having a wavelength of 550 nm. In addition, since the gate conductive layer (GML) according to the second comparative example includes both a Ti layer and an ITO layer, as described above, a problem of precipitation of precipitated particles (PRC) may occur.

[0287] On the other hand, the gate conductive layer (GML) according to the first embodiment may have a lower reflectivity for light of all wavelengths than the first and second comparative examples. The gate conductive layer (GML) according to the first embodiment may include a Ti layer and an AZTO layer, thereby reducing the reflectivity of the gate conductive layer (GML). In addition, since the gate conductive layer (GML) according to the first embodiment does not include indium atoms, precipitated particles (PRC) are not precipitated, thereby improving the reliability of the gate conductive layer (GML).

[0288] Hereinafter, other embodiments of a display device according to one embodiment will be described. In the following embodiments, the same components as in the previously described embodiments will be referred to by the same reference numerals, and duplicate descriptions will be omitted or simplified, with the differences being primarily described.

[0289] Fig. 19 is a cross-sectional view showing an example of a portion of a display area and a portion of a pad area of ​​a display device according to another embodiment. Fig. 20 is a cross-sectional view showing a wiring pad and a flexible film of a display device according to another embodiment.

[0290] Referring to FIGS. 19 and 20, the display device (10) according to the present embodiment is different from the display device (10) according to the embodiment described with reference to FIG. 13, etc. in that it does not include a sixth sub-pad (SPD6).

[0291] More specifically, in the display substrate (100_1) of the display device (10) according to the present embodiment, the second pad electrode (PDE2_1) of the wiring pad (WPD) may not include the sixth sub-pad (SPD6) (see FIG. 13). For example, the uppermost layer of the second pad electrode (PDE2_1) of the wiring pad (WPD) may be the fifth sub-pad (SPD5).

[0292] A protective film (PV) disposed on a wiring pad (WPD) may include a through hole for exposing the wiring pad (WPD). A fifth sub-pad (SPD5) may be exposed to the outside through the through hole of the protective film (PV).

[0293] In some embodiments, the connecting film (510) may include a base film (511) and a bump (512). The base film (511) may be a flexible circuit film on which components such as a display driver (520) (see FIG. 4) may be mounted. The bump (512) may be a conductive protrusion protruding from the base film (511) toward a wiring pad (WPD). In the display device (10) according to the present embodiment, the bump (512) of the connecting film (510) may be in direct contact with the fifth sub-pad (SPD5).

[0294] The sixth sub-pad (SPD6) (see FIG. 13) of the display device (10) according to one embodiment described with reference to FIG. 13 and the like may include a metal oxide. On the other hand, the fifth sub-pad (SPD5) of the display device (10) according to the present embodiment may include a metal. Therefore, the wiring pad (WPD) of the display device (10) according to the present embodiment may have superior electrical characteristics than the display device (10) according to one embodiment described with reference to FIG. 13 and the like. Accordingly, the loss of signals and voltages that the display substrate (100_1) receives from or provides to the connection film (510) may be reduced or minimized.

[0295] In the drawing, the case where the connecting film (510) is connected to the wiring pad (WPD) is described as an example, but it is not limited thereto. For example, the same technical idea can be applied even when the display driving unit (520) (see FIG. 4) and / or the circuit board (530) (see FIG. 4) described with reference to FIGS. 4 and 5 are connected to the wiring pad (WPD). Components connected to the wiring pad (WPD), such as the connecting film (510), the display driving unit (520) (see FIG. 4), and the circuit board (530) (see FIG. 4), can be referred to as driving components.

[0296] FIGS. 21 to 23 are schematic perspective views showing a device including a display device according to one embodiment.

[0297] Fig. 21 illustrates a virtual reality device (1) to which a display device (10) according to one embodiment is applied. Fig. 22 illustrates a smart watch (2) to which a display device (10) according to one embodiment is applied. Fig. 23 illustrates a display device (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment being applied to a display unit of an automobile.

[0298] Referring to FIG. 21, a virtual reality device (1) according to one embodiment may be a device in the form of glasses. The virtual reality device (1) according to one embodiment may include a display device (10), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), glasses frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0299] Although the drawing illustrates a virtual reality device (1) including eyeglass frame legs (30a, 30b), the virtual reality device (1) according to one embodiment may be applied to a head-mounted display including a head-mounted band that can be mounted on the head instead of the eyeglass frame legs (30a, 30b). The virtual reality device (1) according to one embodiment is not limited to the structure illustrated in the drawing, and may be applied in various forms to various other electronic devices.

[0300] The display device housing (50) may include a display device (10) and a reflective member (40). An image displayed on the display device (10) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10) through the right eye.

[0301] The display device housing (50) may be disposed at the right end of the support frame (20), but is not limited thereto. For example, the display device housing (50) may be disposed at the left end of the support frame (20), and the image displayed on the display device (10) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10) through the left eye. Alternatively, the display device housing (50) may be disposed at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10) through both the left eye and the right eye.

[0302] Referring to FIG. 22, a display device (10) according to one embodiment can be applied to a smart watch (2), which is one of smart devices.

[0303] Referring to FIG. 23, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0304] FIGS. 24 and 25 are schematic perspective views showing a transparent display device including a display device according to one embodiment.

[0305] Referring to FIGS. 24 and 25, a display device (10) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. A user positioned at the front of the transparent display device can view the image (IM) displayed on the display device (10) as well as an object (RS) or background positioned at the back of the transparent display device.

[0306] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A first conductive layer disposed on the above substrate; An active layer disposed on the first challenge layer; A second conductive layer disposed on the active layer, comprising a transparent conductive oxide (TCO) and not containing indium (In); A third conductive layer disposed on the second conductive layer; A transistor including a gate electrode disposed in the second conductive layer, and a drain electrode and a source electrode disposed in the active layer; and A display device comprising a light-emitting element including a first electrode disposed on the third conductive layer and connected to the source electrode.

2. In paragraph 1, A display device wherein the second conductive layer comprises aluminum-zinc-tin-oxide (AZTO).

3. In paragraph 1, The second conductive layer includes a first gate conductive layer and a second gate conductive layer disposed on the first gate conductive layer, A display device wherein the second gate conductive layer has higher light transmittance than the first gate conductive layer.

4. In paragraph 3, A display device wherein the second gate conductive layer includes aluminum-zinc-tin-oxide (AZTO).

5. In paragraph 4, A display device wherein the second gate conductive layer contains aluminum in an amount of 1 at% to 10 at% relative to the remaining atoms excluding oxygen atoms.

6. In paragraph 4, A display device wherein the second gate conductive layer contains zinc in an amount of 60 to 90 at% relative to the remaining atoms excluding oxygen atoms.

7. In paragraph 4, A display device wherein the second gate conductive layer contains tin in an amount of 10 to 30 at% relative to the remaining atoms excluding oxygen atoms.

8. In paragraph 4, A display device, wherein the second gate conductive layer contains aluminum in an amount of 0.5 at% to 5 at% relative to the total atoms.

9. In paragraph 4, A display device wherein the second gate conductive layer contains zinc in an amount of 20 at% to 40 at% relative to the total atoms.

10. In paragraph 4, A display device, wherein the second gate conductive layer contains 7 at% to 15 at% of tin relative to the total atoms.

11. In paragraph 4, A display device wherein the second gate conductive layer contains oxygen at 50 at% to 60 at% relative to the total atoms.

12. In paragraph 3, A display device wherein the first gate conductive layer has a lower reflectivity than the second gate conductive layer.

13. In paragraph 12, A display device wherein the first gate conductive layer includes titanium (Ti).

14. In paragraph 3, A display device wherein the thickness of the second gate conductive layer is thicker than the thickness of the first gate conductive layer.

15. In paragraph 14, A display device wherein the thickness of the second gate conductive layer is 2 to 30 times the thickness of the first gate conductive layer.

16. In paragraph 15, A display device wherein the thickness of the second gate conductive layer is 400Å to 3000Å.

17. In paragraph 15, A display device wherein the thickness of the first gate conductive layer is 100 Å to 200 Å.

18. In paragraph 1, The third conductive layer comprises a transparent conductive oxide (TCO), A display device wherein the transparent conductive oxide (TCO) of the second conductive layer and the transparent conductive oxide (TCO) of the third conductive layer are different materials.

19. In paragraph 1, A display device wherein the second conductive layer has a lower reflectivity than the first conductive layer or the third conductive layer.

20. Substrate; A first conductive layer disposed on the above substrate; An active layer disposed on the first challenge layer; A second conductive layer disposed on the active layer; A transistor disposed on the first conductive layer; and A light emitting element is disposed on the second conductive layer and is connected to the transistor, The second challenge layer is, A first gate conductive layer comprising a first material, A second gate conductive layer disposed on the first gate conductive layer and including a second material, A third gate conductive layer disposed on the second gate conductive layer and including a third material, and A fourth gate conductive layer is disposed on the third gate conductive layer and includes aluminum-zinc-tin-oxide (AZTO). A display device wherein the first to third materials include metal.

21. In paragraph 20, A display device in which the first to third materials include one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

22. In paragraph 21, The above first material is a display device including titanium (Ti).

23. In paragraph 21, The second material is a display device including copper (Cu).

24. In paragraph 21, The third material is a display device including titanium (Ti).

25. In paragraph 20, A display device wherein the thickness of the fourth gate conductive layer is thicker than the thickness of the third gate conductive layer.

26. In paragraph 20, A display device wherein the thickness of the second gate conductive layer is thicker than the thickness of the fourth gate conductive layer.

27. A substrate including a display area and a pad area arranged on one side of the display area; A first conductive layer disposed on the above substrate; An active layer disposed on the first challenge layer; A second conductive layer disposed on the active layer, comprising a transparent conductive oxide in the display area, and not containing indium (In); A transistor disposed on the first conductive layer in the display area; A light emitting element disposed on the second conductive layer in the display area and connected to the transistor; and Including a wiring pad arranged on the substrate in the above pad area, A display device wherein the wiring pad includes a first pad electrode disposed on the first conductive layer and a second pad electrode disposed on the second conductive layer.

28. In paragraph 27, A display device wherein the second pad electrode does not include a transparent conductive oxide.

29. In paragraph 27, Further comprising a driving component connected to the above wiring pad, A display device in which the second pad electrode is in direct contact with the driving component and includes a sub-pad layer including a metal.

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